CN101788974A - Variable point FFT/IFFT operation method, device and system - Google Patents
Variable point FFT/IFFT operation method, device and system Download PDFInfo
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Abstract
The embodiment of the invention discloses a variable point FFT/IFFT operation method, a variable point FFT/IFFT operation device and a variable point FFT/IFFT operation system, relates to the field of a signal processing technique, and solves the problem of long processing delay of the FFT/IFFT. The method comprises the following steps: sequentially reading two pieces of data from a first RAM corresponding to each butterfly arithmetic element to the corresponding butterfly arithmetic element in the each grade of butterfly operation of former m-grade butterfly operation, and writing a data former address after the butterfly operation back to the first RAM; sequentially reading the two pieces of data from a second RAM corresponding to each butterfly arithmetic element to the corresponding butterfly arithmetic element, and writing the data former address after the butterfly operation back to the second RAM; and respectively reading one piece of data from the two RAMs corresponding to each butterfly arithmetic element to the corresponding butterfly arithmetic element in the each grade of butterfly operation from m+1-grade to n-grade butterfly operation, and writing the data former address after the butterfly operation back to the two corresponding RAMs.
Description
Technical field
The present invention relates to the signal processing technology field, relate in particular to a kind of running point FFT/IFFT operational method, Apparatus and system.
Background technology
In the communications field, often require to do the FFT/IFFT computing (Fast Fourier Transform (FFT)/inverse fast Fourier transform) that difference is counted, even the different moment in same system need be finished the FFT/IFFT computing that difference is counted according to different demands.ASIC (Application SpecificIntegrated Circuit as the multimode intermediate frequency, special IC) in the chip, need be to UMTS (Universal MobileTelecommunication System, universal mobile telecommunications system), CDMA (Code Division MultipleAddressing, CDMA), LTE (Long Term Evolution, a kind of Long Term Evolution of 3G mobile communication), one or several standards in the GSM various standards such as (Global System for Mobile communications, global system for mobile communicationss) are handled simultaneously.Under the situation of LTE standard single carrier, need be AWPC slicing (Adaptive Weight Peak Cancellation, the adaptive weighting slicing), because LTE comprises various bandwidth mode such as 1.4M, 3M, 5M, 10M, 15M, 20M, this is just need do 256 points, 512 points, 1024 points, 2048 FFT/IFFT computings according to the different bandwidth mode of LTE, and processing delay must be controlled within the symbol of 2 LTE.
The typical structure of realizing 2048,1024,512 running point FFT/IFFT in the prior art as shown in Figure 1, the structure of this running point FFT/IFFT is based on order and imports inverted order output.
Wherein x (n) expression input etc. the data of pending FFT computing.Clk represents work clock.FFT counts to indicate and is used to indicate counting of FFT.The output of x (k) expression FFT, 1024 outputs separately, 2048 and 512 the public same output of FFT.
Be expressed as a degree of depth and be 1024 or 512 FIFO, the degree of depth is definite according to counting of FFT.The function of other similar pattern is identical among Fig. 1.
With
Be respectively the FFT butterfly computing unit of two kinds of different structures.
The 10bit/9bit of the counter of expression 10bit/9bit.The bit wide of counter is counted definite by FFT, the similar pattern function is identical among Fig. 1.
Yet the inventor finds that when adopting said structure to carry out the running point computing, because this structure adopts serial structure to organize FFT butterfly computing unit, the delay of deal with data is longer in the FFT calculating process.As when doing the running point FFT/IFFT computing of LTE single carrier AWPC slicing, can surpass the symbol of 2 LTE.
Summary of the invention
Embodiments of the invention provide a kind of running point FFT/IFFT operational method, Apparatus and system, when carrying out running point FFT/IFFT computing, have reduced the processing delay of running point FFT/IFFT.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of running point FFT arithmetic unit comprises:
2
N-mThe individual degree of depth is 2
mRAM, be used to deposit 2
nPoint data, described every point data are stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately;
2
N-m-1Individual butterfly processing element is used for read-write control unit is carried out butterfly computation successively from the data that described RAM reads;
Read-write control unit, be used for every grade of butterfly computation at preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
A kind of running point FFT/IFFT operational method, wherein 2
nPoint data leaves 2 in
N-mThe individual degree of depth is 2
mRAM in, described every point data is stored in respectively separately in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation, this method comprises:
In every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
A kind of FFT/IFFT disposal system comprises:
The FFT arithmetic unit is used for 2
N-mThe individual degree of depth is 2
mRAM in deposit 2
nPoint data, described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately, in every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence;
Address conversion device is used for the default OPADD of FFT arithmetic unit is carried out the Input Address that the bit-reversed operation obtains the IFFT arithmetic unit;
The IFFT arithmetic unit, be used for to write from the data that the default OPADD of FFT arithmetic unit is read the Input Address of the IFFT arithmetic unit that address conversion device draws, in every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
Running point FFT/IFFT device, operational method and system that the embodiment of the invention provides are by carrying out 2 of FFT/IFFT computing with needs
nEvery point data in the point data is stored in respectively separately in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation, and then 2
N-m-1Individual butterfly processing element carries out butterfly computation successively to the data that read-write control unit is read from described RAM.Wherein, in every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
Because in every grade of butterfly computation, each butterfly processing element all carries out butterfly computation with read-write control unit reading of data from each self-corresponding RAM of described each butterfly processing element at the same time, and each butterfly computation write back the former address as a result, last data in each self-corresponding RAM of described each butterfly processing element are carried out butterfly computation, and finish last data behind this butterfly computation are write back among the RAM of above-mentioned correspondence, just begin to carry out the butterfly computation of next stage.Just each butterfly processing element in the running point FFT/IFFT device in the embodiment of the invention is parallel pipelining process work, compares with the running point FFT/IFFT device of available technology adopting serial structure, has reduced the processing delay of FFT/IFFT computing.
Simultaneously, by the described FFT/IFFT disposal system of the embodiment of the invention, at first with 2
nPoint data is carried out the FFT computing, then by address conversion device just the default OPADD of FFT arithmetic unit carry out the Input Address that bit-reversed operation obtains the IFFT arithmetic unit, each point data of from above-mentioned RAM, reading according to the default OPADD of FFT arithmetic unit, Input Address according to the IFFT arithmetic unit writes, and carries out the IFFT computing then.Owing to incite somebody to action 2 of order input in the FFT arithmetic unit
nPoint data leaves in according in the bit-reversed address that the corresponding address in above-mentioned RAM of order carries out obtaining after the bit-reversed operation separately, the Input Address that draws by above-mentioned address conversion device can guarantee that each point data still deposits in corresponding address in above-mentioned RAM, this each point data of reading will then carried out the IFFT computing as the input data of IFFT arithmetic unit then.Directly alphabetic data being imported the inverted order data that the FFT arithmetic unit draws compared with prior art reads, be alphabetic data by adjusting these inverted order data of reading again, and then input IFFT arithmetic unit carries out the IFFT computing and compares, and the data processing that has reduced the FFT/IFFT disposal system postpones.
In addition since in the embodiment of the invention by directly data being read in the IFFT arithmetic unit from the FFT arithmetic unit behind the address mapping, be 2 with adopting the degree of depth when adjusting these inverted order data of reading in the prior art for alphabetic data
nRAM preserve need to adjust 2
nPoint data is compared, and has reduced the amount of expending of hardware resource.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural drawing of prior art running point FFT/IFFT;
Fig. 2 is the structured flowchart of embodiment 1 running point FFT arithmetic unit;
Fig. 3 is the process flow diagram of embodiment 1 running point FFT/IFFT operational method;
Fig. 4 is the structural drawing of FFT/IFFT disposal system among the embodiment 1;
Fig. 5 is the structured flowchart of embodiment 2 running point FFT arithmetic units;
Fig. 6 is the precedence diagram of depositing of 2048 point data among the embodiment 2;
Fig. 7 is the FFT operational flowchart of 2048 point data among the embodiment 2;
Fig. 8 is the precedence diagram of depositing of 1024 point data among the embodiment 2;
Fig. 9 is the FFT operational flowchart of 1024 point data among the embodiment 2;
Figure 10 is the precedence diagram of depositing of 512 point data among the embodiment 2;
Figure 11 is the FFT operational flowchart of 512 point data among the embodiment 2;
Figure 12 is the precedence diagram of depositing of 256 point data among the embodiment 2;
Figure 13 is the FFT operational flowchart of 256 point data among the embodiment 2;
Figure 14 is the synoptic diagram that embodiment 2FFT arithmetic unit is handled multichannel data;
Figure 15 is the process flow diagram of embodiment 2 running point FFT/IFFT operational methods;
Figure 16 is the structural drawing of FFT/IFFT disposal system among the embodiment 2.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Embodiment 1:
The embodiment of the invention provides a kind of running point FFT arithmetic unit, and as shown in Figure 2, this device comprises: the degree of depth is 2
mRAM11, butterfly processing element 12 and read-write control unit 13.
Wherein, 2
N-mThe individual degree of depth is 2
mRAM11, be used to deposit 2
nPoint data, described every point data are stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately.The each point data storage addresses is changeless in carrying out the butterfly computation process.
2
N-m-1Individual butterfly processing element 12 is used for read-write control unit is carried out butterfly computation successively from the data that described RAM reads;
Read-write control unit 13, be used for every grade of butterfly computation at preceding m level butterfly computation, from each butterfly processing element 12 each self-corresponding RAM, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each butterfly processing element 12 each self-corresponding the 2nd RAM, read the butterfly processing element 12 of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each butterfly processing element 12 each self-corresponding two RAM, read the butterfly processing element 12 of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
Because each butterfly processing element in the running point FFT device in the embodiment of the invention is parallel pipelining process work.In every grade of butterfly computation, each butterfly processing element all carries out butterfly computation with read-write control unit reading of data from each self-corresponding RAM of described each butterfly processing element at the same time, and each butterfly computation write back the former address as a result, up to the butterfly computation of finishing each point data.In the processing procedure of whole running point FFT device, each butterfly processing element is in running order always, has improved the efficient of butterfly computation.Compare with the running point FFT device of available technology adopting serial structure, reduced the processing delay of FFT computing.
The embodiment of the invention also provides a kind of running point FFT/IFFT operational method, as shown in Figure 3, and wherein 2
n Point data leaves 2 in
N-mThe individual degree of depth is 2
mRAM in, described every point data is stored in respectively separately in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation, this method comprises:
201, in every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.
202, in every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
In above-mentioned every grade of butterfly computation from the first order to the n level butterfly computation, each butterfly processing element all carries out butterfly computation with read-write control unit reading of data from each self-corresponding RAM of described each butterfly processing element at the same time, and each butterfly computation write back the former address as a result, last data in each self-corresponding RAM of described each butterfly processing element are carried out butterfly computation, and finish last data behind this butterfly computation are write back among the RAM of above-mentioned correspondence, just begin to carry out the butterfly computation of next stage.Can avoid data when read-write, to produce conflict like this.Each butterfly processing element in the running point FFT device in the embodiment of the invention is parallel pipelining process work, compares with the running point FFT device of available technology adopting serial structure, has reduced the processing delay of FFT computing.
A kind of FFT/IFFT disposal system, as shown in Figure 4, this system comprises: FFT arithmetic unit 31, address conversion device 32 and IFFT arithmetic unit 33.
Wherein, FFT arithmetic unit 31 is used for 2
N-mThe individual degree of depth is 2
mRAM in deposit 2
nPoint data, described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately, in every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
The data that IFFT arithmetic unit 33 is used for reading from the default OPADD of FFT arithmetic unit write the Input Address of the IFFT arithmetic unit that address conversion device draws, in every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
Owing to incite somebody to action 2 of order input in the FFT arithmetic unit
nPoint data leaves in according in the bit-reversed address that the corresponding address in above-mentioned RAM of order carries out obtaining after the bit-reversed operation separately, can guarantee that by the Input Address that above-mentioned address conversion device draws each point data of reading still is written to this address of data correspondence in above-mentioned RAM from above-mentioned RAM, this each point data of reading will then be carried out the IFFT computing again as the input data of IFFT arithmetic unit then.Directly alphabetic data being imported the inverted order data that the FFT arithmetic unit draws compared with prior art reads, be alphabetic data by adjusting these inverted order data of reading again, and then input IFFT arithmetic unit carries out the IFFT computing and compares, and the data processing that has reduced the FFT/IFFT disposal system postpones.In addition since in the embodiment of the invention by directly data being read in the IFFT arithmetic unit from the FFT arithmetic unit behind the address mapping, be 2 with adopting the degree of depth when adjusting these inverted order data of reading in the prior art for alphabetic data
nRAM preserve need to adjust 2
nPoint data is compared, and has reduced the amount of expending of hardware resource.
Embodiment 2:
In the embodiment of the invention 2
nPoint data when carrying out the FFT computing, described 2
nPoint data deposits in 2
N-mThe individual degree of depth is 2
mRAM in, n 〉=m wherein.Suppose that application scenarios need carry out the FFT computing of 2048 points, 1024 points, and 256 point data at 512, the degree of depth of the RAM that adopts is 128, and this moment, the value of m was 7.At first, be that example is introduced a kind of running point FFT arithmetic unit in detail with 2048 FFT computings, this moment, the value of n was 11.As shown in Figure 5, this device comprises: the degree of depth is 128 RAM41, butterfly processing element 42, read-write control unit 43, input block 44, selection control module 45 and output unit 46.
Wherein, input block 44 is used for importing the address that 2048 point data are 128 RAM 16 degree of depth to each point data correspondence in proper order by default write port.As writing data simultaneously, in 256 clock period, just can finish the input of 2048 point data by 8 default write ports.16 degree of depth are 128 RAM41, are used to deposit 2048 point data, and described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately.As shown in Figure 6, described 2048 point data leave among 16 128RAM41 according to each self-corresponding bit-reversed address, and the each point data storage addresses is changeless in carrying out the butterfly computation process.
8 butterfly processing elements 42 are used for read-write control unit is carried out butterfly computation successively from the data that described RAM41 reads.Above-mentioned 2048 point data need be carried out 11 grades of butterfly computations.
Whole butterfly computation process can be divided into two stages.As shown in Figure 7, the phase one is: in every grade of butterfly computation of described preceding 7 grades of butterfly computations, and the corresponding butterfly processing element of every adjacent two RAM.Read-write control unit 43 is used for every grade of butterfly computation at preceding 7 grades of butterfly computations, from each butterfly processing element 42 each self-corresponding RAM, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each butterfly processing element 42 each self-corresponding the 2nd RAM, read the butterfly processing element 42 of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.As shown in Figure 7,16 RAM represent with RAM0 to RAM15 that respectively 8 butterfly processing elements are represented with BF0 to BF7 respectively.In first order butterfly computation, RAM0 and RAM1 are two adjacent RAM, so the multiplexing butterfly processing element BF0 of RAM0 and RAM1, this moment, the one RAM of butterfly processing element BF0 correspondence was RAM0, and the 2nd corresponding RAM is RAM1.Read-write control unit 43 can read two data to this butterfly processing element BF0 from the RAM0 of butterfly processing element BF0 correspondence, and the data former address behind the butterfly computation is write back RAM0; From the RAM1 of butterfly processing element BF0 correspondence, read the butterfly processing element BF0 of two data, and the data former address behind the butterfly computation is write back RAM1 to correspondence.It is the data behind the butterfly computation to be write back to these data in the stored address, make that the each point data storage addresses is changeless in carrying out the butterfly computation process before computing that back operations is write in this former address.Other butterfly processing element BF1 to BF7 calculating process is similar, does not repeat them here.
Subordinate phase is: every grade of butterfly computation in described the 8th grade to the 11st grade butterfly computation is expressed as: 7+x level butterfly computation, described x value are the integer between 1 to 4, in described 7+x level butterfly computation, with every adjacent 2
xIndividual RAM is divided into one group, and each RAM in described each group being divided equally in proper order according to described each RAM position is the first son group and the first son group again, and all comprise 2 in each son group this moment
X-1Individual RAM.The corresponding butterfly processing element of i RAM in i RAM in the described first son group and described second sub the group.Wherein, 2
X-1〉=i 〉=1.In every grade of butterfly computation of read-write control unit 43 in the 8th grade to the 11st grade butterfly computation, read the butterfly processing element 42 of data respectively from each butterfly processing element 42 each self-corresponding two RAM respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.As shown in Figure 7, in the 9th grade of butterfly computation, the x value is 2, this moment, every adjacent 4 RAM were divided into one group, each RAM in described each group being divided equally in proper order according to described each RAM position is the first son group and the first son group again, as in 4 RAM of first group, RAM0 and RAM1 are the first son group, and RAM2 and RAM3 are the second son group.First RAM0 in the described first son group and the corresponding butterfly processing element BF0 of first RAM2 during described second son is organized, equally, second RAM1 in the described first son group and the corresponding butterfly processing element BF1 of second RAM3 during described second son is organized.Read-write control unit 43 reads the butterfly processing element BF0 of data to correspondence respectively, and the data former address behind the butterfly computation is write back among the RAM0 and RAM2 of described correspondence in the 9th grade of butterfly computation from the RAM0 of butterfly processing element BF0 correspondence and RAM2.Other butterfly processing element BF1 to BF7 calculating process is similar, does not repeat them here.
It is the assigned address sense data of 128 RAM from 16 degree of depth that output unit 46 is used for by default read port.Described assigned address can be decided according to the data of user's request, such as reading 160 point data according to user's needs.Compare with output fixed order in the prior art, satisfied personalized output demand.
Because each butterfly processing element in the running point FFT arithmetic unit in the embodiment of the invention is parallel pipelining process work.In every grade of butterfly computation, each butterfly processing element all carries out butterfly computation with read-write control unit reading of data from each self-corresponding RAM of described each butterfly processing element at the same time, and each butterfly computation write back the former address as a result, up to the butterfly computation of finishing each point data.In the processing procedure of whole running point FFT arithmetic unit, each butterfly processing element is in running order always, has improved the efficient of butterfly computation.Compare with the running point FFT arithmetic unit of available technology adopting serial structure, reduced the processing delay of FFT computing.
In addition, in the described running point FFT of the embodiment of the invention arithmetic unit, can also carry out the FFT computing of 1024 points, and 256 point data at 512.
When the FFT computing of carrying out 1024 point data, it is address among 128 the RAM to each point data correspondence 8 degree of depth that described input block 44 is imported 1024 point data in proper order by default write port.As writing data simultaneously, in 256 clock period, just can finish the input of 1024 point data by 4 default write ports.8 degree of depth are 128 RAM41, are used to deposit 1024 point data, and as shown in Figure 8, described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately.
4 butterfly processing elements 42 are used for read-write control unit is carried out butterfly computation successively from the data that described RAM41 reads.Above-mentioned 1024 point data need be carried out 10 grades of butterfly computations.
Whole butterfly computation process can be divided into two stages.As shown in Figure 9, the phase one is: in every grade of butterfly computation of described preceding 7 grades of butterfly computations, and the corresponding butterfly processing element of every adjacent two RAM.Read-write control unit 43 is used for every grade of butterfly computation at preceding 7 grades of butterfly computations, from each butterfly processing element 42 each self-corresponding RAM, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each butterfly processing element 42 each self-corresponding the 2nd RAM, read the butterfly processing element 42 of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.
Subordinate phase is: every grade of butterfly computation in described the 8th grade to the 10th grade butterfly computation is expressed as: 7+x level butterfly computation, described x value are the integer between 1 to 3, in described 7+x level butterfly computation, with every adjacent 2
xIndividual RAM is divided into one group, and each RAM in described each group being divided equally in proper order according to described each RAM position is the first son group and the first son group again, and all comprise 2 in each son group this moment
X-1Individual RAM.The corresponding butterfly processing element of i RAM in i RAM in the described first son group and described second sub the group.In every grade of butterfly computation of read-write control unit 43 in the 8th grade to the 10th grade butterfly computation, from each butterfly processing element 42 each self-corresponding two RAM, read the butterfly processing element 42 of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
When the FFT computing of carrying out 512 point data, it is address among 128 the RAM to each point data correspondence 4 degree of depth that described input block 44 is imported 512 point data in proper order by default write port.As writing data simultaneously, in 256 clock period, just can finish the input of 512 point data by 2 default write ports.4 degree of depth are 128 RAM41, are used to deposit 512 point data, and as shown in figure 10, described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately.
2 butterfly processing elements 42 are used for read-write control unit is carried out butterfly computation successively from the data that described RAM41 reads.Above-mentioned 512 point data need be carried out 9 grades of butterfly computations.
Whole butterfly computation process can be divided into two stages.As shown in figure 11, the phase one is: in every grade of butterfly computation of described preceding 7 grades of butterfly computations, and the corresponding butterfly processing element of every adjacent two RAM.Read-write control unit 43 is used for every grade of butterfly computation at preceding 7 grades of butterfly computations, from each butterfly processing element 42 each self-corresponding RAM, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each butterfly processing element 42 each self-corresponding the 2nd RAM, read the butterfly processing element 42 of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.
Subordinate phase is: every grade of butterfly computation in described the 8th grade to the 9th grade butterfly computation is expressed as: 7+x level butterfly computation, described x value is 1 or 2, in described 7+x level butterfly computation, with every adjacent 2
xIndividual RAM is divided into one group, and each RAM in described each group being divided equally in proper order according to described each RAM position is the first son group and the first son group again, and all comprise 2 in each son group this moment
X-1Individual RAM.The corresponding butterfly processing element of i RAM in i RAM in the described first son group and described second sub the group.In every grade of butterfly computation of read-write control unit 43 in the 8th grade to the 9th grade butterfly computation, read the butterfly processing element 42 of data respectively from each butterfly processing element 42 each self-corresponding two RAM respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
When the FFT computing of carrying out 256 point data, it is address among 128 the RAM to each point data correspondence 2 degree of depth that described input block 44 is imported 256 point data in proper order by default write port.As writing data, in 256 clock period, just can finish the input of 256 point data by 1 default write port.2 degree of depth are 128 RAM41, are used to deposit 256 point data, and as shown in figure 12, described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately.
1 butterfly processing element 42 is used for read-write control unit is carried out butterfly computation successively from the data that described RAM41 reads.Above-mentioned 256 point data need be carried out 8 grades of butterfly computations.
Whole butterfly computation process can be divided into two stages.As shown in figure 13, the phase one is: in every grade of butterfly computation of described preceding 7 grades of butterfly computations, and the corresponding butterfly processing element of every adjacent two RAM.Read-write control unit 43 is used for every grade of butterfly computation at preceding 7 grades of butterfly computations, from each butterfly processing element 42 each self-corresponding RAM, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each butterfly processing element 42 each self-corresponding the 2nd RAM, read the butterfly processing element 42 of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.
Subordinate phase is: described the 8th grade of butterfly computation is expressed as: 7+x level butterfly computation, described x value is 1, in described the 8th grade of butterfly computation, every adjacent 2 RAM are divided into one group, each RAM in described each group being divided equally in proper order according to described each RAM position is the first son group and the first son group again, and all comprise 2 in each son group this moment
X-1Individual RAM.The corresponding butterfly processing element of i RAM in i RAM in the described first son group and described second sub the group.Read-write control unit 43 is in the 8th grade of butterfly computation, read the butterfly processing element 42 of data respectively from each butterfly processing element 42 each self-corresponding two RAM respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
The running point FFT arithmetic unit that the embodiment of the invention provided can also be handled 1024 FFT computings of 2 passages simultaneously under the constant situation of resource, 512 FFT computings of 4 passages, 256 FFT computings of 8 passages, the specific implementation process as shown in figure 14.Compared with prior art, can realize the maximum using of resource.As can be implemented in 256 FFT/IFFT computings of 8 passages in the trap under the UMTS and CDMA standard in the multimode intermediate frequency project.
The embodiment of the invention also provides a kind of running point FFT/IFFT operational method, as shown in figure 15, is that example is introduced in detail with the FFT calculating process of 2048 point data, and this method comprises the steps:
501, importing 2048 point data in proper order by default write port is address among 128 the RAM to each point data correspondence 16 degree of depth.As writing data simultaneously, in 256 clock period, just can finish the input of 2048 point data by 8 default write ports.Described 16 degree of depth are that 128 RAM is used to deposit 2048 point data, and described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately.
502, above-mentioned 2048 point data need be carried out 11 grades of butterfly computations.Carry out butterfly computation successively by the data that 8 butterfly processing elements are read from described RAM read-write control unit.
Whole butterfly computation process can be divided into two stages.Phase one is: in every grade of butterfly computation of described preceding 7 grades of butterfly computations, and the corresponding butterfly processing element of every adjacent two RAM.In every grade of butterfly computation of preceding 7 grades of butterfly computations, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.
Subordinate phase is: every grade of butterfly computation in described the 8th grade to the 11st grade butterfly computation is expressed as: 7+x level butterfly computation, described x value are the integer between 1 to 4, in described 7+x level butterfly computation, with every adjacent 2
xIndividual RAM is divided into one group, and each RAM in described each group being divided equally in proper order according to described each RAM position is the first son group and the first son group again, and all comprise 2 in each son group this moment
X-1Individual RAM.The corresponding butterfly processing element of i RAM in i RAM in the described first son group and described second sub the group.In every grade of butterfly computation in the 8th grade to the 11st grade butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
Carry out data when input at input block in the above-mentioned steps 501, forbid in the step 502 above-mentioned RAM being carried out data read-write operation by selecting control module, otherwise when the data read-write operation that read-write control unit is correlated with, forbid that input block carries out the input of data.Thereby produce data collision in the time of can avoiding carrying out when in RAM, writing data and in the step 502 in the step 501 in the butterfly computation process corresponding RAM read and write.
503, be sense data the assigned address of 128 RAM by default read port from 16 degree of depth.Described assigned address can be decided according to the data of user's request, such as reading 160 point data according to user's needs.Compare with output fixed order in the prior art, satisfied personalized output demand.
Each butterfly processing element in the running point FFT device that adopts in the embodiment of the invention is parallel pipelining process work, compares with the running point FFT device of available technology adopting serial structure, has reduced the processing delay of FFT computing.Other data handling procedures of counting are similar, do not repeat them here.
The FFT arithmetic unit that the embodiment of the invention provides can also be applied in the FFT/IFFT disposal system, and as shown in figure 16, described FFT/IFFT disposal system comprises: FFT arithmetic unit 61, address conversion device 62 and I FFT arithmetic unit 63.
Wherein, it is that 128 RAM deposits 2048 point data that FFT arithmetic unit 61 is used for 16 degree of depth, described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately, in every grade of butterfly computation of preceding 7 grades of butterfly computations, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.
In every grade of butterfly computation in the 8th grade to the 11st grade butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
The data that IFFT arithmetic unit 63 is used for reading from the default OPADD of FFT arithmetic unit write the Input Address of the IFFT arithmetic unit that address conversion device draws, because after the FFT computing, what deposit in the address 1 as above-mentioned RAM is that sequence number is 1 data, read sequence number this moment from address 1 be 1 data, and write in the address 1024, thereby guaranteed that each point data still leaves in the corresponding address ram.In every grade of butterfly computation of preceding 7 grades of butterfly computations, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence.
In every grade of butterfly computation in the 8th grade to the 11st grade butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
Because 2048 point data that will import in proper order in the FFT arithmetic unit leave in according in the bit-reversed address that the corresponding address in above-mentioned RAM of order carries out obtaining after the bit-reversed operation separately, can guarantee that by the Input Address that above-mentioned address conversion device draws each point data of reading still is written to this address of data correspondence in above-mentioned RAM from above-mentioned RAM, this each point data of reading will then be carried out the IFFT computing again as the input data of IFFT arithmetic unit then.Directly alphabetic data being imported the inverted order data that the FFT arithmetic unit draws compared with prior art reads, be alphabetic data by adjusting these inverted order data of reading again, and then input IFFT arithmetic unit carries out the IFFT computing and compares, and the data processing that has reduced the FFT/IFFT disposal system postpones.
In addition, since in the embodiment of the invention by directly data being read in the IFFT arithmetic unit from the FFT arithmetic unit behind the address mapping, with adopting the degree of depth in the prior art when adjusting these inverted order data of reading for alphabetic data is that 2048 RAM preserves 2048 point data that need to adjust and compares, and has reduced the amount of expending of hardware resource.
The embodiment of the invention is mainly used in the signal processing system, if with the degree of depth in the embodiment of the invention is that 128 RAM is divided into littler storage unit, can also realize 128 FFT/IFFT of 16 passages equally, 64 FFT/IFFT of 32 passages, 32 FFT/IFFT of 64 passages or the like.The embodiment of the invention has solved the problem that processing delay is grown in carrying out the FFT/IFFT calculating process in the prior art.
Through the above description of the embodiments, the those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential common hardware, can certainly pass through hardware, but the former is better embodiment under a lot of situation.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium that can read, floppy disk as computing machine, hard disk or CD etc., comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (10)
1. a running point FFT arithmetic unit is characterized in that, comprising:
2
N-mThe individual degree of depth is 2
mRAM, be used to deposit 2
nPoint data, described every point data are stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately;
2
N-m-1Individual butterfly processing element is used for read-write control unit is carried out butterfly computation successively from the data that described RAM reads;
Read-write control unit is used for every grade of butterfly computation at preceding m level butterfly computation, reads the butterfly processing element of two data to correspondence successively from each self-corresponding RAM of each butterfly processing element, and the data former address behind the butterfly computation is write back
The one RAM; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
2. running point FFT arithmetic unit according to claim 1 is characterized in that,
In every grade of butterfly computation of described preceding m level butterfly computation, the corresponding butterfly processing element of every adjacent two RAM,
Every grade of butterfly computation in described m+1 level to the n level butterfly computation is expressed as: m+x level butterfly computation, described x value are the integer between 1 to n-m, in described m+x level butterfly computation, with every adjacent 2
xIndividual RAM is divided into one group, each RAM in described each group being divided equally in proper order according to described each RAM position is the first son group and the first son group again, the corresponding butterfly processing element of i RAM in i RAM in the described first son group and described second sub the group.
3. running point FFT arithmetic unit according to claim 1 is characterized in that, also comprises:
Input block is used for importing 2 in proper order by default write port
nPoint data arrives each point data correspondence 2
N-mThe individual degree of depth is 2
mRAM in the address.
4. running point FFT arithmetic unit according to claim 1 is characterized in that, also comprises:
Output unit is used for by default read port from 2
N-mThe individual degree of depth is 2
mThe assigned address of RAM in sense data.
5. running point FFT arithmetic unit according to claim 3 is characterized in that, also comprises:
Select control module, be used to control input block and read-write control unit and carry out asynchronous operation.
6. a running point FFT/IFFT operational method is characterized in that 2
nPoint data leaves 2 in
N-mThe individual degree of depth is 2
mRAM in, described every point data is stored in respectively separately in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation, this method comprises:
In every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
7. running point FFT/IFFT operational method according to claim 6 is characterized in that, also comprises: import 2 in proper order by default write port
nPoint data arrives each point data correspondence 2
N-mThe individual degree of depth is 2
mRAM in the address.
8. running point FFT/IFFT operational method according to claim 6 is characterized in that, also comprises: by presetting read port from 2
N-mThe individual degree of depth is 2
mThe assigned address of RAM in sense data.
9. running point FFT/IFFT operational method according to claim 7 is characterized in that, also comprises: control input 2
nAsynchronous carrying out between the operation of point data and the read-write operation when carrying out butterfly computation.
10. a FFT/IFFT disposal system is characterized in that, comprising:
The FFT arithmetic unit is used for 2
N-mThe individual degree of depth is 2
mRAM in deposit 2
nPoint data, described every point data is stored in respectively in the bit-reversed address that the order corresponding address carries out obtaining after the bit-reversed operation separately, in every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence;
Address conversion device is used for the default OPADD of FFT arithmetic unit is carried out the Input Address that the bit-reversed operation obtains the IFFT arithmetic unit;
The IFFT arithmetic unit, be used for to write from the data that the default OPADD of FFT arithmetic unit is read the Input Address of the IFFT arithmetic unit that address conversion device draws, in every grade of butterfly computation of preceding m level butterfly computation, from each self-corresponding RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back a RAM to correspondence; From each self-corresponding the 2nd RAM of each butterfly processing element, read the butterfly processing element of two data successively, and the data former address behind the butterfly computation is write back the 2nd RAM to correspondence;
In every grade of butterfly computation in m+1 level to the n level butterfly computation, from each self-corresponding two RAM of each butterfly processing element, read the butterfly processing element of data respectively respectively, and the data former address behind the butterfly computation is write back among two RAM of described correspondence to correspondence.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102306142A (en) * | 2011-08-11 | 2012-01-04 | 华中科技大学 | Method and circuit for scheduling data of memory through fast Fourier transform (FFT) reverse operation |
| CN102306142B (en) * | 2011-08-11 | 2014-05-07 | 华中科技大学 | Method and circuit for scheduling data of memory through fast Fourier transform (FFT) reverse operation |
| CN103544111A (en) * | 2013-10-08 | 2014-01-29 | 北京理工大学 | Mixed base FFT method based on real-time processing |
| CN103544111B (en) * | 2013-10-08 | 2016-06-01 | 北京理工大学 | A kind of hybrid base FFT method based on real-time process |
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| CN104268122B (en) * | 2014-09-12 | 2017-03-22 | 安徽四创电子股份有限公司 | Point-changeable floating point FFT (fast Fourier transform) processor |
| CN117389946A (en) * | 2023-11-09 | 2024-01-12 | 合肥灿芯科技有限公司 | FFT (fast Fourier transform) implementation structure capable of dynamically expanding points |
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