CN117389944A

CN117389944A - Dual-path CPU control method, system, device and storage medium

Info

Publication number: CN117389944A
Application number: CN202311181961.2A
Authority: CN
Inventors: 黄晓; 王渊; 李璇; 周庆飞; 李文帅
Original assignee: China Great Wall Technology Group Co ltd
Current assignee: China Great Wall Technology Group Co ltd
Priority date: 2023-09-13
Filing date: 2023-09-13
Publication date: 2024-01-12

Abstract

The method is applied to a double-path CPU control system, a receiving end of a low-speed signal of a slave CPU is switched from the master BMC to the slave BMC by the master BMC under the condition that the working mode of a server is a double-path CPU interconnection mode, and after the low-speed signal is switched, the working mode of the server is a double-single-path CPU mode, so that the server avoids memory access across the CPU by changing the working mode, and the data stability is higher when the server works in the double-single-path CPU mode, and can also meet the requirement of a user on the data stability.

Description

Dual-path CPU control method, system, device and storage medium

Technical Field

The application belongs to the technical field of computers, and particularly relates to a double-path CPU control method, a double-path CPU control system, a double-path CPU control device and a double-path CPU control storage medium.

Background

With the continuous development of computer technology, in order to meet the demands of users for computing power of servers, two-way central processing units (Central Processing Unit, CPU) interconnecting servers are proposed.

Although the two-way CPU interconnection server meets the user demands in terms of computational power, when the user has higher requirements on data stability, the two-way CPU interconnection server greatly influences the data stability due to the problem of poor performance of accessing the memory across the CPU.

Therefore, a method is needed to solve the problem that the dual-path CPU interconnect server has poor inter-CPU access memory performance, so that the dual-path CPU interconnect server can meet the requirement of the user on data stability.

Disclosure of Invention

The embodiment of the application provides a double-path CPU control method, a double-path CPU control system, a double-path CPU control device and a double-path CPU control storage medium, which can solve the problem that a double-path CPU interconnection server has poor inter-CPU access memory performance.

In a first aspect, an embodiment of the present application provides a dual-path CPU control method, which is applied to the dual-path CPU control system, where the dual-path CPU control system includes: the control method comprises the steps of enabling a server to comprise a slave CPU and a master CPU, enabling the master BMC to be in communication connection with the slave CPU and the master CPU, enabling the slave BMC to be in communication connection with the slave CPU, and enabling the slave BMC to be in communication connection with the master BMC, wherein the control method comprises the following steps:

determining a working mode of the server, wherein the working mode comprises the following steps: the dual single-path CPU mode and the dual-path CPU interconnection mode are as follows: the master BMC controls the master CPU, and the slave BMC controls the slave CPU, and the two-way CPU interconnection mode is as follows: the master BMC controls the master CPU and the slave CPU;

under the condition that the working mode of the server is a two-way CPU interconnection mode, the master BMC switches the receiving end of the low-speed signal of the slave CPU from the master BMC to the slave BMC, and after the low-speed signal is switched, the working mode of the server is a two-way and one-way CPU mode.

In a possible implementation manner of the first aspect, the method further includes: under the condition that the working mode of the server is a double-single-path CPU mode, the master BMC switches the receiving end of the low-speed signal of the slave CPU from the slave BMC to the master BMC, and after the low-speed signal is switched, the working mode of the server is a double-path CPU interconnection mode.

In a possible implementation manner of the first aspect, the determining an operation mode of the server includes:

and determining the working mode of the server corresponding to the identification of the master BMC and the identification of the slave BMC according to the identification of the master BMC and the identification of the slave BMC.

In a possible implementation manner of the first aspect, before the master BMC switches the receiving end of the low speed signal of the slave CPU from the master BMC to the slave BMC, the method further includes:

the master BMC detects the slave BMC's heartbeat signal.

In a possible implementation manner of the first aspect, determining an operation mode of the server includes:

the master BMC reads the working mode of the server configured by the user;

the master BMC sends the working mode of the server configured by the user to a controller of the server;

the controller of the server sets the identification of the main CPU and the identification of the auxiliary CPU as the identifications corresponding to the working mode of the server configured by the user according to the working mode of the server configured by the user;

The controller of the server reads the identification of the main CPU and the identification of the slave CPU and controls the main CPU and the slave CPU to execute the configured working mode.

In a possible implementation manner of the first aspect, determining, according to the identity of the master BMC and the identity of the slave BMC, an operation mode of a server corresponding to the identity of the master BMC and the identity of the slave BMC includes:

according to the identification of the master BMC and the identification of the slave BMC, respectively corresponding identifications, determining whether the identification of the master BMC and the slave BMC can normally communicate, wherein a mapping relation exists between the identification of the master BMC and whether the master BMC and the slave BMC can normally communicate, and a mapping relation exists between the identification of the slave BMC and whether the slave BMC and the slave BMC can normally communicate;

under the condition that the master BMC can normally communicate and the slave BMC cannot normally communicate, determining that the working mode of the server is a two-way CPU interconnection mode;

and under the condition that the master BMC can normally communicate and the slave BMC can normally communicate, determining the working mode of the server to be a double single-channel CPU mode.

In a second aspect, embodiments of the present application provide a dual path CPU controlled system, the system including: the server comprises a slave CPU and a master CPU, the master BMC is in communication connection with the slave CPU and the master CPU, the slave BMC is in communication connection with the slave CPU, the slave BMC is in communication connection with the master BMC, and the system is used for the method in any one of the first aspects.

In a third aspect, an embodiment of the present application provides a communication apparatus, including: the two-way CPU control system according to the second aspect described above.

In a fourth aspect, embodiments of the present application provide a chip, including: a processor for calling and running a computer program from a memory, causing a communication device on which the chip is mounted to perform the method of any of the above first aspects.

In a fifth aspect, a computer readable storage medium stores a computer program which, when executed by a processor, implements the method according to any of the first aspects.

In a sixth aspect, embodiments of the present application provide a computer program product, which when run on a server, causes the server to perform the method of any one of the first aspects.

In a seventh aspect, embodiments of the present application provide another communication device, including at least one processor and an interface circuit, where the at least one processor is configured to perform the method according to any one of the first aspects.

It will be appreciated that the advantages of the second to seventh aspects may be found in the relevant description of the first aspect, and are not described here again.

Compared with the prior art, the embodiment of the application has the beneficial effects that: under the condition that the working mode of the server is a two-way CPU interconnection mode, the master BMC switches the receiving end of the low-speed signal of the slave CPU from the master BMC to the slave BMC, after the low-speed signal is switched, the working mode of the server is a double-single-way CPU mode, so that the server avoids memory access across the CPU by changing the working mode, and the server has higher data stability when working in the double-single-way CPU mode and can also meet the requirement of a user on the data stability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a dual-path CPU control system provided in an embodiment of the present application;

fig. 2 is a flow chart of a method for judging a working mode of a server according to an embodiment of the present application;

Fig. 3 is a flow chart of a method for starting up a server according to an embodiment of the present application;

fig. 4 is a flow chart of a method for switching a server working mode according to an embodiment of the present application;

fig. 5 is a flowchart of another method for switching a server working mode according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a communication device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

With the continuous development of computer technology, in order to meet the demands of users on the computing power of the server, a two-way CPU interconnection server is provided. The dual-path CPU interconnection server adopts a non-uniform memory access (Non Uniform Memory Access, NUMA) architecture to realize dual-path CPU interconnection, the NUMA architecture combines a plurality of cores into a Node, each Node is equivalent to a symmetrical multiprocessor (Symmetric multiprocessing, SMP), the CPU in the same Node block is communicated through a bus in the Node, the bus bandwidth bottleneck is solved, but different memory access performances are greatly different under the NUMA architecture, the performance of accessing local memory in the Node is optimal, and the performance of accessing memory across the CPU is poorer.

Aiming at the problems, the embodiment of the application provides a double-path CPU control method, which is applied to a double-path CPU control system, and when the working mode of a server is a double-path CPU interconnection mode, a main BMC switches a receiving end of a low-speed signal of a slave CPU from the main BMC to the slave BMC, and after the low-speed signal is switched, the working mode of the server is a double-single-path CPU mode, so that the server avoids memory access across the CPU by changing the working mode, and the server works in the double-single-path CPU mode, has higher data stability and can meet the requirement of a user on the data stability; the requirement of converting the server from the two-way CPU interconnection mode to the two-way and one-way CPU mode is realized through the BMC.

The two-way CPU control method provided in the embodiment of the present application will be specifically described below.

Fig. 1 is a schematic structural diagram of a dual-path CPU control system provided in the present application, as shown in fig. 1, where the control system includes: a server motherboard, a baseboard management controller (Baseboard Manager Controller, BMC) backplane, and a BMC expansion board;

the server motherboard includes: a master CPU, a slave CPU, a complex programmable logic device (Complex Programmable Logic Device, CPLD), and a first interface. The first interface is used for being connected with the BMC bottom plate in a pluggable mode.

The BMC bottom plate includes: the second interface, the third interface and the main BMC chip. The second interface is used for being connected with the server mainboard in a pluggable mode. The third interface is used for being connected with the BMC expansion board in a pluggable mode. Master BMC chip, abbreviated as: and the main BMC is used for switching working modes based on different application scenes, wherein the working modes comprise a two-way CPU interconnection mode and a one-way CPU mode.

It should be noted that, the two-way CPU interconnection mode refers to that two CPUs (a master CPU and a slave CPU) are interconnected through high-speed signals, the two CPUs perform signal transmission and signal reading and writing, the two CPUs share the master BMC, and b realize remote access and monitoring functions through the same set of keyboard, display and mouse (Keyboard, video, mouse, KVM) in communication with the master BMC. The single-path CPU mode means that the main CPU independently works relative to the slave CPU, the main CPU is independently provided with a BMC without sharing the BMC with other CPUs, and the independent remote access and monitoring function can be realized through the KVM corresponding to the main CPU.

It is understood that the connection between the BMC backplane and the server motherboard may be a direct connection or an indirect connection via a connector.

In one possible embodiment, the second interface of the BMC backplane is directly connected to the first interface of the server motherboard.

In a possible embodiment, the control system further includes a first board-to-board connector for connecting the BMC backplane and the server motherboard by connecting the first interface and the second interface, respectively. In a specific embodiment, the first board-to-board connector includes an interface a and an interface B, the first board-to-board connector is connected to the server motherboard by the interface a and the first interface in a pluggable manner, and the first board-to-board connector is connected to the BMC motherboard by the interface B and the second interface in a pluggable manner. Therefore, the pluggable connection between the BMC bottom plate and the server main board can be realized by utilizing the first plate connector. Illustratively, the first inter-board connector may be a general purpose computer platform (OPEN Compute Project, OCP) connector.

The BMC expansion board comprises: the fourth interface and the slave BMC chip are used for being connected with the BMC bottom plate in a pluggable mode.

It will be appreciated that the connection between the BMC backplane and the BMC extension board may be a direct connection or an indirect connection via a connector.

In one possible embodiment, the third interface of the BMC chassis is directly connected to the fourth interface of the BMC expansion board.

In a possible embodiment, the third interface and the fourth interface are respectively connected by using an m.2 connector, so as to realize indirect connection between the BMC bottom plate and the BMC expansion board.

In one possible embodiment, the CPLD on the server motherboard may communicate with the master BMC and the slave BMC via an integrated circuit bus (Inter-Integrated Circuit, IIC), respectively. The CPLD is used for controlling the power-on condition of each CPU based on different working modes.

In one possible embodiment, the server motherboard further includes a switch module in communication with the CPLD and in communication with the master BMC and the slave BMC, respectively. The master BMC switches the low speed signal of the slave CPU through the switching module, in other words, a receiving end for changing the low speed signal of the slave CPU.

It should be noted that, in this embodiment of the present application, the server motherboard includes two CPUs, where under the condition that the two CPUs work independently, each is provided with an independent BMC, the master CPU is provided with a master BMC, the slave CPU is provided with a slave BMC, and remote access and monitoring functions to the master CPU and the slave CPU are implemented through KVM corresponding to the master BMC and the slave BMC, respectively, and this working mode is referred to as a dual single-path CPU mode. When the working mode of the control system provided by the application is a double-single-path CPU mode, the control system can be understood to work by two independent servers, and CPLD is shared between the two servers, but data interaction is not performed. The BMC expansion board in the embodiment of the application is connected to the BMC base board, and does not occupy the space of the server additionally; the BMC expansion board has lower cost, and the server is flexibly switched between a double-path CPU interconnection mode and a double-single-path CPU mode through interaction between the master BMC and the slave BMC and the CPLD, so that the requirements of users on different scenes such as calculation force, data stability and the like are met, and the competitiveness of server products is improved.

It should be understood that the system architecture illustrated in fig. 1 is not intended to constitute a particular limitation as to the architecture of the control system applicable to the examples herein. In other embodiments of the present application, control systems suitable for use in the examples of the present application may include more or fewer components than shown in FIG. 1, or different components, etc., and embodiments of the present application are not limited in this respect. Also, the components shown in FIG. 1 may be implemented in hardware, software, or a combination of software and hardware.

Fig. 2 is a flow chart of a method for judging a working mode of a server according to an embodiment of the present application. The method shown in fig. 2 may be applied to the control system shown in fig. 1.

Next, a method for determining a working mode of a server according to an embodiment of the present application is described with reference to fig. 2, and specifically, the embodiment of the present application provides a method for determining a two-way CPU interconnection mode and a two-way CPU mode, which is applied to the control system described above, where the control system further includes a power supply unit (Power Supply Unit, PSU), and the PSU is configured to provide a stable power supply for the server. The PSU is connected to the server mainboard in a pluggable mode, and when the PSU is connected with the server mainboard and the server is not started, the master BMC and the slave BMC can finish kernel loading and file system loading.

In the case that the server motherboard is plugged into the PSU and the server is not started up, the above-mentioned working mode judging method includes:

s201, acquiring working mode information through the master BMC.

In one possible embodiment, the control system reads the operating mode information from the BIOS through the master BMC and CPLD. It should be noted that the CPLD may communicate with the master BIOS and the slave BIOS through a serial peripheral interface (Serial Peripheral interface, SPI) bus, respectively. It can be understood that, if the user designates the operation mode of the server, the operation mode information corresponding to the operation mode designated by the user may be written in the BIOS in advance. The working modes of the server comprise a two-way CPU interconnection mode and a two-way CPU mode. The working mode information comprises first working mode information and second working mode information, wherein the first working mode information is information corresponding to a double-path CPU interconnection mode, and the second working mode information is information corresponding to a double-single-path CPU mode.

Specifically, the master BMC sends a first acquiring instruction to the CPLD through the IIC, where the first acquiring instruction is used to acquire working mode information corresponding to a working mode of the server, and the CPLD responds to the first acquiring instruction, reads the working mode information from the BIOS through the SPI bus, and sends the read working mode information to the master BMC through the IIC bus, so that the control system acquires the working mode information of the server through the master BMC.

In one possible embodiment, the operating mode information stored in the master BIOS and the slave BIOS are the same, and the operating mode information may be read from the master BIOS by the master BMC or from the slave BIOS by the master BMC.

S202, judging whether the working mode information is read from the BIOS or not through the master BMC, and executing S03 under the condition that the master BMC does not read the working mode information from the BIOS; in case that the master BMC reads the operation mode information from the BIOS, S04 is performed.

It will be appreciated that the user may or may not specify the operating mode of the server. When the user designates the operation mode of the server, the master BMC may read the operation mode information corresponding to the server, and then S03 is executed. If the user does not specify the operation mode of the server, the master BMC does not read the operation mode information corresponding to the server, and S04 is executed.

S203, determining the working mode information of the server through the master BMC according to the identification of the master BMC and the identification of the slave BMC, and executing S04.

It will be appreciated that when the user does not specify the operating mode of the server, the operating mode of the server may be determined based on the hardware configuration of the current server. In the embodiment of the application, the hardware configuration of the current server is determined according to the identification of the master BMC and the identification of the slave BMC, so that the working mode of the server is determined, and the working mode information corresponding to the working mode of the server is further determined. The identification of the BMC may include an identifier of the BMC, which may be controlled by the CPLD GPIO pin.

In one possible embodiment, the CPLD sends a second acquiring instruction to the CPLD, where the second acquiring instruction is used to acquire the identifier of the master BMC and the identifier of the slave BMC, and the CPLD reads the identifier of the master BMC and the identifier of the slave BMC in response to the second acquiring instruction and sends the second acquiring instruction to the master BMC, receives the identifier of the master BMC and the identifier of the slave BMC through the master BMC, and determines the configuration conditions of the master BMC and the slave BMC according to the identifier of the master BMC and the identifier of the slave BMC, so as to determine the working mode of the server.

Illustratively, the identifier of the master BMC is denoted by P0, P1, P2, and the identifier of the slave BMC is denoted by Q0, Q1, Q2.

If P0, P1 and P2 are set to 000, the master BMC is in place; the master BMC in place indicates that the master BMC is properly connected to the server and that the master BMC is able to communicate properly.

If P0, P1, P2 are other parameters than 000, for example: 001. 010, 100, 101, 110, 111, represent master BMC failures.

If Q0, Q1 and Q2 are set to 011, the slave BMC is in place; the slave BMC bit indicates that the slave BMC is properly connected to the master BMC and that the slave BMC is able to communicate properly.

If Q0, Q1, Q2 are set to 100, it indicates that the slave BMC is out of place; a slave BMC not in place indicates that the slave BMC is connected properly to the master BMC, but that the slave BMC is not communicating properly.

In one possible embodiment, the server is determined to correspond to different modes of operation based on the identifiers of different master BMCs and different slave BMCs.

For example, if P0, P1, P2 are 000, Q0, Q1, Q2 are 011, that is, the master BMC is in place and the slave BMC is in place, the corresponding operation mode of the server is a dual single-path CPU mode.

If P0, P1, P2 are 000, Q0, Q1, Q2 are 100, i.e. the master BMC is in place and the slave BMC is out of place, the corresponding operation mode of the server is a two-way CPU operation mode.

If P0, P1, P2 is 000 and Q0, Q1, Q2 are not acquired, that is, the master BMC is in place and the slave BMC is not configured or fails, and the identifier of the slave BMC cannot be read normally, the working mode corresponding to the server is a two-way CPU working mode.

If P0, P1, P2 are other parameters than 000, for example: 001. 010, 100, 101, 110, 111, and Q0, Q1, Q2 are not acquired, the master BMC fails, the slave BMC is not configured or fails, the identifier of the slave BMC cannot be read normally, and the corresponding working mode of the server cannot be determined.

S204, the working mode information is sent to the CPLD through the main BMC, and after the CPLD receives the working mode information, S205-S206 can be executed, or S207-S209 can be executed.

The master BMC sends the operating mode information to the CPLD via the IIC, for example.

S205, receiving the working mode information through the CPLD, determining register information corresponding to the working mode information according to the working mode information, and setting a register according to the register information.

Illustratively, the CPLD determines different register information based on different operating mode information. For example, in the case where the operation mode information is the dual single-path CPU mode, the determined register information is ft_cpu0_ INSTANCEID 0=0, ft_cpu 1_instrenceid0=1; in the case where the operation mode information is the two-way CPU interconnect mode, the determined register information is ft_cpu0_ INSTANCEID0 =0, ft_cpu 1_instrenceid0=0.

S206, controlling the CPU to be powered on and reset through the CPLD according to the working mode information.

S207, initializing the starting configuration of the application program according to the working mode information through the CPLD.

S208, controlling the normal start of the application program through the CPLD.

S209, finishing starting through the master BMC.

Under the condition that the server is not electrified, the working mode of the server is determined by acquiring the working mode information of the server configured by the user, so that the CPLD control application program completes initial configuration according to the working mode of the server, waits for the starting of the server, and saves the starting time of the server, thereby further improving the experience of the user on using the server.

Fig. 3 is a schematic flowchart of a method for starting up a server according to an embodiment of the present application. Specifically, with reference to fig. 3, an embodiment of the present application provides a method for starting a server in a dual-path CPU interconnection mode or a dual-single-path CPU mode. During the power-up process of the alternating current (Alternating Current, AC) of the server, the starting method comprises the following steps:

s301, judging whether the slave BMC is in place or not through the master BMC.

If the slave BMC is not in place, the remote KVM control may be implemented by the master BMC on the server motherboard and the slave CPU, and S302 is executed.

If the slave BMC is in place, the remote KVM control may be implemented by the master BMC to the master CPU on the server motherboard, and the remote KVM control may be implemented by the slave BMC to the slave CPU on the server motherboard, then S308 is executed.

In one possible embodiment, the master BMC determines whether the slave BMC is in place based on the slave BMC's identifier. Specifically, the master BMC sends a third acquiring instruction to the CPLD, where the third acquiring instruction is used to acquire the identifier of the slave BMC, and the CPLD responds to the third acquiring instruction to acquire the identifier of the slave BMC and sends the acquired identifier of the slave BMC to the master BMC, so that the master BMC can determine whether the slave BMC is in place according to the identifier of the slave BMC.

In a possible embodiment, the master BMC stores a correspondence between the identifier of the slave BMC and the presence information, where the correspondence may include: the identifier of the slave BMC is 011 and the corresponding relation of the slave BMC in place, and the identifier of the slave BMC is 100 and the corresponding relation of the slave BMC out of place. The master BMC acquires the identifier of the slave BMC and determines whether the slave BMC is in place or not according to the identifier of the slave BMC and the corresponding relation between the pre-stored identifier of the slave BMC and the in-place information.

S302, determining that the working mode is a two-way CPU interconnection mode through the master BMC.

S303, the working mode indication information is sent to the CPLD through the main BMC. The working mode indication information comprises a double-path CPU interconnection mode, and the working mode indication information is used for indicating that the working mode of the CPLD server is the double-path CPU interconnection mode.

In one possible embodiment, the master BMC sends the operating mode indication information to the CPLD over the I2C bus.

S304, responding to the working mode indication information, switching the power-on sequential logic to the dual-path power-on sequential logic corresponding to the dual-path CPU interconnection mode through the CPLD, setting SOCKIT ID of the master CPU and the slave CPU to be 2' b00, and waiting for the power-on starting of the CPU.

S305, detecting a power-on starting signal of the CPU through the CPLD, and executing S306 if the power-on starting signal of the CPU is detected through the CPLD; if the CPLD does not detect the power-on start signal of the CPU, S305 is re-executed.

In a possible embodiment, the CPU corresponds to a start button, and when the start button is pressed, a power-on start signal can be generated, and the CPLD detects the power-on start signal, which indicates that the CPU can perform power-on start.

S306, the double-path power-on sequential logic is operated through the CPLD.

S307, the SOCKIT ID is sent to the BIOS through the CPLD, so that the BIOS runs the two-way BIOS according to the SOCKIT ID.

S308, switching the low-speed signal to the slave BMC through the master BMC.

Wherein the low speed signal comprises: I2C or universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), etc.

Specifically, a working mode switching request is sent to the CPLD through the master BMC, the working mode switching request comprises a double single-path CPU mode, the double single-path CPU mode is sent to the switch module through the CPLD responding to the working mode switching request, and the switch module switches a low-speed signal of the slave CPU from the master BMC to the slave BMC according to the double single-path CPU mode.

The SWITCH module may be a SWITCH chip, for example.

S309, detecting whether the slave BMC has a heartbeat signal or not through the master BMC.

In one possible embodiment, the master BMC periodically detects whether the slave BMC has a heartbeat signal within a preset time period. For example, the preset time period may be 5 minutes, which is not limited in this application.

The detection of whether the slave BMC has a heartbeat signal is to determine whether the slave BMC is "alive", in other words, to determine whether the slave BMC can normally communicate.

S310, if the heartbeat signal of the slave BMC is not detected by the master BMC, the low-speed signal of the slave CPU is switched to the master BMC, and S302-S307 are executed.

In one possible embodiment, if a heartbeat signal from the BMC is detected by the master BMC, then S311-S316 are performed.

If the master BMC does not detect the heartbeat signal of the slave BMC, it is determined that the slave BMC cannot normally communicate, that is, cannot control the slave CPU by the slave BMC, and the master BMC is still required to control the slave CPU, so that it is required to switch the low-speed signal of the slave CPU to the master BMC.

S311, determining that the working mode is a double-single-channel CPU working mode through the master BMC.

S312, the working mode indication information is sent to the CPLD through the main BMC. The working mode indication information is used for indicating that the working mode of the CPLD server is a double-single-path CPU working mode.

S313, responding to the working mode indication information, switching the power-on sequential logic to the double single-circuit power-on sequential logic corresponding to the double single-circuit CPU working mode through the CPLD, setting SOCKIT ID of the master CPU and the slave CPU to be 2' b01, and waiting for the power-on start of the CPU.

S314, detecting a power-on starting signal of the CPU through the CPLD.

If the CPLD detects the power-on starting signal of the CPU, executing S315; if the CPLD does not detect the power-on start signal of the CPU, S314 is re-executed.

S315, running double single power-on sequential logic through the CPLD.

S316, the SOCKIT ID is sent to the BIOS through the CPLD, so that the BIOS runs the double-single-path BIOS according to the SOCKIT ID.

Fig. 4 is a schematic flowchart of a method for switching a server working mode according to an embodiment of the present application. Specifically, referring to fig. 4, a method for switching a dual single CPU mode to a dual CPU interconnection mode is described in this embodiment. After the server is normally started in a double-single-path CPU mode, the method for switching the double-single-path CPU mode into a double-path CPU interconnection mode in the normal operation process of the server comprises the following steps:

s401, receiving a switching request through the master BMC.

The switching request includes a target working mode, and the target working mode in the embodiment of the application is a two-way CPU interconnection mode.

In one possible embodiment, the user may select the target operating mode by using a KVM remotely interconnected with the master BMC, and the KVM generates a specific IPMI command to the master BMC according to the target operating mode, where the specific IPMI command includes a switch request generated according to the target operating mode.

And S402, generating a power supply enabling signal through the master BMC according to the switching request, and sending the power supply enabling signal to the slave BMC to control the slave BMC to turn off the power supply of the BMC expansion card according to the power supply enabling signal.

S403, notifying the CPLD to control the mainboard of power-down of the server through the main BMC, sending an instruction for switching the sequential logic and an instruction for setting the SOCKIT ID of the main CPU and the slave CPU to the CPLD, switching the power-up sequential logic into the double-path power-up sequential logic through the CPLD according to the instruction for switching the sequential logic, and setting the SOCKIT ID of the main CPU and the slave CPU to be 2' b00 according to the instruction for setting the SOCKIT ID of the main CPU and the slave CPU.

It should be noted that S403 may be executed first, and S402 may be executed later; s402 and S403 may also be performed simultaneously.

S404, after the power-down of the server main board is completed, the low-speed signal of the slave CPU is switched to the master BMC through the switch module.

In a possible embodiment, whether the power-down of the server main board is completed is monitored through the CPLD, when the power-down completion of the server main board is detected, a power-down completion signal of the server main board is generated, the power-down completion signal of the server main board is sent to the main BMC, the main BMC sends a switching instruction to the switch module through the CPLD, and the switch module switches the low-speed signal of the slave CPU from the slave BMC to the main BMC according to the switching instruction.

S405, a startup instruction is sent to the CPLD through the main BMC.

Through the S401-S405, the server can be switched from the double-single-path CPU mode to the double-path CPU interconnection mode according to the working mode corresponding to the user requirement in the normal operation process, so that the requirement of the user is met.

Fig. 5 is a schematic flowchart of another method for switching a server working mode according to an embodiment of the present application. Referring to fig. 5, a method for switching a dual-path CPU interconnect mode to a dual-single-path CPU mode is provided in this embodiment, specifically, after a server is powered on normally in the dual-path CPU interconnect mode, or after the dual-single-path CPU mode is switched to the dual-path CPU interconnect mode, the method for switching from the dual-path CPU interconnect mode to the dual-single-path CPU mode includes:

s501, receiving a switching request through the master BMC.

The switching request includes a target working mode, which in the embodiment of the application is a dual single-path CPU mode.

In a possible embodiment, in the process that the server normally operates in the two-way CPU interconnection mode, the user wants to switch the working mode of the server to the two-way CPU mode, and can select the target working mode through the KVM remotely interconnected with the master BMC, and the KVM generates a specific IPMI command to the master BMC according to the target working mode, where the specific IPMI command includes a switch request generated according to the two-way CPU mode.

S502, generating a power supply enabling signal through the master BMC according to the switching request, sending the power supply enabling signal to the slave BMC, and controlling the slave BMC to close the power supply of the BMC expansion card according to the power supply enabling signal.

S503, notifying the CPLD to control the mainboard of power-down of the server through the main BMC, sending an instruction for switching the sequential logic and an instruction for setting the SOCKIT ID of the main CPU and the slave CPU to the CPLD, switching the power-up sequential logic into double-single-path power-up sequential logic through the CPLD according to the instruction for switching the sequential logic, and setting the SOCKIT ID of the main CPU and the slave CPU to be 2' b01 according to the instruction for setting the SOCKIT ID of the main CPU and the slave CPU.

It should be noted that S503 may be executed first, and S502 may be executed later; s502 and S503 may also be performed simultaneously.

S504, after the power-down of the server main board is completed, the low-speed signal of the server is switched to the slave BMC through the switch module in a mode of being split into two.

In a possible embodiment, whether the power-down of the server main board is completed is monitored through the CPLD, when the power-down completion of the server main board is detected, a server main board power-down completion signal is generated, the server main board power-down completion signal is sent to the master BMC, the master BMC sends a switching instruction to the switch module through the CPLD, the switch module divides the low-speed signal of the server into two parts to be switched to the master BMC and the slave BMC according to the switching instruction, namely, the low-speed signal of the master CPU is sent to the master BMC, and the low-speed signal of the slave CPU is sent to the slave BMC.

S505, a power enable signal is sent through the master BMC, and the slave BMC is controlled to power on the BMC expansion card according to the power enable signal.

S506, detecting a heartbeat signal of the slave BMC through the master BMC, and if the heartbeat signal of the slave BMC is detected, sending a power-on instruction to the CPLD through the master BMC; if the heartbeat signal of the slave BMC is not detected, the master BMC sends information of the fault of the BMC expansion board to the CPLD.

Through the above S501-S506, it is possible to receive a switching instruction corresponding to the two-way CPU interconnection mode required by the user when the server normally operates in the two-way single-way CPU mode, set the master CPU and the slave CPU in the server, and change the receiving end of the low-speed signal of the server, so as to implement the switching of the server from the two-way CPU interconnection mode to the two-way CPU interconnection mode, thereby meeting the requirement of the user.

According to the control method of the two-way CPU, the working modes of the server are flexibly switched according to different configuration requirements of users, so that the server can meet more application scenes.

It should be understood that the various numbers referred to in the embodiments of the present application are merely for ease of description and are not intended to limit the scope of the embodiments of the present application. The sequence numbers of the above-mentioned processes do not mean the sequence of execution sequence, and the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

It should also be understood that the foregoing description of embodiments of the present application focuses on highlighting differences between the various embodiments and that the same or similar elements not mentioned may be referred to each other and are not described in detail herein for brevity.

The embodiment of the application provides a double-circuit CPU control system, which comprises: the server comprises a slave CPU and a master CPU, the master BMC is in communication connection with the slave CPU and the master CPU, the slave BMC is in communication connection with the slave CPU, and the slave BMC is in communication connection with the master BMC and is used for executing the two-way CPU control method, so that the same effects as the implementation method can be achieved.

The application also provides a communication device which comprises the double-circuit CPU control system.

The application also provides a chip comprising: and a processor for calling and running the computer program from the memory. The processor mentioned in any of the above may be a CPU, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the above-mentioned feedback information transmission method.

Another communication device 600 is also provided that includes at least one processor 610 and at least one interface circuit 620. The processor 610 and the interface circuit 620 may be interconnected by wires. For example, interface circuit 620 may be used to receive signals from other devices (e.g., terminal equipment). For another example, interface circuit 620 may be used to send signals to other devices (e.g., processor 610). The interface circuit 620 may, for example, read instructions stored in the memory and send the instructions to the processor 610. The instructions, when executed by the processor 610, may cause the communication device to perform the various steps performed by the first terminal or the second terminal in the examples described above. Of course, the communication device may also comprise other discrete components, which are not particularly limited in this application.

The chip, the computer readable storage medium, the computer program product or the communication device provided in this application are all configured to execute the corresponding method provided above, so that the beneficial effects thereof can be referred to the beneficial effects in the corresponding method provided above, and will not be described herein.

It is to be understood that the memory in this application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a ROM, a Programmable ROM (PROM), an erasable programmable EPROM (EPROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory, among others. The volatile memory may be RAM, which acts as external cache. There are many different types of RAM, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and direct memory bus RAM (DR RAM).

Various objects such as various messages/information/devices/network elements/systems/devices/actions/operations/processes/concepts may be named in the present application, and it should be understood that these specific names do not constitute limitations on related objects, and that the named names may be changed according to the scenario, context, or usage habit, etc., and understanding of technical meaning of technical terms in the present application should be mainly determined from functions and technical effects that are embodied/performed in the technical solution.

In the various examples of this application, where there is no special description or logical conflict, terms and/or descriptions between the different examples are consistent and may reference each other, technical features in the different examples may be combined to form new examples according to their inherent logical relationship.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the examples disclosed herein may be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The methods in the examples of the present application may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described herein are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer program or instructions may be stored in or transmitted across a computer-readable storage medium. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server that integrates one or more available media.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method examples, and are not repeated herein.

In the several examples provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus examples described above are merely illustrative, e.g., the division of the elements is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purposes of the present application.

In addition, each functional unit in each example of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a readable storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the examples of the present application. And the aforementioned readable storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The double-path CPU control method is applied to the double-path CPU control system, and the double-path CPU control system comprises: the server comprises a slave CPU and a master CPU, the master BMC is in communication connection with the slave CPU and the master CPU, the slave BMC is in communication connection with the slave CPU, and the slave BMC is in communication connection with the master BMC, and the control method is characterized by comprising the following steps:

determining a working mode of the server, wherein the working mode comprises the following steps: the dual single-path CPU mode and the dual-path CPU interconnection mode are as follows: the master BMC controls the master CPU, the slave BMC controls the slave CPU, and the two-way CPU interconnection mode is as follows: the master BMC controls the master CPU and the slave CPU;

and under the condition that the working mode of the server is a two-way CPU interconnection mode, the master BMC switches the receiving end of the low-speed signal of the slave CPU from the master BMC to the slave BMC, and after the low-speed signal of the slave CPU is switched, the working mode of the server is the two-way and one-way CPU mode.

2. The method of claim 1, wherein the method further comprises:

under the condition that the working mode of the server is a double-single-path CPU mode, the master BMC switches the receiving end of the low-speed signal of the slave CPU from the slave BMC to the master BMC, and after the low-speed signal is switched, the working mode of the server is the double-path CPU interconnection mode.

3. The method of claim 1, wherein the determining the operating mode of the server comprises:

4. The method of claim 1, wherein before the master BMC switches the receiving end of the low speed signal of the slave CPU from the master BMC to the slave BMC, the method further comprises:

the master BMC detects the heartbeat signal of the slave BMC.

5. The method of claim 1, wherein the determining the operating mode of the server comprises:

the master BMC reads the working mode of the server configured by the user;

the controller of the server sets the identification of the master CPU and the identification of the slave CPU as identifications corresponding to the working mode of the server configured by the user according to the working mode of the server configured by the user;

and the controller of the server reads the identification of the master CPU and the identification of the slave CPU and controls the working modes of the master CPU and the slave CPU to execute configuration.

6. The method of claim 3, wherein determining the operating mode of the server corresponding to the identity of the master BMC and the identity of the slave BMC based on the identity of the master BMC and the identity of the slave BMC comprises:

determining whether the identification of the master BMC and the slave BMC can normally communicate according to the identifications respectively corresponding to the identification of the master BMC and the identification of the slave BMC, wherein a mapping relationship exists between the identification of the master BMC and between the identification of the slave BMC and the slave BMC;

under the condition that the master BMC can normally communicate and the slave BMC cannot normally communicate, determining that the working mode of the server is the two-way CPU interconnection mode;

and under the condition that the master BMC can normally communicate and the slave BMC can normally communicate, determining the working mode of the server to be the double single-path CPU mode.

7. A two-way CPU control system, the system comprising: a server comprising a slave CPU and a master CPU, a master BMC communicatively coupled to the slave CPU and the master CPU, a slave BMC communicatively coupled to the slave CPU, the slave BMC and the master BMC communicatively coupled to each other, the system configured to perform the method of any of claims 1 to 6.

8. A communication device, comprising: the two-way CPU control system of claim 7.

9. A chip, comprising: a processor for calling and running a computer program from a memory, causing a communication device on which the chip is mounted to perform the method of any one of claims 1 to 6.

10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the method according to any one of claims 1 to 6.