CN117375609A - Switched capacitor integrator based on optimized passive charge compensation capacitance and sigma-delta modulator - Google Patents

Switched capacitor integrator based on optimized passive charge compensation capacitance and sigma-delta modulator Download PDF

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Publication number
CN117375609A
CN117375609A CN202311480478.4A CN202311480478A CN117375609A CN 117375609 A CN117375609 A CN 117375609A CN 202311480478 A CN202311480478 A CN 202311480478A CN 117375609 A CN117375609 A CN 117375609A
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switch
capacitor
sampling
operational amplifier
switched
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Inventor
张巧惠
李鹏
习伟
陈军健
关志华
刘德宏
邓清唐
吴雨沼
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Southern Power Grid Digital Grid Research Institute Co Ltd
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Southern Power Grid Digital Grid Research Institute Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a switched capacitor integrator and a sigma-delta modulator based on an optimized passive charge compensation capacitor. The switched capacitor integrator comprises a switched sampling capacitor, an operational amplifier, a feedback capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a capacitive load and a passive charge compensation capacitor; the working process of the switch sampling capacitor comprises a sampling working period and an integration working period; in a sampling working period, the first switch, the fourth switch and the seventh switch are closed, and the second switch, the third switch, the fifth switch and the sixth switch are opened; during the integration duty cycle, the first switch, the fourth switch, and the seventh switch are turned off, and the second switch, the third switch, the fifth switch, and the sixth switch are turned off. The bandwidth of the switch capacitor integrator is improved by optimizing the capacitance value of the passive charge compensation capacitor, and the better signal-to-noise-and-distortion ratio is obtained.

Description

Switched capacitor integrator based on optimized passive charge compensation capacitance and sigma-delta modulator
Technical Field
The embodiment of the invention relates to the technical field of analog-digital conversion, in particular to a switched capacitor integrator and a sigma-delta modulator based on optimized passive charge compensation capacitor.
Background
Analog-to-Digital Converter (ADC) is an important bridge for communicating Analog signals and digital signals, and sigma-delta ADC is taken as a typical representative thereof, and is particularly favored for having high resolution and high precision, and is widely applied to the fields of digital audio, instrument sensing, communication and the like.
The sigma-delta modulator is a core component of the sigma-delta ADC, and has a large influence on the signal-to-noise-and-distortion ratio of one of the important parameters of the ADC, and can improve the signal-to-noise-and-distortion ratio through noise shaping, thereby obtaining a higher-performance ADC. Non-ideal factors of the switched capacitor integrator in the sigma-delta modulator, such as gain, bandwidth, slew rate, etc. of the operational amplifier therein, greatly affect the noise shaping effect, thereby changing the signal-to-noise-and-distortion ratio of the overall ADC, resulting in an impact on the performance of the ADC.
In the prior art, the slew rate of the switched capacitor integrator is usually improved by adopting a motion compensation mode, however, the active compensation mode necessarily requires additional modules such as transconductance conversion, a DAC (digital-to-analog converter), voltage buffering and the like, so that the total area of the circuit is increased, and the total power consumption of the circuit is increased.
Disclosure of Invention
The invention provides a switched capacitor integrator and a sigma-delta modulator based on an optimized passive charge compensation capacitor, which are used for reducing the conversion time of an integration period and the conversion time of a sampling period of the switched capacitor integrator, improving the bandwidth of the switched capacitor integrator, obtaining a better signal-to-noise distortion ratio, improving the performance of an ADC, reducing the area of a circuit and reducing the total power consumption of the circuit.
In a first aspect, an embodiment of the present invention provides a switched capacitor integrator based on optimizing a passive charge compensation capacitor, including a switched sampling capacitor, an operational amplifier, a feedback capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a capacitive load, and a passive charge compensation capacitor;
the first end of the first switch is connected with the input end of the switch capacitor integrator, and the second end of the first switch is connected with the second end of the second switch and the first end of the switch sampling capacitor; the second end of the switch sampling capacitor is connected with the first end of the third switch and the second end of the fourth switch, and the second end of the third switch is connected with the first input end of the operational amplifier and the first end of the feedback capacitor; the output end of the operational amplifier is connected with the first end of the fifth switch, the second end of the feedback capacitor and the second end of the passive capacitance compensation capacitor, and the first end of the fifth switch is connected with the first end of the capacitive load; the first end of the passive charge compensation capacitor is connected with the second end of the sixth switch and the second end of the seventh switch, and the first end of the sixth switch is connected with the input voltage; a first end of the second switch, a first end of the fourth switch, a first end of the seventh switch, a second end of the capacitive load, and a second input terminal of the operational amplifier are grounded;
the working process of the switch sampling capacitor comprises a sampling working period and an integration working period; during the sampling duty cycle, the first switch, the fourth switch, and the seventh switch are closed, and the second switch, the third switch, the fifth switch, and the sixth switch are opened; during the integration duty cycle, the first switch, the fourth switch, and the seventh switch are open, and the second switch, the third switch, the fifth switch, and the sixth switch are closed.
Further, during the sampling duty cycle, the voltage at the first input terminal of the operational amplifier satisfies:
during the integration duty cycle, the voltage at the first input of the operational amplifier satisfies:
wherein v is in_S V being the voltage of the first input of the operational amplifier at the sampling duty cycle in_I V being the voltage at the first input of the operational amplifier during the integration period in For the input voltage, C A For the equivalent capacitance value of the first input end of the operational amplifier, C C Compensating the capacitance of the capacitor for the passive charge, C I C is the capacitance value of the feedback capacitor L Is the capacitance value of the capacitive load.
Further, the time of the sampling duty cycle satisfies:
the integration duty cycle time satisfies:
wherein t is S T is the time of the sampling work period I For the time of the integration duty cycle, SR I For the slew rate, SR of the operational amplifier during the integration duty cycle S At the sampling station for the operational amplifierRate of roll of cycle, V c Is the threshold voltage of the operational amplifier.
Further, the capacitance value of the passive charge compensation capacitor satisfies:
t S ＝t I ；
the capacitance value C of the passive charge compensation capacitor obtained by the formula C To optimize the capacitance value C O 。
Further, the total capacitive load C at the output of the operational amplifier during the sampling duty cycle T_S The method meets the following conditions:
the total capacitive load C at the output of the operational amplifier during the integration period T_I The method meets the following conditions:
further, the cutoff frequency of the transconductance of the operational amplifier and the bandwidth of the switched capacitor integrator at the sampling duty cycle satisfies:
the cutoff frequency of the transconductance of the operational amplifier and the bandwidth of the switched capacitor integrator at the integration duty cycle satisfies:
wherein g m Is the transconductance of the operational amplifier, f S F is the cut-off frequency of the bandwidth of the switched capacitor integrator at the sampling duty cycle I For said switch in said integration duty cycleCut-off frequency of bandwidth of the capacitive integrator.
Further, the first switch, the fourth switch and the seventh switch are controlled by a sampling pulse clock, the second switch, the third switch and the fifth switch are controlled by an integration pulse clock, and the sixth switch is controlled by a compensation pulse clock.
Further, in the sampling working period, the sampling pulse clock is at a high level, and the integrating pulse clock and the compensating pulse clock are at a low level; and in the integration working period, the sampling pulse clock is in a low level, and the integration pulse clock and the compensation pulse clock are in a high level.
Further, in the sampling working period, the voltage v of the output end of the operational amplifier out_S The method meets the following conditions:
in a second aspect, an embodiment of the present invention further provides a sigma-delta modulator, including the switched capacitor integrator based on the optimized passive charge compensation capacitor.
The invention provides a switched capacitor integrator and a sigma-delta modulator based on an optimized passive charge compensation capacitor, wherein the switched capacitor integrator comprises a switched sampling capacitor, an operational amplifier, a feedback capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a capacitive load and the passive charge compensation capacitor. Meanwhile, by providing the passive charge compensation capacitor, the addition of an active compensation module in a circuit is avoided, and compared with the prior art, the circuit area is reduced and the total power consumption of the circuit is reduced under the condition of reaching the signal-to-noise distortion ratio of the sigma-delta modulator in the same ADC.
Drawings
Fig. 1 is a schematic circuit diagram of a switched capacitor integrator based on optimizing a passive charge compensation capacitor according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of another switched capacitor integrator based on optimizing passive charge compensation capacitance according to an embodiment of the present invention.
Fig. 3 shows a passive charge compensation capacitor C according to an embodiment of the present invention C Respectively adopt the non-optimized capacitance value C' C And optimizing capacitance value C O The obtained voltage of the input end of the switched capacitor integrator changes with time.
Fig. 4 is a timing chart of a sampling pulse clock CLK1, an integration pulse clock CLK2 and a compensation pulse clock CLK3 according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a sigma-delta modulator according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic circuit diagram of a switched capacitor integrator based on optimizing a passive charge compensation capacitor according to an embodiment of the present invention, as shown in fig. 1, the switched capacitor integrator includes a switched sampling capacitor C S Operational amplifier 101, feedback capacitor C I First switch S 1 Second switch S 2 Third switch S 3 Fourth switch S 4 Fifth switch S 5 Sixth switch S 6 Seventh switch S 7 Capacitive load C L And a passive charge compensation capacitor C C ；
First switch S 1 A first switch S connected to the input of the switched capacitor integrator 1 And a second switch S 2 A second terminal of (C), a switch sampling capacitor (C) S Is connected to the first end of the housing; switch sampling capacitor C S Is connected to the second end of (2)Third switch S 3 A first end, a fourth switch S 4 A third switch S connected to the second end of 3 A second terminal of (C) and a first input terminal of the operational amplifier 101, a feedback capacitor C I Is connected to the first end of the housing; the output terminal of the operational amplifier 101 and the fifth switch S 5 A first end of (C) a feedback capacitance C I A second terminal of (C), a passive charge compensation capacitor (C) C A fifth switch S connected to the second end of 5 Is connected to the capacitive load C L Is connected to the first end of the housing; passive charge compensation capacitor C C A first end and a sixth switch S 6 A second end of the seventh switch S 7 A sixth switch S connected to the second end of 6 Is connected with the input voltage V in The method comprises the steps of carrying out a first treatment on the surface of the Second switch S 2 A first end, a fourth switch S 4 A first end, a seventh switch S 7 Is the first end of the capacitive load C L A second input terminal of the operational amplifier 101 is grounded;
switch sampling capacitor C S The working process of the system comprises a sampling working period and an integration working period; during the sampling working period, the first switch S 1 Fourth switch S 4 Seventh switch S 7 Closing a second switch S 2 Third switch S 3 Fifth switch S 5 Sixth switch S 6 Disconnecting; during the integration period, the first switch S 1 Fourth switch S 4 Seventh switch S 7 Open, second switch S 2 Third switch S 3 Fifth switch S 5 Sixth switch S 6 Closing.
Wherein the input end of the switch capacitance integrator is connected with the input voltage V in . Switch sampling capacitor C S In the normal working process, two working periods are existed, namely a sampling working period and an integration working period, and the sampling capacitor C is switched at the same time S The working period of the switch capacitor integrator is provided with a sampling state and an integrating state, and the first switch S can be controlled by a sampling pulse clock 1 Fourth switch S 4 Seventh switch S 7 Is controlled by integrating pulse clocksTwo switches S 2 Third switch S 3 Fifth switch S 5 Sixth switch S 6 To switch on and off the sampling capacitor C S Different working periods are entered, so that different working states of the switched capacitor integrator are controlled. Capacitive load C L Is the load existing at the output end of the circuit of the switched capacitor integrator in the actual working process. Feedback capacitor C I In the circuit of the switched capacitor integrator, a feedback capacitor C I The function of the integrating state of the switched capacitor integrator is implemented together with the operational amplifier 101. Passive charge compensation capacitor C C The slew rate of the switched capacitor integrator can be improved by a capacitance compensation mode without increasing excessive circuit area.
Specifically, during circuit operation, when the switch samples the capacitor C S In a sampling working period, i.e. when the switched capacitor integrator is in a sampling state, the first switch S 1 Fourth switch S 4 Seventh switch S 7 Closing a second switch S 2 Third switch S 3 Fifth switch S 5 Sixth switch S 6 Off, the output voltage V of the previous cycle of the operational amplifier 101 out (n-1) is stored in the passive charge compensation capacitor C C In (a) and (b); when the switch sampling capacitor C S In the integration working period, the switched capacitor integrator enters an integration state, and a first switch S 1 Fourth switch S 4 Seventh switch S 7 Open, second switch S 2 Third switch S 3 Fifth switch S 5 Sixth switch S 6 Closing, feedback capacitance C I And capacitive load C L The charge on the polar plate changes, and the charge Q (n) transferred in the period satisfies the input voltage V in the period in (n) the output voltage V of the operational amplifier 101 after sampling the period out (n) a relationship as follows:
passive electricityCharge compensation capacitor C C Charge transfer amount Q of (2) c (n) satisfies the formula:
Q c (n)＝C C (V in (n)-(V out (n)-V out (n-1)))；
the deduction can be obtained:
according to the law of total charge conservation, when the switching time of the integration period is 0, a passive charge compensation capacitor C can be obtained C Is not optimized for capacitance C' C The following formula is satisfied:
whereas the input of the operational amplifier 101 has an equivalent capacitance C A When considering the equivalent capacitance C at the input of the operational amplifier 101 A Then, a conversion time formula of the sampling period and a conversion time formula of the integration period of the switched capacitor integrator can be obtained. When the conversion time in the actual sampling period is shorter than the conversion time in the sampling period, or the conversion time in the actual integration period is shorter than the conversion time in the integration period, the distortion of the switched capacitor integrator is caused, so that the sigma-delta modulator is affected. The switching time of the integration period increases with the decrease of the capacitance value of the passive charge compensation capacitor, when the passive charge compensation capacitor C C The capacitance value of (2) is an unoptimized capacitance value C' C The switching time of the integration period is 0, but the switching time of the sampling period is not the shortest time at this time. The conversion time formula of the sampling period and the conversion time formula of the integration period can be obtained by equaling the two, and the passive charge compensation capacitor C can be obtained by establishing an equation C Is of the optimized capacitance C O Optimizing capacitance value C O As passive charge compensation capacitor C C The capacitance value of the switch capacitor integrator can obtain better signal-to-noise distortion ratio, and the addition of an active compensation mode is avoidedAnd the circuit area is reduced, and the total power consumption of the circuit is reduced.
The invention provides a switched capacitor integrator and a sigma-delta modulator based on an optimized passive charge compensation capacitor, wherein the switched capacitor integrator comprises a switched sampling capacitor, an operational amplifier, a feedback capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a capacitive load and the passive charge compensation capacitor. Meanwhile, by providing the passive charge compensation capacitor, the addition of an active compensation module in a circuit is avoided, and compared with the prior art, the circuit area is reduced and the total power consumption of the circuit is reduced under the condition of reaching the signal-to-noise distortion ratio of the sigma-delta modulator in the same ADC.
Fig. 2 is a schematic circuit diagram of another switched capacitor integrator based on optimizing a passive charge compensation capacitor according to an embodiment of the present invention, as shown in fig. 2, fig. 2 shows an equivalent capacitor C at a first input terminal of an operational amplifier 101 A The equivalent capacitance C is supplemented in the circuit schematic diagram of the switch capacitance integrator A A second end of the capacitor C is connected with the first input end of the operational amplifier 101 A Is grounded to the second input terminal of the operational amplifier 101. Further, during the sampling duty cycle, the voltage at the first input terminal of the operational amplifier 101 satisfies:
during the integration duty cycle, the voltage at the first input of the operational amplifier 101 satisfies:
wherein v is in_S Voltage at sampling duty cycle for the first input of operational amplifier 101，v in_I V, the voltage at the first input of the operational amplifier 101 during the integration duty cycle in For input voltage, C A Is the equivalent capacitance value C of the first input terminal of the operational amplifier 101 C Compensating the capacitor C for passive charge C Capacitance value C of (C) I For feeding back capacitance C I Capacitance value C of (C) L For capacitive load C L Is a capacitance value of (a).
Specifically, the sampling duty cycle is the switched sampling capacitance C S The amount of charge reaches the time interval required for stabilization from the beginning. When considering the equivalent capacitance C of the first input terminal of the operational amplifier 101 A Thereafter, during the sampling period, the voltage v at the first input of the operational amplifier 101 in_S And input voltage v in The following are satisfied:
by the above relation, when the input voltage is input, the passive charge compensates the capacitor C C Capacitance value of (C), feedback capacitance C I Capacitance of (C), capacitive load C L The switch sampling capacitor C can be obtained when the capacitance of the first input terminal of the operational amplifier 101 and the equivalent capacitance of the second input terminal are known S During the sampling duty cycle, the voltage v at the first input of the operational amplifier 101 in_S 。
Similarly, when considering the equivalent capacitance C of the first input terminal of the operational amplifier 101 A Then, according to the small signal equivalent circuit of the switch capacitance integrator, the capacitor C is sampled at the switch S The voltage v at the first input of the operational amplifier 101 in_I And input voltage v in The following are satisfied:
by the above relation, when the input voltage is input, the passive charge compensates the capacitor C C Capacitance value of (C), feedback capacitance C I Capacitance of (C), capacitive load C L The switch sampling capacitor C can be obtained when the capacitance of the first input terminal of the operational amplifier 101 and the equivalent capacitance of the second input terminal are known S During the integration period, the voltage v at the first input of the operational amplifier 101 in_I 。
Further, the sampling duty cycle time satisfies:
the integration duty cycle time satisfies:
wherein t is S For sampling the time of the working period, t I For integrating the time of the duty cycle, SR I For slew rate, SR of op amp 101 during the integration duty cycle S For the slew rate, V, of the operational amplifier 101 during the sampling duty cycle c Is the threshold voltage of the operational amplifier 101.
Wherein the sampling working period time is the switch sampling capacitor C S The time required for the charge quantity to reach the stabilization from the beginning is the time required for the integration work period to reach the stabilization from the beginning of the integration output charge quantity of the switched capacitor integrator.
Specifically, the switched capacitor integrator has two operating states, namely a sampling state and an integrating state, during normal operation, corresponding to the sampling duty cycle and the integrating duty cycle of the switched capacitor, respectively, and the switching of the operating states of the switched capacitor integrator means that a step excitation is input to the operational amplifier 110, and the response of the operational amplifier 110, that is, the change of the output voltage, has a certain delay, when the input step voltage is greater than the threshold voltage V c Only when the output voltage is changed, the critical voltage V c Overdrive voltage V of differential input pair transistor of operational amplifier 110 ov The formula is satisfied as follows:
slew rate SR of operational amplifier 101 during sampling duty cycle S The calculation process is as follows: total capacitive load C at output node of switched capacitor integrator in sampling state T_S Equal to the formula:
total capacitive load C T_S For the total capacitance value of the switched-capacitor integrator in the sampling state, the total capacitive load C at the output node of the switched-capacitor integrator in the sampling state is obtained T_S Then, according to the output current I of the operational amplifier 101 O The slew rate SR of the operational amplifier 101 during the sampling duty cycle is obtained S The method comprises the following steps:
slew rate SR S The slew rate of the output voltage of the operational amplifier 101 is reflected by adding a passive charge compensation capacitor C C The slew rate SR of the operational amplifier 101 in the switched capacitor integrator can be optimized without increasing excessive circuit area S Thereby optimizing the signal-to-noise-and-distortion ratio of the ADC as a whole.
The slew rate SR of the operational amplifier 101 is obtained S Then, the voltage v at the first input terminal of the operational amplifier 101 can be used as in_S Obtaining the time t of the sampling working period S 。
Slew rate SR of operational amplifier 101 during integration duty cycle I The calculation process is as follows: total capacitive load C at output node of switched capacitor integrator in integrating state T_I Equal to the formula:
total capacitive load C T_I For the total capacitance value of the switched-capacitor integrator in the integrated state, the total capacitive load C at the output node of the switched-capacitor integrator in the integrated state is obtained T_S Then, according to the output current I of the operational amplifier 101 O The slew rate SR of the operational amplifier 101 during the integration duty cycle is obtained I The method comprises the following steps:
the slew rate SR of the operational amplifier 101 during the integration duty cycle is obtained I Then, the voltage v at the first input terminal of the operational amplifier 101 can be used as in_I Obtaining the time t of the integration working period I 。
Further, a passive charge compensation capacitor C C The capacitance value of (2) satisfies:
t S ＝t I ；
passive charge compensation capacitor C obtained by the formula C Capacitance C of (2) C To optimize the capacitance value C O 。
Specifically, the time t of the integration duty cycle I Along with C C The capacitance value of the passive charge compensation capacitor decreases and increases, when the passive charge compensation capacitor C C The capacitance value of (2) is an unoptimized capacitance value C' C Time t of integration duty cycle I 0, but at this time the time t of the sampling duty cycle S FIG. 3 shows a passive charge compensation capacitor C according to an embodiment of the present invention C Respectively adopt the non-optimized capacitance value C' C And optimizing capacitance value C O The obtained time-dependent voltage curve of the input end of the switched capacitor integrator is shown in fig. 3, in which the integrating working period and the curve section in the sampling working period are the time of the integrating working period and the time of the sampling working period of the switched capacitor integrator, respectively, and the passive charge compensation capacitor C C Using non-optimised capacitance C' C Sampling engineering of switched capacitor integratorThe time of the working period is longer than that of the passive charge compensation capacitor C C With optimised capacitance C O Time of sampling duty cycle. Thus, the time t of the sampling duty cycle can be obtained by calculation S And time t of the integration duty cycle I The formula is equal to the formula, and the passive charge compensation capacitor C can be obtained by establishing the formula C Is of the optimized capacitance C O Optimizing capacitance value C O As passive charge compensation capacitor C C The capacitance value of the switch capacitor integrator can enable the switch capacitor integrator to obtain better signal-to-noise distortion ratio, the addition of an active compensation module is avoided, the circuit area is reduced, and the total power consumption of the circuit is reduced.
Further, the total capacitive load C at the output of the operational amplifier 110 during the sampling period T_S The method meets the following conditions:
the total capacitive load C at the output of the operational amplifier 110 during the integration duty cycle T_I The method meets the following conditions:
the total capacitive load of the output end of the operational amplifier is the total capacitance value of the output end of the operational amplifier.
Further, the cutoff frequency of the transconductance of the operational amplifier 110 and the bandwidth of the switched capacitor integrator at the sampling duty cycle satisfies:
the transconductance of the operational amplifier 110 and the cutoff frequency of the bandwidth of the switched capacitor integrator at the integration duty cycle satisfy:
wherein g m Is the transconductance of an operational amplifier, f S F is the cut-off frequency of the bandwidth of the switched capacitor integrator at the sampling duty cycle I Is the cut-off frequency of the bandwidth of the switched capacitor integrator at the integration duty cycle.
Specifically, for a switched capacitor integrator, the cut-off frequency is a characteristic index of the switched capacitor integrator, and designing a switched capacitor integrator specifies the target value of the parameter by adding the passive charge compensation capacitor C C The cut-off frequency of the bandwidth of the switched capacitor integrator can be improved, and a better signal-to-noise-and-distortion ratio is obtained.
Further, a first switch S 1 Fourth switch S 4 Seventh switch S 7 A second switch S controlled by the sampling pulse clock CLK1 2 Third switch S 3 Fifth switch S 5 A sixth switch S controlled by the integral pulse clock CLK2 6 Controlled by the compensated pulse clock CLK 3.
In the sampling working period, the sampling pulse clock CLK1 is high level, and the integration pulse clock CLK2 and the compensation pulse clock CLK3 are low level; in the integration duty cycle, the sampling pulse clock CLK1 is low, and the integration pulse clock CLK2 and the compensation pulse clock CLK3 are high.
Specifically, fig. 4 is a timing chart of a sampling pulse clock CLK1, an integration pulse clock CLK2 and a compensation pulse clock CLK3 according to an embodiment of the invention, as shown in fig. 4, in a switched sampling capacitor C S The sampling pulse clock CLK1 is high and the integration pulse clock CLK2 and the compensation pulse clock CLK3 are low, thereby causing the first switch S to 1 Fourth switch S 4 Seventh switch S 7 Closing a second switch S 2 Third switch S 3 Fifth switch S 5 Sixth switch S 6 Switching off, and enabling the switched capacitor integrator to enter a sampling state; in the switch sampling capacitor C S The sampling pulse clock CLK1 is low and the integration pulse clock CLK2 and the compensation pulse clock CLK3 are lowHigh level, thereby causing the first switch S 1 Fourth switch S 4 Seventh switch S 7 Open, second switch S 2 Third switch S 3 Fifth switch S 5 Sixth switch S 6 And closing, and enabling the switched capacitor integrator to enter an integration state. Wherein the compensation pulse clock CLK3 is applied to the switch sampling capacitor C S Is only high in the initial stage and is low in the subsequent stage, so that the integrated duty cycle of the (a) is controlled by the sixth switch S 6 Is connected with input voltage V in And voltage compensation is carried out on the integrating process of the switched capacitor integrator, so that the integrating state process of the switched capacitor integrator is quickened, and the time of an integrating working period is shortened.
Further, in the sampling working period, the voltage v of the output end of the operational amplifier out_S The method meets the following conditions:
specifically, the voltage v at the first input terminal of the operational amplifier 101 is obtained in_S And input voltage v in After the relation between the two, the voltage v of the output end of the operational amplifier can be obtained out_S 。
Fig. 5 is a schematic diagram of a structure of a sigma-delta modulator according to an embodiment of the present invention, and as shown in fig. 5, the sigma-delta modulator 200 includes the switched-capacitor integrator 100 based on the optimized passive charge compensation capacitor according to the above embodiment.
Illustratively, an optimized capacitance value C is employed O Contrast non-optimized capacitance C' C The capacitance value is reduced by 64.2%, so that the circuit area of the sigma-delta modulator is reduced, and meanwhile, the capacitor C is compensated by the passive charge C The bandwidth f of the switched capacitor integrator increases with decreasing capacitance value, expressed as follows:
f＝min{f S ，f I }
optimizing capacitance C by sampling O The signal-to-noise-and-distortion ratio of the corresponding sigma-delta modulator can be improved by more than 10dB, and an optimized capacitance value C is adopted O Sigma-delta modulator signal-to-noiseThe distortion ratio is highest.
The invention provides a sigma-delta modulator which obtains better signal-to-noise-and-distortion ratio by providing a passive charge compensation capacitor. Meanwhile, the addition of an active compensation module in the circuit is avoided, and compared with the prior art, the circuit area is reduced and the total power consumption of the circuit is reduced under the condition of reaching the signal-to-noise distortion ratio of the sigma-delta modulator in the same ADC.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (10)

1. The switched capacitor integrator based on the optimized passive charge compensation capacitor is characterized by comprising a switched sampling capacitor, an operational amplifier, a feedback capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a capacitive load and the passive charge compensation capacitor;
the first end of the first switch is connected with the input end of the switch capacitor integrator, and the second end of the first switch is connected with the second end of the second switch and the first end of the switch sampling capacitor; the second end of the switch sampling capacitor is connected with the first end of the third switch and the second end of the fourth switch, and the second end of the third switch is connected with the first input end of the operational amplifier and the first end of the feedback capacitor; the output end of the operational amplifier is connected with the first end of the fifth switch, the second end of the feedback capacitor and the second end of the passive capacitance compensation capacitor, and the first end of the fifth switch is connected with the first end of the capacitive load; the first end of the passive charge compensation capacitor is connected with the second end of the sixth switch and the second end of the seventh switch, and the first end of the sixth switch is connected with the input voltage; a first end of the second switch, a first end of the fourth switch, a first end of the seventh switch, a second end of the capacitive load, and a second input terminal of the operational amplifier are grounded;
the working process of the switch sampling capacitor comprises a sampling working period and an integration working period; during the sampling duty cycle, the first switch, the fourth switch, and the seventh switch are closed, and the second switch, the third switch, the fifth switch, and the sixth switch are opened; during the integration duty cycle, the first switch, the fourth switch, and the seventh switch are open, and the second switch, the third switch, the fifth switch, and the sixth switch are closed.
2. The switched-capacitor integrator based on optimized passive charge compensation capacitance of claim 1 wherein during the sampling duty cycle the voltage at the first input of the operational amplifier satisfies:
during the integration duty cycle, the voltage at the first input of the operational amplifier satisfies:
wherein v is in_S V being the voltage of the first input of the operational amplifier at the sampling duty cycle in_I V being the voltage at the first input of the operational amplifier during the integration period in For the input voltage, C A For the equivalent capacitance value of the first input end of the operational amplifier, C C Make up for the passive chargeCapacitance value of compensation capacitor C I C is the capacitance value of the feedback capacitor L Is the capacitance value of the capacitive load.
3. The switched-capacitor integrator based on optimized passive charge compensation capacitance of claim 2 wherein the time of the sampling duty cycle satisfies:
the integration duty cycle time satisfies:
wherein t is S T is the time of the sampling work period I For the time of the integration duty cycle, SR I For the slew rate, SR of the operational amplifier during the integration duty cycle S For the slew rate of the operational amplifier in the sampling working period, V c Is the threshold voltage of the operational amplifier.
4. A switched-capacitor integrator based on an optimised passive charge compensation capacitor as claimed in claim 3, wherein the capacitance value of the passive charge compensation capacitor satisfies:
t S ＝t I ；
the capacitance value C of the passive charge compensation capacitor obtained by the formula C To optimize the capacitance value C O 。
5. The switched-capacitor integrator based on optimized passive charge compensation capacitance as claimed in claim 2, wherein the total capacitive load C at the output of the operational amplifier at the sampling duty cycle T_S The method meets the following conditions:
the total capacitive load C at the output of the operational amplifier during the integration period T_I The method meets the following conditions:
6. the switched-capacitor integrator based on optimized passive charge compensation capacitance of claim 4 wherein the transconductance of the operational amplifier and the cutoff frequency of the bandwidth of the switched-capacitor integrator at the sampling duty cycle satisfy:
the cutoff frequency of the transconductance of the operational amplifier and the bandwidth of the switched capacitor integrator at the integration duty cycle satisfies:
wherein g m Is the transconductance of the operational amplifier, f S F is the cut-off frequency of the bandwidth of the switched capacitor integrator at the sampling duty cycle I Is the cut-off frequency of the bandwidth of the switched capacitor integrator at the integration duty cycle.
7. The switched-capacitor integrator based on optimized passive charge compensation capacitance of claim 1 wherein the first, fourth and seventh switches are clocked by a sampling pulse, the second, third and fifth switches are clocked by an integration pulse, and the sixth switch is clocked by a compensation pulse.
8. The switched-capacitor integrator based on optimized passive charge compensation capacitance of claim 7 wherein during the sampling duty cycle the sampling pulse clock is high and the integration pulse clock and the compensation pulse clock are low; and in the integration working period, the sampling pulse clock is in a low level, and the integration pulse clock and the compensation pulse clock are in a high level.
9. The switched-capacitor integrator based on optimized passive charge compensation capacitor of claim 2 wherein the voltage v at the output of the operational amplifier during the sampling duty cycle out_S The method meets the following conditions:
10. a sigma-delta modulator comprising the switched-capacitor integrator of any of claims 1-8 based on an optimized passive charge compensation capacitor.
CN202311480478.4A 2023-11-08 2023-11-08 Switched capacitor integrator based on optimized passive charge compensation capacitance and sigma-delta modulator Pending CN117375609A (en)

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