CN117375384B - Specific detuning modulation method for width modulation ratio of two-stage five-level current source inverter - Google Patents

Specific detuning modulation method for width modulation ratio of two-stage five-level current source inverter Download PDF

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CN117375384B
CN117375384B CN202311414958.0A CN202311414958A CN117375384B CN 117375384 B CN117375384 B CN 117375384B CN 202311414958 A CN202311414958 A CN 202311414958A CN 117375384 B CN117375384 B CN 117375384B
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zero vector
stage
switching
vector
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CN117375384A (en
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王伟琦
夏晓婷
房绪鹏
周厚银
毕华坤
张玉敏
于永进
魏龙飞
祝延凯
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Shandong University of Science and Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • H02M7/53876—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output based on synthesising a desired voltage vector via the selection of appropriate fundamental voltage vectors, and corresponding dwelling times

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention discloses a specific harmonic elimination modulation method of a wide modulation ratio of a two-stage five-level current source inverter, which belongs to the field of current source inverters, adopts the two-stage five-level current source inverter and comprises the following steps: setting the number of harmonic frequencies and the number of switching angles to be eliminated; in the minimum modulation unit (0, pi/6), introducing a zero vector at the moment when the power switch S 5 is turned off and the power switch S 1 is turned on, and determining the type of vector combination in the minimum modulation unit according to the number of switch angles; determining a switching mode of a switch in a minimum modulation unit; constructing a driving pulse model of the power switch S 1～S8 and determining an output current waveform; solving the magnitude of each switching angle under different modulation ratios, and realizing specific harmonic elimination modulation. According to the invention, by designing the pulse sequence of the power switch, a zero vector state is reasonably introduced into the pulse model of the power switch, the adjustable range of the modulation ratio is widened, and the loss of the power switch S 1～S6 of the rear-stage circuit is reduced.

Description

Specific detuning modulation method for width modulation ratio of two-stage five-level current source inverter
Technical Field
The invention belongs to the technical field of current source inverters, and particularly relates to a specific harmonic elimination modulation method for a wide modulation ratio of a two-stage five-level current source inverter.
Background
The current source inverter (Current Source Inverter, CSI) is an interface device for connecting new energy and a power grid, has boosting property and good fault tolerance, and is applied to renewable energy power generation systems such as photovoltaic power generation and wind power generation. In a high-power application scenario, in order to reduce the current stress of a power switch and improve the output capacity and the electric energy quality of an integral converter, a current source inverter often adopts a multi-level technical scheme. A typical topology of a conventional three-phase five-level current source inverter is shown in fig. 1, and is generally constructed by parallel integration of 2 three-phase three-level current source inverters. In terms of modulation, high power current source inverters are typically operated at lower switching frequencies to reduce switching losses, which also results in a substantial increase in harmonics of the output current, affecting power quality. The specific harmonic cancellation modulation (Selected Harmonic Elimination Pulse Width Modulation, shewm) technique, also referred to simply as specific harmonic cancellation modulation technique, is an effective method for alleviating the problem of harmonics of an inverter at low switching frequencies by calculating the switching time of the power switch to cancel the lower harmonics.
The two-stage five-level current source inverter is a novel multi-level CSI topological structure and comprises a front-stage circuit and a rear-stage circuit, wherein the front-stage circuit is added with a double-T-shaped parallel circuit, the rear-stage circuit keeps an original H6 converter bridge, five-level output is realized through only eight power switching tubes, and compared with the traditional five-level CSI, the five-level current source inverter can output five-level current through fewer power switching devices, is simple and convenient to operate and has a better cost performance. But so far, there is no intensive study for implementing the shewm modulation method.
When a conventional five-level current source inverter performs a specific harmonic cancellation technique, a zero vector is not generally introduced to reduce the number of switching actions and thus the power loss. According to the technical scheme, if the two-stage five-level current source inverter is used without modification, the problem that the modulation ratio is limited when specific harmonic cancellation modulation is performed is faced. For example, 3 switching angles are set, namely alpha 1、α2、α3 and 5 th、7th harmonic waves are eliminated, an output current waveform is shown in fig. 2, a switching angle solving result is shown in fig. 3, and the adjustable range of the modulation ratio is only (0.7,0.89); setting 5 switch angles, namely alpha 1、α2、α3、α4、α5 and eliminating 5 th、7th、11th、13th harmonic, wherein the output current waveform is shown in fig. 4, the solving result of the switch angles is shown in fig. 5, and the adjustable range of the modulation ratio is only (0.82,0.83).
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a specific harmonic elimination modulation method for the width modulation ratio of a two-stage five-level current source inverter, which is reasonable in design, overcomes the defects in the prior art and has a good effect.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
The specific harmonic elimination modulation method of the wide modulation ratio of the two-stage five-level current source inverter adopts the two-stage five-level current source inverter, the topological structure of the two-stage five-level current source inverter comprises a front-stage structure and a rear-stage structure, the front-stage structure is a double-T-shaped parallel circuit, the front-stage structure is composed of a voltage source U dc, two parallel power switching tubes S 7、S8, two inductors L 1、L2 with the same electrical parameters and a diode D 1、D2, and the rear-stage structure is a H6 converter bridge and is composed of six power switching tubes S 1～S6, a filter capacitor C A、CB、CC and a three-phase load; the method comprises the following steps:
s1, setting harmonic frequency and switching angle number to be eliminated;
S2, introducing a zero vector at the moment when the power switch tube S 5 is turned off and the power switch tube S 1 is turned on in the minimum modulation unit (0, pi/6), and determining the type of vector combination in the minimum modulation unit according to the number of switch angles;
S3, determining a switching mode of a switch in the minimum modulation unit;
S4, constructing a driving pulse model of the power switch S 1～S8 and determining an output current waveform according to the switching mode and the driving pulse limiting condition of the power switch S 1～S8;
S5, carrying out Fourier decomposition on the modulated output current waveform I a to obtain an n-order harmonic expression I a,n of the output current, enabling I a,n =0, simultaneously controlling the magnitude of the modulation ratio m, writing a nonlinear equation set, solving the magnitude of each switching angle under different modulation ratios, and realizing specific harmonic elimination modulation.
Further, the power switching tube S 1～S6 is a common low-speed power switching tube with reverse blocking capability, and comprises a GTO, a reverse blocking IGCT and a reverse blocking IGBT module.
Further, the power switching transistors S 7 and S 8 select a fully controlled device with reverse blocking capability and high-speed commutation capability, and the fully controlled device comprises a reverse blocking high-speed IGBT module and a silicon carbide-based reverse blocking MOSFET.
Further, the topological structure of the two-stage five-level current source inverter is converted by the action of a power switch tube S 1、S5 of a rear-stage structure in a minimum modulation unit; the output current includes a non-zero vector state and a zero vector state, the non-zero vector state including a large vector state and a small vector state; in a minimum modulation unit (0, pi/6), introducing a zero vector at the moment when the power switch tube S 5 is turned off and the power switch tube S 1 is turned on, wherein the zero vector is configured between two non-zero vectors, so that the switching action of zero current switching can be completed in a zero vector interval by two non-zero vector switch combinations adjacent to each other in front and back;
Starting from the time t=0, sequentially cycling by taking three vector states of a non-zero vector, a zero vector and a non-zero vector as minimum units; the minimum intra-modulation unit vector combinations are classified into three types: the number of the type-one switching angles is N=3k, k=1, 2,3, …, and the vector state before the time of T=pi/6 is zero vector, non-zero vector and non-zero vector; the number of the type two switch angles is N=3k+1, k=1, 2,3, …, and the vector state before the time of T=pi/6 is a non-zero vector, a non-zero vector and a zero vector; the number of the three switch angles of the type is N=3k+2, k=0, 1,2, …, and the vector state before the time of T=pi/6 is a non-zero vector, a zero vector and a non-zero vector.
Further, the non-zero vector of the mode one is formed by alternately distributing large vectors and small vectors, the modulation ratio adjustable range is between the mode two and the mode three, and the output current harmonic distortion rate is also between the mode two and the mode three; the number of small vectors in the minimum modulation unit is more than that of large vectors in the second mode, the harmonic distortion rate of the mode output current is lower than that of the first mode and the third mode, the output electric energy quality is high, and the modulation ratio adjustable range is smaller than that of the first mode and the third mode; the number of large vectors in the minimum modulation unit is more than the number of small vectors in the mode III, the adjustable range of the mode modulation ratio is larger than that of the mode I and the mode II, the harmonic distortion rate of the output current is higher than that of the mode I and the mode II, and the output power quality is lower than that of the mode I and the mode II; an appropriate switching pattern is selected based on the adjustable range of the modulation ratio and the harmonic distortion rate of the output current.
Further, the zero vector state is obtained when the power switching transistors S 7 and S 8 are turned on together, the large vector state is obtained when the power switching transistors S 7 and S 8 are both turned off, and the small vector state is obtained when the power switching transistors S 7 and S 8 are turned on one by one.
Further, in S3, the driving pulse of the power switch tube S 1～S6 needs to satisfy the following conditions: taking (0, 2 pi) as a period, the power switch tube S 1 is kept on at (pi/3, 2 pi/3), and the driving pulses of the power switch tube S 1～S6 are sequentially different by pi/3; the drive pulse period of the power switching transistors S 7 and S 8 is pi/3.
Further, in S4, the expression of the post-fourier-decomposition output current i (ωt) is:
the n-th harmonic expression of the output current is:
the modulation ratio m satisfies the following formula:
Wherein, I a,1 is fundamental wave amplitude, and I dc is direct current side current.
The beneficial technical effects are as follows:
The invention provides a specific harmonic elimination modulation method of a two-stage five-level current source inverter wide modulation ratio, which reasonably introduces a zero vector state into a pulse model of a power switch by designing a pulse sequence of the power switch, widens the adjustable range of the modulation ratio, and simultaneously reduces the loss of a power switch S 1～S6 of a later-stage circuit.
Drawings
Fig. 1 is a schematic diagram of a topology of a conventional three-phase five-level current source inverter;
FIG. 2 is a waveform diagram of three-phase output current when a conventional two-stage five-level current source inverter performs a specific harmonic cancellation technique to set 3 switching angles;
FIG. 3 is a diagram of the switching angle solution when a conventional two-stage five-level current source inverter performs a specific harmonic cancellation technique to set 3 switching angles;
FIG. 4 is a waveform diagram of three-phase output current when a conventional two-stage five-level current source inverter performs a specific harmonic cancellation technique to set 5 switching angles;
FIG. 5 is a diagram of the switching angle solution when a conventional two-stage five-level current source inverter performs a specific harmonic cancellation technique to set 5 switching angles;
FIG. 6 is a topology diagram of a two-stage five-level current source inverter of the present invention;
FIG. 7 is a device selection diagram of a power switch S 1～S6 in the present invention;
wherein (a) is a GTO; (b) is a reverse blocking IGCT; (c) is a reverse blocking IGBT;
FIG. 8 is a device selection diagram of power switching transistors S 7 and S 8 in the present invention;
Wherein, (a) is a reverse blocking type high speed IGBT; (b) is a silicon carbide based reverse blocking MOSFET;
FIG. 9 is a graph of sinusoidal modulation wave and current state for a dual stage five-level current source inverter according to the present invention;
FIG. 10 illustrates a switch state around pi/6 for example of the invention for performing switch mode one;
FIG. 11 illustrates a switch state of type two around pi/6 for example of the invention for performing switch mode one;
FIG. 12 is a diagram of the present invention for example of performing switch mode one, type three switch states around pi/6;
FIG. 13 is a pulse model diagram of the power switch S 1～S6 in example 1;
FIG. 14 is a waveform diagram of the pulse patterns of the switch mode-power switches S 7 and S 8 and the output current i a in the embodiment 1;
FIG. 15 is a graph showing the result of solving the switching angle of the first switching pattern in example 1;
FIG. 16 is a waveform diagram of the pulse patterns of the switch mode two power switches S 7 and S 8 and the output current i a in the embodiment 1;
FIG. 17 is a diagram showing the result of solving the switching angle of the second switching pattern in example 1;
FIG. 18 is a pulse pattern diagram of the power switch S 1～S6 in example 2;
FIG. 19 is a waveform diagram of the pulse patterns of the switch mode-power switches S 7 and S 8 and the output current i a in the embodiment 2;
FIG. 20 is a graph showing the result of solving the switching angle of the first switching pattern in example 2;
FIG. 21 is a waveform diagram of the pulse patterns of the switch mode two power switches S 7 and S 8 and the output current i a in example 2;
FIG. 22 is a diagram showing the result of solving the switching angle of the second switching pattern in example 2;
FIG. 23 is a waveform diagram of the pulse patterns of the switch-mode three-power switches S 7 and S 8 and the output current i a in example 2;
FIG. 24 is a diagram showing the result of solving the switching angle of the third switching pattern in example 2;
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and examples. The examples described below are by way of example only and are not to be construed as limiting the invention. It should be understood that in the description of the present invention, references to orientations or positional relationships as indicated in the top, bottom, upper, lower, left, right, etc. are based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In order to further illustrate the technical solution of the present invention, a detailed description will be given below with reference to a plurality of specific embodiments.
The specific harmonic elimination modulation method of the wide modulation ratio of the two-stage five-level current source inverter adopts the two-stage five-level current source inverter, as shown in fig. 6, the topological structure of the two-stage five-level current source inverter comprises a front-stage structure and a rear-stage structure, the front-stage structure is a double-T-shaped parallel circuit, the front-stage structure is composed of a voltage source U dc, two parallel power switching tubes S 7、S8, two inductors L 1、L2 with the same electrical parameters and a diode D 1、D2, and the rear-stage structure is an H6 converter bridge and is composed of six power switching tubes S 1～S6, a filter capacitor C A、CB、CC and a three-phase load;
The power switching tube S 1～S6 reserves the configuration scheme of the traditional high-power current source inverter, and selects a common low-speed power switching tube with reverse blocking capability, such as GTO, reverse blocking IGCT, reverse blocking IGBT module and the like, as shown in figure 7;
The power switching tubes S 7 and S 8 are full-control devices with reverse blocking capacity and high-speed current conversion capacity, and the full-control devices comprise a reverse blocking type high-speed IGBT module and a silicon carbide based reverse blocking type MOSFET, as shown in fig. 8;
The switch combination state of the topology is shown in table 1, and the output current has two states, namely a non-zero vector state and a zero vector state (I 0), wherein the non-zero vector state is divided into a large vector state (I 1、I2、I3、I4、I5、I6) and a small vector state (I 7、I8、I9、I10、I11、I12). Through the mutual cooperation of different switches, the five-level current of 0, +/-0.5I dc,±Idc can be output. The output current state is determined by the front-stage current power switching transistors S 7 and S 8, the power switching transistors S 7 and S 8 are in zero vector state when being jointly conducted, the power switching transistors S 7 and S 8 are in large vector state when being both turned off, and the power switching transistors S 7 and S 8 are in small vector state when being turned on and off, as shown in FIG. 9;
Table 1: a two-stage five-level current source inverter switching state;
Note that: when the front-stage power switches S 7 and S 8 are conducted together, the rear-stage H6 converter bridge is short-circuited, and whether the power switch S 1～S6 in the rear-stage circuit is on or not does not affect the zero vector state of the circuit.
Let the initial free angle (switching angle) be α, the number of switching angles α be N. Taking (0, 2 pi) as a period, the constraint conditions of the method of the invention are as follows:
(1) The output current (taking a phase as an example, the phases of the output three-phase current i a,ib,ic differ by 2 pi/3 in sequence) needs to satisfy the condition: the output current satisfies half-wave symmetry, i.e., is centered about the (pi, 0) point; the output current satisfies quarter-wave symmetry, i.e. about the x=pi/2 axis.
(2) Taking a power switch tube S 1 as an example, the driving pulse of the power switch S 1～S6 needs to meet the condition that the power switch S 1 is kept on at (pi/3, 2 pi/3) in order to reduce the action times of the low-speed switch as much as possible; the drive pulses of the power switch tube S 1～S6 are sequentially different by pi/3.
(3) The drive pulse period of the power switching transistors S 7 and S 8 is pi/3.
(4) The conditions to be satisfied for the switching angle α are as follows:
0＜α1＜α2＜…＜αN＜π/6。
the specific detuning modulation method for the width modulation ratio of the two-stage five-level current source inverter specifically comprises the following steps:
s1, setting harmonic frequency and switching angle number to be eliminated;
S2, introducing a zero vector at the moment when the power switch tube S 5 is turned off and the power switch tube S 1 is turned on in the minimum modulation unit (0, pi/6), and determining the type of vector combination in the minimum modulation unit according to the number of switch angles;
The topological structure of the two-stage five-level current source inverter is converted in a minimum modulation unit by the action of a power switch tube S 1、S5 of a rear-stage structure; the output current includes a non-zero vector state and a zero vector state, the non-zero vector state including a large vector state and a small vector state; in the minimum modulation unit, zero vectors are introduced at the moment when the power switch tube S 5 is turned off and the power switch tube S 1 is turned on, and the zero vectors are configured between two non-zero vectors, so that the switching action of zero current switch can be completed in a zero vector interval by two non-zero vector switch combinations adjacent in front and back;
The vector combination in the minimum modulation unit of the invention, as shown in table 2, starts from the time t=0, takes three vector states of non-zero vector, zero vector and non-zero vector as minimum units, and loops in turn; as can be seen from Table II, the number of switching angles is different, and the vector states of the vector combinations around pi/6 are also different. The minimum intra-modulation unit vector combinations are therefore classified into three types: the number of the type-one switching angles is N=3k, k=1, 2,3, …, and the vector state before the time of T=pi/6 is zero vector, non-zero vector and non-zero vector; the number of the type two switch angles is N=3k+1, k=1, 2,3, …, and the vector state before the time of T=pi/6 is a non-zero vector, a non-zero vector and a zero vector; the number of the three switch angles of the type is N=3k+2, k=0, 1,2, …, and the vector state before the time of T=pi/6 is a non-zero vector, a zero vector and a non-zero vector.
Table 2: vector combining in minimum modulation unit
Tables 3, 4 and 5 list the vector combinations of each type within the minimum modulation unit, respectively, and the vector combinations of the three types within the minimum modulation unit differ only around pi/6. Under the precondition of meeting the requirement of outputting five-level current, large vectors and small vectors can be arbitrarily allocated theoretically.
Table 3: vector combination of type one (n=3k, k=1, 2,3, …) in minimum modulation unit and switch mode thereof
Table 4: vector combination of type two (n=3k+1, k=1, 2,3, …) in minimum modulation unit and switch mode thereof
Table 5: vector combination of type three (n=3k+2, k=0, 1,2, …) in minimum modulation unit and switch mode thereof
S3, determining a switching mode of a switch in the minimum modulation unit;
the minimum modulation unit is pi/6, and the switching state of one period can be determined only by determining the switching mode in the (0, pi/6) interval, so that only the switching mode in the (0, pi/6) interval is needed to be focused.
There are three types of switching modes: the non-zero vector of the mode one is formed by alternately distributing large vectors and small vectors, the mode is that the waveform of the output current (taking i a as an example) in the (0, pi/6) interval and the waveform in the (pi/6, pi/3) interval are in anti-mirror symmetry with respect to x=pi/6, the modulation ratio adjustable range is between the mode two and the mode three, usually (0, 0.8), and the harmonic distortion rate of the output current is also between the mode two and the mode three; the number of small vectors in the minimum modulation unit is more than the number of large vectors in the mode II, the mode output current is more similar to a sine wave, the harmonic distortion rate of the output current is lower, the harmonic distortion rate of the mode output current is lower than that of the mode I and the mode III, the output electric energy quality is high, but the modulation ratio adjustable range is smaller than that of the mode I and the mode III, and is usually (0,0.6); mode three has a larger number of large vectors than a smaller number of small vectors in the minimum modulation unit, the adjustable range of the mode modulation ratio is larger than that of mode one and mode two, usually (0, 1) but the harmonic distortion rate of the output current is higher than that of mode one and mode two, and the output power quality is lower than that of mode one and mode two; an appropriate switching pattern is selected based on the adjustable range of the modulation ratio and the harmonic distortion rate of the output current.
Taking the example of executing the first switching pattern, fig. 10 shows the switching state of the vector combination type one around pi/6, fig. 11 shows the switching state of the vector combination type two around pi/6, and fig. 12 shows the switching state of the vector combination type three around pi/6.
S4, constructing a driving pulse model of the power switch S 1～S8 and determining an output current PWM waveform according to the switching mode and the driving pulse limiting condition of the power switch S 1～S8;
S5, carrying out Fourier decomposition on the modulated output current PWM waveform I a to obtain an n-order harmonic expression I a,n of the output current, enabling I a,n =0, simultaneously controlling the magnitude of the modulation ratio m, writing a nonlinear equation set, solving the magnitude of each switching angle under different modulation ratios, and realizing specific harmonic elimination modulation.
Wherein, the expression of the output current i (ωt) after fourier decomposition is:
the n-th harmonic expression of the output current is:
the modulation ratio m satisfies the following formula:
Wherein, I a,1 is fundamental wave amplitude, and I dc is direct current side current.
The specific harmonic elimination modulation method of the two-stage five-level current source inverter wide modulation ratio provided by the invention has the advantages that the number of the switch angles can be any positive integer, and the limitation of parity is avoided. The invention widens the value range of the modulation ratio by reasonably introducing zero vector in the pulse model. In addition, the zero vector is introduced to enable the two non-zero vector switch combinations adjacent in front and back to complete zero current switch switching action in a zero vector interval, so that the switching loss of the power switch S 1～S6 of the rear-stage circuit is reduced.
The following two embodiments, n=3 (eliminating 5 th、7th harmonic wave), n=7 (eliminating 5 th、7th、11th、13th、17th、19th harmonic wave), specifically describe a specific tuning method of the two-stage five-level current source inverter wide modulation ratio proposed by the present invention:
Embodiment one:
3 switching angles are set to be alpha 1、α2、α3 respectively, and 5 th、7th harmonic waves are eliminated. This type switches the switching state 3 times in the (0, pi/6) interval, with one zero vector and three non-zero vectors. In order to meet the requirement that the output current is five-level, at least one large vector and one small vector in the non-zero vectors are available, and only one non-zero vector can be flexibly selected in the embodiment, so that the output current has only two switching modes.
Fig. 13 shows a pulse pattern of the post-stage power switch S 1～S6 when n=3. Since the output current is not affected by the back-stage power switches S 1～S6 but is determined by the front-stage circuit power switches S 7 and S 8, the pulse pattern of the back-stage power switch S 1～S6 is the same regardless of which switching mode is selected, except for the pulse patterns of the power switches S 7 and S 8 and the waveform of the output current.
This embodiment exemplifies two switch switching modes. The non-zero vectors of the switching pattern, which are in the minimum modulation interval, are uniformly and alternately distributed by the large vectors and the small vectors, as shown in fig. 14. Equation (4) performs an N-th harmonic expression of the switching mode one-time output current for n=10. Equation (6) is a nonlinear equation set to be solved, and the magnitude of each switch angle under different modulation ratios is obtained by solving the equation set. The switching angle solution for this mode at different modulation ratios is shown in fig. 15, with the modulation ratio adjustable range (0,0.89).
The number of small vectors is greater than the number of large vectors in the minimum modulation interval in the second switching mode, as shown in fig. 16. Equation (5) performs an N-th harmonic expression of the output current when the switching mode two is performed for n=10. The result of the switching angle solution for this mode at different modulation ratios is shown in fig. 17, with the modulation ratio adjustable range (0,0.52). Switch mode two has more small vectors within the minimum modulation unit and therefore the modulation ratio adjustable range is relatively small compared to switch mode one.
Embodiment two:
7 switch angles are set to be alpha 1、α2、α3、α4、α5、α6、α7 respectively, and 5 th、7th、11th、13th、17th、19th harmonic waves are eliminated. This type switches the switching state 7 times in the (0, pi/6) interval, with three zero vectors and five non-zero vectors, where the large and small vectors in the non-zero vectors can theoretically be arbitrarily allocated (there is at least one large vector and one small vector), so this type has a plurality of switching modes.
Fig. 18 shows a pulse pattern of the post-stage power switch S 1～S6 when n=7.
This embodiment enumerates three switch modes. The non-zero vectors of the switch mode-in the minimum modulation interval are uniformly and alternately distributed by the large vector states and the small vector states, as shown in fig. 19. Equation (7) performs an N-th harmonic expression of the switching mode one-time output current for n=10. Equation (10) is a nonlinear equation set to be solved, and the magnitude of each switch angle under different modulation ratios is obtained by solving the equation set. The result of the switching angle solution for this mode at different modulation ratios is shown in fig. 20, with the modulation ratio adjustable range (0,0.75).
The number of small vectors is greater than the number of large vectors in the minimum modulation interval in the second switching mode, as shown in fig. 21. Equation (8) performs an N-th harmonic expression of the output current when the switching mode two is performed for n=10. The result of the switching angle solution for this mode at different modulation ratios is shown in fig. 22, with the modulation ratio adjustable range (0,0.51). Since there are more small vectors in switch mode two, the modulation ratio adjustable range is relatively small compared to switch mode one.
The number of large vectors in the minimum modulation section is greater than the number of small vectors in the switching pattern three, as shown in fig. 23. Equation (9) performs an N-th harmonic expression of the switching mode three-time output current for n=10. The result of the switching angle solution for this mode at different modulation ratios is shown in fig. 24, with the modulation ratio adjustable range (0,0.95). In contrast to fig. 15, 17 and 19, the modulation ratio adjustable range of switch mode three is greater than switch mode one and switch mode two.
It should be understood that the above description is not intended to limit the invention to the particular embodiments disclosed, but to limit the invention to the particular embodiments disclosed, and that the invention is not limited to the particular embodiments disclosed, but is intended to cover modifications, adaptations, additions and alternatives falling within the spirit and scope of the invention.

Claims (8)

1. The specific harmonic elimination modulation method of the wide modulation ratio of the two-stage five-level current source inverter is characterized in that the two-stage five-level current source inverter is adopted, the topological structure of the two-stage five-level current source inverter comprises a front-stage structure and a rear-stage structure, the front-stage structure is a double-T-shaped parallel circuit, the front-stage structure is composed of a voltage source U dc, two parallel power switching tubes S 7、S8, two inductors L 1、L2 with the same electrical parameters and a diode D 1、D2, and the rear-stage structure is an H6 converter bridge and is composed of six power switching tubes S 1～S6, a filter capacitor C A、CB、CC and a three-phase load; the power switching tube S 1～S6 forms a three-phase bridge circuit, S 1、S3、S5 is an upper bridge arm switching tube, S 4、S6、S2 is a lower bridge arm switching tube, and the three phases a, b and c are respectively corresponding to each other; the method comprises the following steps:
s1, setting harmonic frequency and switching angle number to be eliminated;
S2, introducing a zero vector at the moment when the power switch tube S 5 is turned off and the power switch tube S 1 is turned on in the minimum modulation unit (0, pi/6), and determining the type of vector combination in the minimum modulation unit according to the number of switch angles;
S3, determining a switching mode of a switch in the minimum modulation unit;
S4, constructing a driving pulse model of the power switch S 1～S8 and determining an output current waveform according to the switching mode and the driving pulse limiting condition of the power switch S 1～S8;
S5, carrying out Fourier decomposition on the modulated output current waveform I a to obtain an n-order harmonic expression I a,n of the output current, enabling I a,n =0, simultaneously controlling the magnitude of the modulation ratio m, writing a nonlinear equation set, solving the magnitude of each switching angle under different modulation ratios, and realizing specific harmonic elimination modulation.
2. The specific tuning-out method of the width modulation ratio of the two-stage five-level current source inverter according to claim 1, wherein the power switching tube S 1～S6 is a common low-speed power switching tube with reverse blocking capability, and comprises a GTO, a reverse blocking IGCT and a reverse blocking IGBT module.
3. The specific tuning-out method of the width modulation ratio of the two-stage five-level current source inverter according to claim 1, wherein the power switching transistors S 7 and S 8 select fully-controlled devices with reverse blocking capability and high-speed commutation capability, and the fully-controlled devices comprise a reverse blocking high-speed IGBT module and a silicon carbide-based reverse blocking MOSFET.
4. The specific detuning modulation method for the wide modulation ratio of the two-stage five-level current source inverter according to claim 1, wherein the topology structure of the two-stage five-level current source inverter is commutated in a minimum modulation unit by the action of a post-stage structure power switch tube S 1、S5; the output current includes a non-zero vector state and a zero vector state, the non-zero vector state including a large vector state and a small vector state; in a minimum modulation unit (0, pi/6), introducing a zero vector at the moment when a power switch tube S 5 is turned off and a power switch tube S 1 is turned on, wherein the zero vector is configured between two non-zero vectors, so that a zero current switch switching action can be completed in a zero vector interval by two non-zero vector switch combinations adjacent to each other in front and back;
Starting from the time t=0, sequentially cycling by taking three vector states of a non-zero vector, a zero vector and a non-zero vector as minimum units; the minimum intra-modulation unit vector combinations are classified into three types: the number of the type-one switching angles is N=3k, k=1, 2,3, …, and the vector state before the time of T=pi/6 is zero vector, non-zero vector and non-zero vector; the number of the type two switch angles is N=3k+1, k=1, 2,3, …, and the vector state before the time of T=pi/6 is a non-zero vector, a non-zero vector and a zero vector; the number of the three switch angles of the type is N=3k+2, k=0, 1,2, …, and the vector state before the time of T=pi/6 is a non-zero vector, a zero vector and a non-zero vector.
5. The method for tuning a specific tuning of a width modulation ratio of a two-stage five-level current source inverter according to claim 4, wherein the switching patterns are three: the non-zero vector of the first mode is formed by alternately distributing large vectors and small vectors, the modulation ratio adjustable range of the non-zero vector is between the second mode and the third mode, and the amplitude of the harmonic distortion of the output current is also between the second mode and the third mode; the number of small vectors in the minimum modulation unit is more than that of large vectors in the second mode, the harmonic distortion rate of the mode output current is lower than that of the first mode and the third mode, the output electric energy quality is high, and the modulation ratio adjustable range is smaller than that of the first mode and the third mode; the number of large vectors in the minimum modulation unit is more than the number of small vectors in the mode III, the adjustable range of the mode modulation ratio is larger than that of the mode I and the mode II, the harmonic distortion rate of the output current is higher than that of the mode I and the mode II, and the output power quality is lower than that of the mode I and the mode II; an appropriate switching pattern is selected based on the adjustable range of the modulation ratio and the harmonic distortion rate of the output current.
6. The method of claim 5, wherein the power switching transistors S 7 and S 8 are commonly turned on in a zero vector state, in a large vector state when both power switches S 7 and S 8 are turned off, and in a small vector state when both power switching transistors S 7 and S 8 are turned on and off.
7. The specific tuning method for the width modulation ratio of the two-stage five-level current source inverter according to claim 6, wherein in S4, the driving pulse of the power switching transistor S 1～S6 needs to satisfy the following conditions: taking (0, 2 pi) as a period, the power switch tube S 1 is kept on at (pi/3, 2 pi/3), and the driving pulses of the power switch tube S 1～S6 are sequentially different by pi/3; the drive pulse period of the power switching transistors S 7 and S 8 is pi/3.
8. The specific detuning modulation method for a two-stage five-level current source inverter according to claim 7, wherein in S5, the expression of the post-fourier-decomposition output current i (ωt) is:
the n-th harmonic expression of the output current is:
the modulation ratio m satisfies the following formula:
Wherein, I a,1 is fundamental wave amplitude, and I dc is direct current side current.
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