CN117370255A - Error reporting structure of multi-port PCIe bridging chip - Google Patents
Error reporting structure of multi-port PCIe bridging chip Download PDFInfo
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- CN117370255A CN117370255A CN202311334869.5A CN202311334869A CN117370255A CN 117370255 A CN117370255 A CN 117370255A CN 202311334869 A CN202311334869 A CN 202311334869A CN 117370255 A CN117370255 A CN 117370255A
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- 238000011144 upstream manufacturing Methods 0.000 claims abstract description 31
- 239000000872 buffer Substances 0.000 claims abstract description 5
- 238000012545 processing Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The invention discloses a multi-port PCIe bridging chip error reporting architecture, and belongs to the field of integrated circuits. The invention can buffer PCIe errors detected by the downstream ports of the PCIe virtual switches, generate error report requests and corresponding error information according to the buffer information, report the error information received by the downstream ports of the PCIe virtual switches to the RC through the upstream ports of the corresponding PCIe virtual switches, or route and forward the error information received by the downstream ports of the PCIe virtual switches to the upstream ports of the corresponding PCIe virtual switches, and report the error information to the RC through the upstream ports of the corresponding PCIe virtual switches, thereby being convenient for the RC to locate, analyze and correct the errors in time, avoiding the problem of downtime of the system caused by the errors, enhancing the robustness and reliability of the system and being applicable to realizing the error report function of the multi-port PCIe bridge chip.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a multi-port PCIe bridging chip error reporting architecture.
Background
PCI-Express is a high-speed serial computer expansion bus standard, and is widely applied to hardware devices such as display cards, network adapters, storage and the like of computers due to the characteristics of high data transmission rate, high bandwidth, high data transmission reliability, data integrity, high compatibility and support of parallel data channels. PCIe Switch (Switch) is one of the most common device types in PCIe, which can divide a PCIe bus into multiple sub-buses having 1 upstream port and 2 or more downstream ports, and can transfer data from one endpoint device to another endpoint device while controlling the flow direction and speed of the data. The PCIe Switch chip can expand the number of PCIe channels in the system when the number of PCIe channels provided by the CPU is insufficient, and expansion capacity and flexibility are improved.
Some errors occur during PCIe transmissions, which can be broadly classified as correctable errors and uncorrectable errors, which in turn can be classified as fatal and non-fatal errors. Where correctable errors are automatically recognized by hardware and automatically corrected or recovered. Non-fatal errors can cause a particular transmission to become unreliable, but other functions of the link and hardware are not affected. While fatal errors can cause link and hardware anomalies, recovery can only be achieved by a system reset operation. If the errors are not solved in time, a large number of errors can cause system downtime, and the PCIe transmission is greatly influenced.
The multi-port PCIe bridge chip includes a plurality of PCIe Switch controllers, and the multi-port PCIe bridge chip further includes a Virtual Switch (Virtual Switch) mode, where the Virtual Switch mode has a plurality of PCIe Switch (Switch) upstream ports, and communications between the upstream ports and the downstream ports have a plurality of communications changes, which may further complicate the case of PCIe errors. Therefore, aiming at the problem of performing centralized reporting on PCIe errors received or detected by each port in the multi-port PCIe bridge chip, an error reporting design is required to be specially provided to realize the error reporting function of the whole PCIe bridge chip.
Disclosure of Invention
The invention aims to provide a multi-port PCIe bridging chip Error reporting architecture, which aims to solve the problem that PCIE Error received or detected by a plurality of downstream ports of PCIE Switch cannot be reported to RC (Root Complex) in the prior art.
In order to solve the technical problems, the invention provides an error reporting structure of a multi-port PCIe bridge chip, which comprises an error reporting interface module, an error reporting bus module and an error reporting module, wherein:
the error reporting interface module is connected with the upstream port and the downstream port of the PCIe virtual switch in the multi-port PCIe bridge chip, and performs cross-clock and cache processing on signals received from the downstream ports of the PCIE switches;
the error reporting bus module is connected with the error reporting interface module, and the error reporting module is connected with the error reporting bus module.
In one embodiment, the error reporting interface module is connected to downstream ports of a plurality of PCIe switches, and supports error reporting of the plurality of PCIe virtual switches in a virtual switch mode.
In one embodiment, the error reporting interface module caches the error information received by the downstream port of the PCIe virtual switch connected with the error reporting interface module, the detected PCIe errors with different levels, and the port information into the Ingress FIFO of the error reporting interface module, and simultaneously sends an error reporting request and the error information from the Ingress FIFO of the error reporting interface module to the upstream port of the corresponding PCIe virtual switch;
and the error reporting interface module performs cross-clock processing at the same time, so that the clock domain of the downstream port of the PCIe virtual switch is synchronized to the clock domain of the corresponding upstream port after signal processing.
In one embodiment, the error reporting bus module outputs error information and error detection prompt signals of different levels of the downstream port of the PCIe virtual switch stored in the Ingress FIFO to the error reporting module for processing, and stores the error information output by the error reporting module into the Ingress FIFO at the same time, so as to achieve the purpose of managing port data path interconnection of the PCIe virtual switch.
In one embodiment, the error reporting module converts the error information and PCIe error signal stored in the Ingress FIFO and routes the error information and PCIe error signal to generate a corresponding error information and an error reporting request, and then arbitrates and back-pressure processes the error reporting request, and sends the error reporting request to the error reporting bus module.
In one embodiment, corresponding error information and error reporting requests are generated from PCIe errors detected by a downstream port of the PCIe virtual switch according to port configuration information and PCIe error types, and the requests are sent to the error reporting bus module, or the error information received by the downstream port is directly routed to the error reporting bus module.
In one embodiment, the method arbitrates multiple error reporting requests according to the non-full signal of the Egress FIFO, and simultaneously performs back pressure according to the feedback signal of the upstream port of the PCIe virtual switch, caches subsequent error reporting requests before receiving the feedback signal of the upstream port, and reads and sends subsequent error reporting requests after receiving the feedback signal of the upstream port.
The multi-port PCIe bridging chip error reporting architecture provided by the invention can buffer PCIe errors detected by the downstream ports of a plurality of PCIe virtual switches, generate error reporting requests and corresponding error information according to the buffer information, report the error information received by the downstream ports of the PCIe virtual switches to the RC through the upstream ports of the corresponding PCIe virtual switches, or forward the error information received by the downstream ports of the PCIe virtual switches to the upstream ports of the corresponding PCIe virtual switches, and report the error information to the RC through the upstream ports of the corresponding PCIe virtual switches, thereby facilitating the RC to position, analyze and correct the errors in time, avoiding the problem of system downtime caused by the errors, enhancing the robustness and the reliability of the system, and being capable of realizing the error reporting function of the multi-port PCIe bridging chip.
Drawings
Fig. 1 is a schematic diagram of an overall framework of a multi-port PCIE bridge chip error reporting architecture provided by the present invention;
FIG. 2 is a schematic diagram of a design architecture of an error reporting module according to the present invention;
fig. 3 is a schematic diagram of a multi-port PCIE bridge chip error reporting procedure provided by the present invention.
Detailed Description
The following describes the error reporting architecture of the multi-port PCIe bridge chip according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a schematic diagram of an overall framework of an error reporting architecture of a multi-port PCIE bridge chip provided by the present invention, which mainly includes an error reporting interface module, an error reporting bus module and an error reporting module, where the error reporting interface module is connected to upstream and downstream ports of PCIE Virtual Switch (virtual switches) in the multi-port PCIE bridge chip, and performs cross-clock and cache processing on signals received from a plurality of PCIE Virtual Switch downstream ports, where the purpose of the cross-clock processing is to prevent PCIE Virtual Switch clock frequencies of the upstream and downstream ports from being different, so that signals received from the downstream ports need to be synchronized from a downstream port clock domain to a clock domain of an upstream port that needs to be reported, and error message is conveniently reported to an RC through the upstream port. The logic of the cache processing is that a write enable signal and an input signal of the input FIFO are generated according to port information, error messages of different levels received by PCIE downstream ports, PCIE errors of different levels detected and non-empty signals of the asynchronous FIFO, then a read enable signal of the input FIFO is generated according to the non-empty signals of the asynchronous FIFO, and the Error messages in the input FIFO are sent to upstream ports.
The reading control logic of the Ingress FIFO in the error reporting bus module generates a reading enabling signal of the Ingress FIFO according to a non-empty signal of the asynchronous FIFO, and sends a signal cached in the Ingress FIFO to the error reporting module for processing. The Engress FIFO write control logic generates a write enable signal of the Engress FIFO according to the arbitration result in the error reporting module, and writes the signal processed by the error reporting module into the Engress FIFO.
The error reporting module mainly converts and arbitrates PCIE error information read from the entry FIFO and then writes the PCIE error information into the entry FIFO.
Fig. 2 is a schematic diagram of a design architecture of an Error reporting module in a multi-port PCIE bridge chip, where the Error reporting module generates a corresponding Error Message and an Error reporting request according to a port configuration signal and a PCIE Error type, where the Error reporting module generates the Error reporting request corresponding to an Error detected by a downstream port PCIE Virtual Switch, or generates the Error reporting request corresponding to an Error Message received by the downstream port, and at the same time, the Error reporting module arbitrates a plurality of Error reporting requests, determines a source and an destination of the Error Message in a Virtual Switch mode according to an upstream port configuration signal, and sends the Error reporting request to an Error reporting bus module through an Error reporting submodule corresponding to VS (Virtual Switch). And simultaneously, back pressure is carried out according to the feedback signal of the upstream port PCIE Virtual Switch, the subsequent Error Message request is buffered before the feedback signal of the upstream port is received, and the subsequent Error Message request is read and sent after the feedback signal of the upstream port is received.
Fig. 3 is a schematic diagram of a multi-port PCIE bridge chip error reporting flow according to the present invention, which mainly includes a PCIE upstream and downstream port detection or a PCIE error processing and reporting flow received.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (7)
1. The multi-port PCIe bridging chip error reporting architecture is characterized by comprising an error reporting interface module, an error reporting bus module and an error reporting module, wherein:
the error reporting interface module is connected with the upstream port and the downstream port of the PCIe virtual switch in the multi-port PCIe bridge chip, and performs cross-clock and cache processing on signals received from the downstream ports of the PCIE switches;
the error reporting bus module is connected with the error reporting interface module, and the error reporting module is connected with the error reporting bus module.
2. The multi-port PCIe bridge chip error reporting architecture of claim 1 wherein the error reporting interface module is connected to downstream ports of a plurality of PCIe switches and supports error reporting of a plurality of PCIe virtual switches in virtual switch mode.
3. The multi-port PCIe bridge chip error reporting architecture of claim 1 wherein the error reporting interface module buffers error information received by a downstream port of a PCIe virtual switch connected thereto, detected PCIe errors of different levels, and port information into an Ingress FIFO of the error reporting interface module, and simultaneously sends an error reporting request and error information from an Ingress FIFO of the error reporting interface module to an upstream port of a corresponding PCIe virtual switch;
and the error reporting interface module performs cross-clock processing at the same time, so that the clock domain of the downstream port of the PCIe virtual switch is synchronized to the clock domain of the corresponding upstream port after signal processing.
4. The multi-port PCIe bridge chip error reporting architecture of claim 3 wherein said error reporting bus module outputs different levels of error information and error detection hint signals of a PCIe virtual switch downstream port stored in said Ingress FIFO to said error reporting module for processing, and simultaneously stores said error information output by said error reporting module into said Egress FIFO for managing port data path interconnections of a PCIe virtual switch.
5. The multi-port PCIe bridge chip error reporting architecture of claim 4 wherein said error reporting module converts and routes error information and PCIe error signals stored in said Ingress FIFO to generate corresponding error information and error reporting requests, arbitrates and back-pressure processes said error reporting requests, and sends said error reporting requests to said error reporting bus module.
6. The multi-port PCIe bridge chip error reporting architecture of claim 5 wherein PCIe errors detected by a downstream port of a PCIe virtual switch are generated into corresponding error information and error reporting requests according to port configuration information and PCIe error types, and the requests are sent to the error reporting bus module or error information received by a downstream port is directly routed to the error reporting bus module.
7. The multi-port PCIe bridge chip error reporting architecture of claim 6 wherein a plurality of error reporting requests are arbitrated according to a non-full signal of the Egress FIFO, and back-pressure is performed according to a feedback signal of an upstream port of a PCIe virtual switch, a subsequent error reporting request is buffered before the feedback signal of the upstream port is received, and the subsequent error reporting request is read and sent after the feedback signal of the upstream port is received.
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| CN202311334869.5A CN117370255A (en) | 2023-10-16 | 2023-10-16 | Error reporting structure of multi-port PCIe bridging chip |
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| CN202311334869.5A CN117370255A (en) | 2023-10-16 | 2023-10-16 | Error reporting structure of multi-port PCIe bridging chip |
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