CN117370252A - Signal processing method, signal processing device, electronic equipment and computer readable storage medium - Google Patents
Signal processing method, signal processing device, electronic equipment and computer readable storage medium Download PDFInfo
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Abstract
The application provides a signal processing method, a signal processing device, electronic equipment and a computer readable storage medium; the method comprises the following steps: obtaining a first signal and/or a second signal based on a network controller sideband interface NCSI protocol, wherein the first signal is a signal generated by a baseboard management controller BMC, and the second signal is a signal generated by a network card end; the first signal is time-sequence compensated and/or the second signal is delay compensated based on a first reference clock signal of the NCSI protocol.
Description
Technical Field
The present disclosure relates to computer technology, and in particular, to a signal processing method, apparatus, electronic device, and computer readable storage medium.
Background
The server can realize information transmission between the baseboard management controller (BMC, baseboard Management Controller) chip and the Ethernet controller through the network controller sideband interface (NCSI, network Controller Sideband Interface) bus, but the problems of signal delay, signal attenuation and the like can occur to NCSI signals after long-distance transmission by using cables due to the fact that the distance between the BMC chip and the Ethernet controller is far in the use process.
In the current scheme design, for NCSI signal transmission, remote transmission is realized by using a scheme with better plates and improved cable materials. However, the scheme can only meet the requirement of improving the signal quality in the case of short-distance transmission, and cannot solve the problems of signal delay, signal attenuation and the like in the case of long-distance transmission.
Disclosure of Invention
Embodiments of the present application provide a signal processing method, apparatus, electronic device, and computer readable storage medium, capable of eliminating signal delay and signal attenuation of NCSI signals transmitted through a cable.
The technical scheme of the embodiment of the application is realized as follows:
the embodiment of the application provides a signal processing method, which comprises the following steps:
obtaining a first signal and/or a second signal based on a network controller sideband interface NCSI protocol, wherein the first signal is a signal generated by a baseboard management controller BMC, and the second signal is a signal generated by a network card end;
the first signal is time-sequence compensated and/or the second signal is delay compensated based on a first reference clock signal of the NCSI protocol.
In the above scheme, the method further comprises:
the first signal after the time sequence compensation is sent to a network card end;
the received first signal is subjected to quality processing through the network card end;
and/or the number of the groups of groups,
generating the second signal through the network card end;
the second signal is sent after being subjected to quality processing;
wherein the quality treatment comprises at least one of the following: signal filtering, adjusting signal duty cycle, eliminating signal overshoot and/or undershoot errors, adjusting rise and/or fall time of the signal.
In the above aspect, after the time sequence compensation is performed on the first signal, the method further includes:
the first signal after the time sequence compensation is sent to a network card end;
and performing delay compensation on the received first signal based on the second reference clock signal of the NCSI protocol through the network card end, wherein the first reference clock signal is synchronous with the phase of the second reference clock signal.
In the above solution, the performing timing compensation on the first signal based on the first reference clock signal of the NCSI protocol includes:
determining a first phase error of the first signal transmission process;
the first signal is time-sequence compensated based on the first reference clock signal and the first phase error.
In the above solution, the delay compensation for the second signal based on the first reference clock signal of the NCSI protocol includes:
determining a second phase error of the second signal transmission process;
the second signal is delay compensated based on the first reference clock signal and the second phase error.
An embodiment of the present application provides a signal processing apparatus, including:
the acquisition module is used for acquiring a first signal and/or a second signal based on a network controller sideband interface NCSI protocol, wherein the first signal is a signal generated by a baseboard management controller BMC, and the second signal is a signal generated by a network card end;
and the signal processing module is used for carrying out time sequence compensation on the first signal and/or carrying out delay compensation on the second signal based on the first reference clock signal of the NCSI protocol.
An embodiment of the present application provides a signal processing apparatus, including: the system comprises a main board end and a network card end which are connected through a cable, wherein the main board end comprises a baseboard management controller BMC and a first signal processing unit, and the first signal processing unit is connected with the BMC through a first interface; wherein,
the BMC is used for generating a first signal based on a network controller sideband interface NCSI protocol;
the network card end is used for generating a second signal based on NCSI protocol;
the first signal processing unit is configured to obtain a first signal and/or a second signal, and perform timing compensation on the first signal and/or perform delay compensation on the second signal based on a first reference clock signal of the NCSI protocol.
In the above aspect, the first signal processing unit is further configured to: and sending the first signal after time sequence compensation to the network card end and/or sending the second signal after delay compensation to the BMC.
In the above scheme, the network card end comprises a network card and a second signal processing unit, and the second signal processing unit is connected with the network card through a second interface; wherein,
the network card is used for generating the second signal;
the second signal processing unit is used for receiving the first signal subjected to time sequence compensation, sending the received first signal to the network card after quality processing, and/or sending the second signal generated by the network card to the first signal processing unit after quality processing;
wherein the quality treatment comprises at least one of the following: signal filtering, adjusting signal duty cycle, eliminating signal overshoot and/or undershoot errors, adjusting rise and/or fall time of the signal.
An embodiment of the present application provides an electronic device, including:
a memory for storing executable instructions;
and the processor is used for realizing the signal processing method provided by the embodiment of the application when executing the executable instructions stored in the memory.
The embodiment of the application provides a computer readable storage medium, which stores executable instructions for implementing the signal processing method provided by the embodiment of the application when the executable instructions are executed by a processor.
According to the embodiment of the application, the first signal and/or the second signal based on the NCSI protocol of the sideband interface of the network controller are obtained, the first signal is the signal generated by the BMC, the second signal is the signal generated by the network card end, the first signal is subjected to time sequence compensation and/or the second signal is subjected to delay compensation based on the first reference clock signal of the NCSI protocol, and the first signal and/or the second signal transmitted from two ends are subjected to corresponding compensation based on the first reference clock signal, so that the phases of the signals at two ends are kept synchronous, and the signal delay and the signal attenuation of the NCSI signal transmitted through a cable are eliminated.
Drawings
Fig. 1 is a schematic diagram of an alternative configuration of a signal processing apparatus 100 provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of an alternative architecture of an electronic device 200 provided in an embodiment of the present application;
FIG. 3 is a schematic flow chart of an alternative signal processing method according to an embodiment of the present application;
fig. 4 is a schematic diagram of an alternative structure of a signal processing apparatus 400 according to an embodiment of the present application;
fig. 5 is a schematic diagram of an alternative structure of a signal processing unit according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings, and the described embodiments should not be construed as limiting the present application, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
In the following description, the terms "first", "second", "third" and the like are merely used to distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first", "second", "third" may be interchanged with a specific order or sequence, as permitted, to enable embodiments of the application described herein to be practiced otherwise than as illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.
Before further describing embodiments of the present application in detail, the terms and expressions that are referred to in the embodiments of the present application are described, and are suitable for the following explanation.
1) The baseboard management controller (BMC, baseboard Management Controller) is a dedicated controller for monitoring and managing servers.
2) The network controller sideband interface (NCS, networking Controller Sideband Interface) is an industry standard for sideband interface network controllers for supporting server out-of-band management defined by the international organization for standardization Distributed Management Task Force (DMTF). In short, NCSI is a protocol defined by the communication between the BMC of the host and the network card.
Embodiments of the present application provide a signal processing method, apparatus, electronic device, and computer readable storage medium, capable of eliminating signal delay and signal attenuation of NCSI signals transmitted through a cable.
First, referring to fig. 1, fig. 1 is an optional schematic structural diagram of a signal processing apparatus 100 provided in an embodiment of the present application, where the signal processing apparatus 100 includes a main board end 101 and a network card end 102 connected by a cable (cable). The main board terminal 101 includes a baseboard management controller BMC1011 and a first signal processing unit 1012, where the first signal processing unit 1012 is connected to the BMC1011 through a first interface 1013. The first interface 1013 may be implemented by an open core protocol slot (OCP slot, open Core Protoco slot). The first signal processing unit 1012 may be a Driver chip or a programmable logic editor (FPGA, field Programmable Gate Array). The length of the cable between the main board end 101 and the network card end 102 can be determined according to the actual scene, and the cable can be used for realizing long-distance transmission of NCSI signals between the main board end and the network card end.
Next, referring to fig. 2, fig. 2 is an optional schematic structural diagram of an electronic device 200 provided in the embodiment of the present application, where in practical application, the electronic device 200 may be implemented as the signal processing device 100, the motherboard 101, or the first signal processing unit 1012 in fig. 1. The electronic device 200 shown in fig. 2 includes: at least one processor 201 and a memory 202. The various components in the electronic device 200 are coupled together by a bus system 203. It is understood that the bus system 203 is used to enable connected communications between these components. The bus system 203 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration the various buses are labeled as bus system 203 in fig. 2.
The processor 201 may be an integrated circuit chip with signal processing capabilities such as a general purpose processor, which may be a microprocessor or any conventional processor, or the like, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like.
The memory 202 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid state memory, hard drives, optical drives, and the like. Memory 202 optionally includes one or more storage devices physically remote from processor 201.
Memory 202 includes volatile memory or nonvolatile memory, and may also include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), and the volatile Memory may be a random access Memory (RAM, random Access Memory). The memory 202 described in the embodiments herein is intended to comprise any suitable type of memory.
In some embodiments, the memory 202 is capable of storing data to support various operations, examples of which include programs, modules and data structures, or subsets or supersets thereof, in which embodiments the memory 202 stores an operating system 2021 and an information-configuration means 2022 for storing communication devices based on a multi-configuration; in particular, the method comprises the steps of,
an operating system 2021, including system programs for handling various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and handling hardware-based tasks;
in some embodiments, the information configuration apparatus based on a multiple configuration storage communication device provided in the embodiments of the present application may be implemented in a software manner, and fig. 2 shows the information configuration apparatus 2022 based on a multiple configuration storage communication device stored in the memory 202, which may be software in the form of a program and a plug-in, and includes the following software modules: the obtaining module 20221 and the signal processing module 20222 are logical, and thus may be arbitrarily combined or further split according to the implemented functions. The functions of the respective modules will be described hereinafter.
In other embodiments, the information configuration apparatus based on a multi-configuration storage communication device provided in the embodiments of the present application may be implemented in hardware, and as an example, the information configuration apparatus based on a multi-configuration storage communication device provided in the embodiments of the present application may be a processor in the form of a hardware decoding processor that is programmed to perform the information configuration method based on a multi-configuration storage communication device provided in the embodiments of the present application, for example, the processor in the form of a hardware decoding processor may employ one or more application specific integrated circuits (ASIC, application Specific Integrated Circuit), DSPs, programmable logic devices (PLD, programmable Logic Device), complex programmable logic devices (CPLD, complex Programmable Logic Device), field programmable gate arrays (FPGA, field-Programmable Gate Array), or other electronic components.
The signal processing method provided by the embodiment of the present application will be described below in connection with exemplary applications and implementations of the electronic device provided by the embodiment of the present application.
Referring to fig. 3, fig. 3 is a schematic flowchart of an alternative signal processing method according to an embodiment of the present application, and will be described with reference to the steps shown in fig. 3.
Step 301, obtaining a first signal and/or a second signal based on a sideband interface NCSI protocol of a network controller, wherein the first signal is a signal generated by a baseboard management controller BMC, and the second signal is a signal generated by a network card end;
step 302, performing timing compensation on the first signal and/or performing delay compensation on the second signal based on a first reference clock signal of the NCSI protocol.
The first signal is a signal generated by the BMC and used for being sent to the network card end, and the second signal is a signal generated by the network card end and sent to the main board end. In actual implementation, if the BMC generates the first signal, the first signal is transmitted to the first signal processing unit through the first interface. And the second signal generated by the network card end is transmitted to the main board end through the cable and is received by the first signal processing unit.
In practical implementation, after the first signal processing unit obtains the first signal and/or the second signal based on the NCSI protocol, timing compensation is performed on the first signal and/or delay compensation is performed on the second signal based on the first reference clock signal. Here, the first reference clock signal is a clock signal based on the NCSI protocol, which meets the specification requirements of the NCSI protocol for signals. For example, the signal frequency of the first reference clock signal may be 50MHz. The first signal processing unit performs time sequence compensation on the first signal according to the first reference clock signal and then sends the first signal to the network card end through the cable, so that the phase of the first signal can be kept synchronous with the phase of the first reference clock signal, and the first signal can be kept within the specification conforming to the NCSI protocol.
According to the embodiment of the application, the first signal and/or the second signal based on the NCSI protocol of the sideband interface of the network controller are obtained, the first signal is the signal generated by the BMC, the second signal is the signal generated by the network card end, the first signal is subjected to time sequence compensation and/or the second signal is subjected to delay compensation based on the first reference clock signal of the NCSI protocol, and the first signal and/or the second signal transmitted from two ends are subjected to corresponding compensation based on the first reference clock signal, so that the phases of the signals at two ends are kept synchronous, and the signal delay and the signal attenuation of the NCSI signal transmitted through a cable are eliminated.
In some embodiments, after the timing compensation of the first signal, the method further comprises: the first signal after the time sequence compensation is sent to a network card end; and performing delay compensation on the received first signal based on the second reference clock signal of the NCSI protocol through the network card end, wherein the first reference clock signal is synchronous with the phase of the second reference clock signal.
In practical implementation, after the main board end obtains the first signal after the time sequence compensation, the first signal after the time sequence compensation is sent to the network card end, and after the network card end receives the first signal, the network card end also carries out delay compensation on the first signal based on the second reference clock signal of the NCSI protocol. Here, the delay compensation is used for eliminating delay errors generated in the process of transmitting the first signal through the cable, so that the phase of the first signal at the network card end is synchronous with the second reference clock signal. Here, the phase of the second reference clock signal is synchronous with the phase of the first reference clock signal, it can be understood that the first signal in the embodiment of the present application arrives at the network card end through cable transmission, and after being processed by the second signal processing unit of the network card end, is synchronous with the phase of the second signal at the motherboard end, that is, the phase of the second signal received by the network card is synchronous with the phase of the signal at the motherboard end. By respectively carrying out the time sequence compensation and the delay compensation of the phase at the main board end and the network card end, the first signal can keep more accurate synchronization at the two ends.
In some embodiments, the method further comprises: the first signal after the time sequence compensation is sent to a network card end; the received first signal is subjected to quality processing through the network card end; and/or generating the second signal through the network card end; the second signal is sent after being subjected to quality processing; wherein the quality treatment comprises at least one of the following: signal filtering, adjusting signal duty cycle, eliminating signal overshoot and/or undershoot errors, adjusting rise and/or fall time of the signal.
In actual implementation, after generating the first signal and performing time sequence compensation on the first signal, the main board end sends the first signal to the network card end through a cable. The network card end receives the first signal subjected to time sequence compensation, and then carries out quality processing on the received first signal. And if the network card end generates the second signal, the network card end performs quality processing on the second signal and then sends the second signal to the main board end.
In some embodiments, the timing compensation of the first signal based on the first reference clock signal of the NCSI protocol comprises: determining a first phase error of the first signal transmission process; the first signal is time-sequence compensated based on the first reference clock signal and the first phase error.
In practical implementation, when the first signal processing unit performs timing compensation on the first signal, the first signal may perform timing compensation on the first signal according to the estimated first phase error in the first signal transmission process. Here, the first phase error includes an error generated in the process of transmitting the first signal to the network card terminal. The estimation of the first phase error can be determined according to the length of the cable and the phase attenuation rule in the transmission process. The phase decay law can be derived based on a number of experiments. The first signal is subjected to time sequence compensation at the main board end so as to eliminate a first phase error generated in the process of transmitting the first signal to the network card end, so that the first signal can have a smaller phase error after reaching the network card end, and the first signal can keep relatively synchronous phases at the two ends.
In some embodiments, the delay compensating the second signal based on the first reference clock signal of the NCSI protocol comprises: determining a second phase error of the second signal transmission process; the second signal is delay compensated based on the first reference clock signal and the second phase error.
In some embodiments, the delay compensation of the second signal is performed by the first signal processing unit determining a second phase error of the second signal during transmission. Here, the second phase error may be determined based on the first reference clock signal, and since the first reference clock signal is synchronized with the second reference clock signal, the second phase error generated during transmission of the second signal may be determined to delay-compensate the second signal so as to be clock-synchronized with the first reference signal.
In some embodiments, referring to fig. 4, fig. 4 is an alternative structural schematic diagram of a signal processing apparatus 400 provided in an embodiment of the present application. Here, the network card 102 includes a network card 1021 and a second signal processing unit 1022, and the second signal processing unit 1022 is connected to the network card 1021 through a second interface 1023.
The second interface 1023 may be implemented by an open core protocol slot (OCP slot, open Core Protoco1 slot). The second signal processing unit 1022 may be a Driver chip, or may be a programmable logic editor (FPGA, field Programmable Gate Array). The first signal processing unit 1012 and the second signal processing unit 1022 shown in fig. 4 are each FPGAs.
In practical implementation, the first signal of the motherboard 101 is time-sequence compensated by the first signal processing unit 1012 of the motherboard 101 and then sent to the second signal processing unit 1022 of the network card 102 through the cable. The second signal processing unit 1022 performs quality processing on the received first signal, and then transmits the processed first signal to the network card 1021 through the second interface 1023. The second signal generated by the network card 1021 may be transmitted to the second processing unit 1022 through the second interface 1023, the second processing unit 1022 performs quality processing on the second signal, and then transmits the second signal to the first signal processing unit 1012 of the motherboard terminal 101 through the cable, and the first signal processing unit 1012 performs quality processing on the received second signal and then transmits the second signal to the BMC1011 through the first interface 1013.
In an actual scenario, the first signal may be a signal carrying state information of the BMC, where the state information includes working state information and configuration state information of the system. The main board end sends the first signal to the network card end, so that the network card end can obtain the running state of the main board end. The second signal may be an instruction signal, for example, a system update instruction, a start/stop instruction, or the like. The network card end can control the operation of the main board end by sending a second signal to the main board end.
In actual practice, the quality treatment includes at least one of the following: signal filtering, adjusting signal duty cycle, eliminating signal overshoot and/or undershoot errors, adjusting rise and/or fall time of the signal. The quality of the signal can be adjusted by the quality processing. Illustratively, after quality processing, the signal can be ensured to be a single-ended signal, kept at a 3.3V signal, kept at a signal frequency of 50MHz, adjusted to rise/fall time, avoid overshoot/undershoot, and adjusted to duty cycle, etc., so that all aspects of the signal conform to the NCSI specifications of Driver/FPGA and OCP slots.
In some embodiments, referring to fig. 5, fig. 5 is an optional structural schematic diagram of a signal processing unit provided in an embodiment of the present application. Here, the signal processing unit may be the first signal processing unit or the second signal processing unit. The signal processing unit includes a phase locked loop (PLL, phase Locked Loop) module 501, a transmit signal input output (TX FIFO) module 502, and a receive signal input output (RX FIFO) module 503. Here, taking the first signal processing unit at the motherboard end as an example, the transmit signal input/output (TX FIFO) module 502 is configured to receive the first signal NCSI TX generated by the BMC at the motherboard end, and transmit the first signal NCSI TX to the network card end, and the receive signal input/output (RX FIFO) module is configured to receive the second signal NCSI RX transmitted by the network card end, and transmit the second signal NCSI RX to the BMC. In this embodiment, the first reference clock signal NCSI CLK is input to the PLL module 501, and the PLL module 501 performs timing compensation and delay compensation on the first signal NCSI TX and the second signal NCSI RX, respectively. It should be noted that, after the TX FIFO module 502 obtains the first signal generated by the BMC, the first signal is compensated in time sequence by the PLL and then sent to the network card terminal, and after the second signal is received, the second signal is compensated in delay by the PLL and then sent to the BMC. The signal processing unit can perform time sequence compensation and delay compensation on the signals, so that the received signals and the transmitted signals can be more accurately kept in phase synchronization with the other end.
Continuing with the description below of an exemplary architecture of the signal processing device 2055 implemented as a software module provided in embodiments of the present application, in some embodiments, as shown in fig. 2, the software modules stored in the signal processing device 2055 of the memory 205 may include:
the obtaining module 20551 is configured to obtain a first signal and/or a second signal based on an NCSI protocol of a sideband interface of the network controller, where the first signal is a signal generated by a baseboard management controller BMC, and the second signal is a signal generated by a network card end;
a signal processing module 20552 for timing compensating the first signal and/or delay compensating the second signal based on the first reference clock signal of the NCSI protocol.
In some embodiments, the apparatus further comprises: the quality processing module is used for sending the first signal subjected to the time sequence compensation to the network card end; the received first signal is subjected to quality processing through the network card end; and/or generating the second signal through the network card end; the second signal is sent after being subjected to quality processing; wherein the quality treatment comprises at least one of the following: signal filtering, adjusting signal duty cycle, eliminating signal overshoot and/or undershoot errors, adjusting rise and/or fall time of the signal.
In some embodiments, after the timing compensation of the first signal, the apparatus further comprises: the sending module is used for sending the first signal subjected to the time sequence compensation to the network card end; and performing delay compensation on the received first signal based on the second reference clock signal of the NCSI protocol through the network card end, wherein the first reference clock signal is synchronous with the phase of the second reference clock signal.
In some embodiments, the signal processing module 20552 is further configured to determine a first phase error of the first signal transmission process; the first signal is time-sequence compensated based on the first reference clock signal and the first phase error.
In some embodiments, the signal processing module 20552 is further configured to determine a second phase error of the second signal transmission process; the second signal is delay compensated based on the first reference clock signal and the second phase error.
It should be noted that, the description of the apparatus in the embodiment of the present application is similar to the description of the embodiment of the method described above, and has similar beneficial effects as the embodiment of the method, so that a detailed description is omitted.
The embodiment of the application provides a signal processing device, referring to fig. 1, a signal processing device 100 includes a main board end 101 and a network card end 102 connected by a cable. The main board terminal 101 includes a baseboard management controller BMC1011 and a first signal processing unit 1012, where the first signal processing unit 1012 is connected to the BMC1011 through a first interface 1013. Wherein, the BMC1011 is configured to generate a first signal based on a network controller sideband interface NCSI protocol; the network card end 102 is configured to generate a second signal based on an NCSI protocol; the first signal processing unit 1022 is configured to obtain a first signal and/or a second signal, and perform timing compensation on the first signal and/or perform delay compensation on the second signal based on a first reference clock signal of the NCSI protocol.
In some embodiments, the first signal processing unit 1022 is further configured to: and sending the first signal after time sequence compensation to the network card end and/or sending the second signal after delay compensation to the BMC.
In some embodiments, referring to fig. 4, the network card end 102 includes a network card 1021 and a second signal processing unit 1022, where the second signal processing unit 1022 is connected to the network card 1021 through a second interface 1023; wherein, the network card 1021 is configured to generate the second signal; the second signal processing unit 1022 is configured to receive the first signal after the timing compensation, perform quality processing on the received first signal, and send the first signal to the network card 1021, and/or perform quality processing on the second signal generated by the network card 1021, and send the second signal to the first signal processing unit 1012; wherein the quality treatment comprises at least one of the following: signal filtering, adjusting signal duty cycle, eliminating signal overshoot and/or undershoot errors, adjusting rise and/or fall time of the signal.
It should be noted that, the description of the apparatus in the embodiment of the present application is similar to the description of the embodiment of the method described above, and has similar beneficial effects as the embodiment of the method, so that a detailed description is omitted.
Embodiments of the present application provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the signal processing method according to the embodiment of the present application.
The present embodiments provide a computer readable storage medium storing executable instructions, wherein the executable instructions are stored, which when executed by a processor, cause the processor to perform the signal processing method provided by the embodiments of the present application.
In some embodiments, the computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; but may be a variety of devices including one or any combination of the above memories.
In some embodiments, the executable instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.
As an example, the executable instructions may, but need not, correspond to files in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a hypertext markup language (HTML, hyper Text Markup Language) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).
As an example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or, alternatively, distributed across multiple sites and interconnected by a communication network.
In summary, by the embodiments of the present application, signal delay and signal attenuation of the NCSI signal transmitted through the cable can be eliminated.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application. Any modifications, equivalent substitutions, improvements, etc. that are within the spirit and scope of the present application are intended to be included within the scope of the present application.
Claims (10)
1. A signal processing method, comprising:
obtaining a first signal and/or a second signal based on a network controller sideband interface NCSI protocol, wherein the first signal is a signal generated by a baseboard management controller BMC, and the second signal is a signal generated by a network card end;
the first signal is time-sequence compensated and/or the second signal is delay compensated based on a first reference clock signal of the NCSI protocol.
2. The signal processing method of claim 1, the method further comprising:
the first signal after the time sequence compensation is sent to a network card end;
the received first signal is subjected to quality processing through the network card end;
and/or the number of the groups of groups,
generating the second signal through the network card end;
the second signal is sent after being subjected to quality processing;
wherein the quality treatment comprises at least one of the following: signal filtering, adjusting signal duty cycle, eliminating signal overshoot and/or undershoot errors, adjusting rise and/or fall time of the signal.
3. The signal processing method of claim 1, the method further comprising, after the timing compensation of the first signal:
the first signal after the time sequence compensation is sent to a network card end;
and performing delay compensation on the received first signal based on the second reference clock signal of the NCSI protocol through the network card end, wherein the first reference clock signal is synchronous with the phase of the second reference clock signal.
4. The signal processing method according to claim 1, the timing compensation of the first signal based on the first reference clock signal of the NCSI protocol, comprising:
determining a first phase error of the first signal transmission process;
the first signal is time-sequence compensated based on the first reference clock signal and the first phase error.
5. The signal processing method of claim 1, the delay compensating the second signal based on the first reference clock signal of the NCSI protocol, comprising:
determining a second phase error of the second signal transmission process;
the second signal is delay compensated based on the first reference clock signal and the second phase error.
6. A signal processing apparatus comprising:
the acquisition module is used for acquiring a first signal and/or a second signal based on a network controller sideband interface NCSI protocol, wherein the first signal is a signal generated by a baseboard management controller BMC, and the second signal is a signal generated by a network card end;
and the signal processing module is used for carrying out time sequence compensation on the first signal and/or carrying out delay compensation on the second signal based on the first reference clock signal of the NCSI protocol.
7. A signal processing apparatus comprising: the system comprises a main board end and a network card end which are connected through a cable, wherein the main board end comprises a baseboard management controller BMC and a first signal processing unit, and the first signal processing unit is connected with the BMC through a first interface; wherein,
the BMC is used for generating a first signal based on a network controller sideband interface NCSI protocol;
the network card end is used for generating a second signal based on NCSI protocol;
the first signal processing unit is configured to obtain a first signal and/or a second signal, and perform timing compensation on the first signal and/or perform delay compensation on the second signal based on a first reference clock signal of the NCSI protocol.
8. The apparatus of claim 7, the first signal processing unit further to: and sending the first signal after time sequence compensation to the network card end and/or sending the second signal after delay compensation to the BMC.
9. The device of claim 7, the network card end comprising a network card and a second signal processing unit, the second signal processing unit being connected to the network card through a second interface; wherein,
the network card is used for generating the second signal;
the second signal processing unit is used for receiving the first signal subjected to time sequence compensation, sending the received first signal to the network card after quality processing, and/or sending the second signal generated by the network card to the first signal processing unit after quality processing;
wherein the quality treatment comprises at least one of the following: signal filtering, adjusting signal duty cycle, eliminating signal overshoot and/or undershoot errors, adjusting rise and/or fall time of the signal.
10. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311125952.1A CN117370252A (en) | 2023-09-01 | 2023-09-01 | Signal processing method, signal processing device, electronic equipment and computer readable storage medium |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311125952.1A CN117370252A (en) | 2023-09-01 | 2023-09-01 | Signal processing method, signal processing device, electronic equipment and computer readable storage medium |
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| CN202311125952.1A Pending CN117370252A (en) | 2023-09-01 | 2023-09-01 | Signal processing method, signal processing device, electronic equipment and computer readable storage medium |
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| CN (1) | CN117370252A (en) |
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