CN117360536A

CN117360536A - Circuit system for protecting vehicle from faults and vehicle

Info

Publication number: CN117360536A
Application number: CN202311468914.6A
Authority: CN
Inventors: 徐松; 朱红; 马皎; 王磊; 张岳冬; 姚广俊; 聂世锐
Original assignee: Jika Intelligent Robot Co ltd
Current assignee: Jika Intelligent Robot Co ltd
Priority date: 2023-11-07
Filing date: 2023-11-07
Publication date: 2024-01-09

Abstract

The present disclosure relates to a circuit system for vehicle fault protection and a vehicle. The circuitry includes: the main control chip comprises a first pin and a second pin; the driving chip comprises an input pin; a first self-locking circuit electrically coupled to the first pin and the input pin; a second latching circuit electrically coupled to the second pin and the input pin, wherein the second latching circuit is electrically coupled to the first pin via a second line, and wherein the first latching circuit is electrically coupled to the second pin via the first line to interlock the first latching circuit and the second latching circuit; a first charge pump circuit electrically coupled to the first latching circuit and adapted to unlock the first latching circuit upon a state switch; and a second charge pump circuit coupled to the second latching circuit and adapted to unlock the second latching circuit upon a state switch. In this way, a single main control unit and discrete components are implemented to build a vehicle fault function circuit, increasing circuit reliability and reducing circuit implementation costs.

Description

Circuit system for protecting vehicle from faults and vehicle

Technical Field

The present disclosure relates generally to the field of circuit technology, and in particular to circuitry for vehicle fault protection and a vehicle.

Background

When the electronic control system of the vehicle breaks down, for example, the main control chip runs off or hardware is damaged, the vehicle still needs to complete basic functions at the moment, so that the vehicle can run at the lowest performance level, safely runs to a nearby maintenance site, avoids serious accidents caused by anchoring the vehicle in the outside, and ensures the safety of the vehicle. This is commonly referred to as a vehicle hill home mode.

In this mode, when the vehicle main control chip fails, some loads need to remember the current control state to continue running, but when the main control chip fails, the hardware state of the chip pins is an uncertain state, possibly high and possibly low, which brings great trouble to design. The current scheme generally adopts two control units (MCUs), one master MCU and one slave MCU, as shown in fig. 1, and the two MCUs perform state interaction in real time and monitor each other. When the main MCU is in fault, the slave MCU detects that the main MCU is in fault, and receives related control before the fault, and enters a limp home mode to realize related functions. But two MCUs are adopted, resulting in high hardware cost and relatively complex software logic.

Accordingly, there is an urgent need for a circuit system for vehicle fault protection to solve the problems existing in the current technology.

Disclosure of Invention

According to example embodiments of the present disclosure, a circuit system for vehicle fault protection and a vehicle are provided to overcome the high cost, high complexity and other technical problems of implementing complex limp home mode functions by dual MCUs.

In a first aspect of the present disclosure, a circuit system for vehicle fault protection is provided. The circuitry includes: the main control chip comprises a first pin and a second pin; a driving chip adapted to drive a vehicle via control of the main control chip and including an input pin; a first self-locking circuit having one end electrically coupled to the first pin and the other end electrically coupled to the input pin; a second latching circuit having one end electrically coupled to the second pin and the other end electrically coupled to the input pin, wherein the second latching circuit is electrically coupled to the first pin via a second line, and wherein the first latching circuit is electrically coupled to the second pin via a first line to interlock the first latching circuit and the second latching circuit; a first charge pump circuit electrically coupled to the first latching circuit and adapted to unlock the first latching circuit upon a state switch; and a second charge pump circuit coupled to the second latching circuit and adapted to unlock the second latching circuit upon a state switch.

In such an embodiment, the high cost and complexity of implementing the complex limp home mode function in the vehicle fault mode by the dual MCUs can be overcome, and a low cost and high robustness vehicle fault protection function circuit is built based on the single MCU and the discrete devices.

In some embodiments, the first self-locking circuit includes a second transistor, a third resistor, a fourth resistor, a fifth resistor, and a third transistor, and wherein: the second triode emitter is coupled to the first charge pump circuit, its base is coupled to the third triode collector via the fourth resistor, and its collector is coupled to the input pin via a third line; and one end of the fifth resistor is coupled to the first pin, the other end of the fifth resistor is coupled to the base electrode of the third triode, the other branch is coupled to the collector electrode of the second triode through the third resistor, and the emitter electrode of the third triode is grounded.

In some embodiments, the second self-locking circuit includes a fifth transistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a sixth transistor, and wherein the eleventh resistor has one end coupled to the second pin, another end coupled to the sixth transistor base via a branch and another branch coupled to the fifth transistor collector via the ninth resistor; the emitter of the fifth triode is coupled to the second charge pump circuit, and the base of the fifth triode is coupled to the collector of the sixth triode through the tenth resistor; and the sixth triode has its emitter grounded and its collector coupled to the input pin via a fourth line.

In some embodiments, the first line is coupled to the second pin by the third triode collector and the second line is coupled to the first pin by the sixth triode collector.

In some embodiments, the first charge pump circuit comprises: the positive electrode of the first diode is coupled with the operating voltage; a second diode connected in series with the first diode; a first triode having a base coupled to the cathode of the second diode, an emitter coupled to an operating voltage and a collector coupled to the emitter of the second triode; a first capacitor having one plate coupled to the second diode anode and another plate coupled to the first pin; and a second capacitor having one plate coupled to the second diode cathode and the other plate grounded.

In some embodiments, the first charge pump circuit further comprises: a first resistor having one end coupled to the cathode of the second diode and the other end grounded; and a second resistor disposed between the first pin and the first capacitor.

In some embodiments, the second charge pump circuit comprises: the positive electrode of the third diode is coupled with the operating voltage; a fourth diode connected in series with the third diode; a fourth triode having a base coupled to the cathode of the fourth diode, an emitter coupled to an operating voltage and a collector coupled to the emitter of the fifth triode; a third capacitor having one plate coupled to the fourth diode anode and another plate coupled to the second pin; and a fourth capacitor having one plate coupled to the fourth diode cathode and the other plate grounded.

In some embodiments, the second charge pump circuit further comprises: a seventh resistor having one end coupled to the fourth diode cathode and the other end grounded; and an eighth resistor disposed between the second pin and the third capacitor.

In some embodiments, the circuitry further comprises a sixth resistor, a twelfth resistor, and a thirteenth resistor, and wherein the sixth resistor is coupled at one end to the first pin and at the other end to ground; the twelfth resistor is coupled to the second pin at one end and grounded at the other end; and one end of the thirteenth resistor is coupled to a fifth line, and the other end of the thirteenth resistor is grounded, and the fifth line is coupled to the input pin after the third line and the fourth line are converged.

In a second aspect of the present disclosure, a vehicle is provided. The vehicle comprises circuitry for vehicle fault protection according to the first aspect of the present disclosure.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements. The accompanying drawings are included to provide a better understanding of the present disclosure, and are not to be construed as limiting the disclosure, wherein:

FIG. 1 illustrates a dual MCU vehicle fault protection circuitry employed in the prior art;

FIG. 2 illustrates an example usage scenario of circuitry according to some embodiments of the present disclosure; and

fig. 3 illustrates example circuitry according to some embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below. It should be appreciated that the terms "coupled," "electrically coupled," "connected," "electrically connected," and "electrically coupled" are used interchangeably with each other in certain circumstances. In addition, diodes, triodes, capacitors, resistors (also referred to as "resistors") and the like described below may be any suitable electronic components commonly used in the art, as long as the corresponding functions can be implemented, which is not limited in this disclosure.

Exemplary embodiments of the present disclosure will be described below in conjunction with fig. 1-3.

Fig. 1 shows a dual MCU vehicle fault protection circuitry employed in the prior art. As described above, referring to fig. 1, the present circuitry generally employs two MCUs, a master MCU U1 and a slave MCU U2, which interact in real time and monitor each other. When the main MCU U1 fails, the slave MCU detects that the main MCU fails, and receives related control before failure, and drives the automobile to enter a limp home mode after receiving signals through the input pin IN of the driving chip U3, so that related functions are realized. However, in such a scheme, two MCUs are employed, resulting in high hardware costs and relatively complex software logic.

Based on this, each embodiment of the disclosure utilizes a single MCU and discrete circuit elements, latches the state output by the MCU in real time through two interlocking circuits, outputs to the driving chip, and under the condition that the MCU at any moment fails, the output state before failure can be latched, even if the pin of the MCU is in an uncertain state, the driving chip is not affected, and the operation continues with the current state. Therefore, the high cost and high complexity of the complex limp home mode function under the vehicle fault mode can be overcome, and a limp home function circuit with low cost and high robustness can be built based on a single MCU and discrete devices.

Fig. 2 illustrates an example usage scenario of circuitry according to some embodiments of the present disclosure. In the embodiment shown in fig. 2, vehicle 100 may be any type of vehicle that may carry a person and/or object and that is moved by a power system such as an engine, including, but not limited to, a car, truck, bus, electric vehicle, motorcycle, caravan, train, and the like. In some embodiments, vehicle 100 may be a vehicle having some autopilot capability, such a vehicle also being referred to as an unmanned vehicle. In some embodiments, vehicle 100 may also be a vehicle that does not have autopilot capability or a semi-autopilot vehicle.

With continued reference to fig. 2, circuitry 101 is coupled in the vehicle 100. Although shown as a separate entity, circuitry 101 may be embedded in vehicle 100. Circuitry 101 may also be an entity external to vehicle 100 and may communicate with vehicle 100 via a wireless network. Circuitry 101 may be circuitry capable of implementing vehicle fault protection, such as the schematic circuitry shown in fig. 3, described in detail below.

Fig. 3 illustrates example circuitry according to some embodiments of the present disclosure. Wherein the circuitry shown in fig. 3 may be implemented, for example, as circuitry 101 in fig. 2.

As shown in fig. 3, the circuitry 101 may include a single main control chip U1, a driver chip U2, and functional circuitry between the main control chip U1 and the driver chip U2. The main control chip U1 may include a first Pin1 and a second Pin2, and the driving chip U2 may include an input Pin IN. With continued reference to fig. 3, the main control chip U1 performs the relevant control according to the actual control demand. When the output of the main control chip U1 is high or low, the output is outputted to the input pin IN of the driving chip U2 through the functional circuit between the main control chip U1 and the driving chip U2, so as to perform the control related to the vehicle 100. When the MCU fails, the MCU enters a limp home mode, and the driving chip U2 must keep the current running state to continue running, but at this time, the output of the main control chip U1 may change, so that the control state changes, and the requirement is not met. At this time, the functional circuit between the main control chip U1 and the driving chip U2 shown in fig. 3 latches the state output by the main control chip U1 in real time, outputs the latched state to the driving chip U2, and when the main control chip U1 fails at any time, the output state before failure will be latched, even if the pins (for example, the first Pin1 and the second Pin 2) of the main control chip U1 are in an uncertain state, the driving chip will not be affected, and the operation continues in the current state, thereby realizing the limp home.

In some embodiments, referring to fig. 3, the functional circuit between the main control chip U1 and the driving chip U2 may include a first latch circuit (a branch formed by the second transistor Q2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the third transistor Q3 may be specifically described in detail below), a second latch circuit (a branch formed by the fifth transistor Q5, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, and the sixth transistor Q6 may be specifically described in detail below), a first charge pump circuit (a branch formed by the first diode D1, the second diode D2, the first transistor Q1, the first capacitor C1, the second capacitor C2, the first resistor R1, the second resistor R2 may be specifically described in detail below), and a second charge pump circuit (a branch formed by the third diode D3, the fourth diode D4, the fourth transistor Q4, the third capacitor C4, the fourth capacitor C5, the seventh capacitor R7, and the eighth resistor R8 may be specifically described in detail below). IN one embodiment, a first latching circuit is electrically coupled at one end to the first Pin1 and at the other end to the input Pin IN, a second latching circuit is electrically coupled at one end to the second Pin2 and at the other end to the input Pin IN, wherein the second latching circuit is electrically coupled to the first Pin1 via the second line 2, and wherein the first latching circuit is electrically coupled to the second Pin2 via the first line 1 to interlock the first latching circuit and the second latching circuit; further, the first charge pump circuit is electrically coupled to the first latching circuit and adapted to unlock the first latching circuit upon a state switch. The second charge pump circuit is coupled to the second latching circuit and adapted to unlock the second latching circuit upon a state switch.

In such an embodiment, the first and second latch circuits are latch circuits of the first Pin1 and the second Pin2, respectively, to latch the state output by the main control chip U1 in real time. When the first Pin1 of the main control chip U1 outputs a high level (hereinafter, simply referred to as "high"), the state of the second Pin2 is pulled to a low level (hereinafter, simply referred to as "low") through the first line 1, preventing the state of the second Pin2 from affecting the output. When the output of the second Pin2 is high, the Pin state of the first Pin1 is pulled down through the second circuit 2, so that the state of the first Pin1 is prevented from affecting the output, and the first circuit 1 and the second circuit 2 form an interlocking circuit.

Further, the first charge pump circuit and the second charge pump circuit are respectively a charge pump circuit of the first Pin1 and a charge pump circuit of the second Pin2, and are used for unlocking the self-locking circuit to realize state switching.

Therefore, under the condition of a single MCU, functional circuits of the main control chip U1 and the driving chip U2 can be built based on discrete elements, the complex limp home function is realized, the realization cost of a circuit system is reduced, and the reliability of the circuit system is improved.

In one particular example, with continued reference to fig. 3, the first self-locking circuit may include a second transistor Q2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a third transistor (Q3). The emitter of the second transistor Q2 is coupled to the first charge pump circuit, specifically, to the collector of the first transistor Q1, as will be described in detail below. The base of the second transistor Q2 may be coupled to the collector of the third transistor Q3 via a fourth resistor R4, and the collector of the second transistor Q2 is coupled to the input pin IN via a third line 3. Specifically, the third line 3 may be followed by the fifth line 5 to be coupled to the input pin IN.

In this embodiment, the fifth resistor R5 may have one end coupled to the first Pin1, one of the branches of the other end coupled to the base of the third transistor Q3, and the other branch coupled to the collector of the second transistor Q2 via the third resistor R3. In such an embodiment, the emitter of the third transistor Q3 is grounded.

In one embodiment, as the unlocking circuit of the first Pin1, the first charge pump circuit may include a first diode D1, a second diode D2, a first transistor Q1, a first capacitor C1, and a second capacitor C2. Wherein the first diode D1 and the second diode D2 are connected in series, and the anode of the first diode D1 is coupled to an operating voltage, for example, 3.3V as shown in fig. 3. The base of the first transistor Q1 may be coupled to the cathode of the second diode D2, the emitter of the first transistor Q1 may be coupled to an operating voltage (e.g., 3.3V as shown in fig. 3) and the collector of the first transistor Q1 may be coupled to the emitter of the second transistor Q2.

In this embodiment, one plate of the first capacitor C1 is coupled to the anode of the second diode D2, and the other plate is coupled to the first Pin1. In other words, the upper plate of the first capacitor C1 is located between the first diode D1 and the second diode D2 connected in series, and the lower plate of the first capacitor C1 is coupled to the first Pin1. In another embodiment, the lower plate of the first capacitor C1 may be connected in series with the second resistor R2, and then coupled to the first Pin1 through the second resistor R2.

In this embodiment, one plate of the second capacitor C2 may be coupled to the negative electrode of the second diode D2 and the other plate may be grounded.

Further, the first charge pump circuit may further include a first resistor R1. One end of the first resistor R1 may be coupled to the cathode of the second diode D2, and the other end of the first resistor R1 is grounded.

Therefore, the first self-locking circuit and the first charge pump circuit are respectively a self-locking circuit and an unlocking circuit of the first Pin Pin1, so that the self-locking circuit and the state switching of the circuits can be realized by matching with a second self-locking circuit and a second charge pump circuit which are described below.

In another embodiment, with continued reference to fig. 3, the second self-locking circuit may include a fifth transistor Q5, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a sixth transistor Q6, similar to the first self-locking circuit. One end of the eleventh resistor R11 may be coupled to the second Pin2, and the other end of the eleventh resistor R11 is connected to two branches, wherein one branch is coupled to the base of the sixth transistor Q6 and the other branch may be coupled to the collector of the fifth transistor Q5 through the ninth resistor R9. Further, the emitter of the fifth transistor Q5 is coupled to the collector of the second charge pump circuit, specifically, the fourth transistor Q4, and the base of the fifth transistor Q5 may be coupled to the collector of the sixth transistor Q6 via a tenth resistor R10. Preferably, the emitter of the sixth transistor Q6 may be grounded and the collector of the sixth transistor Q6 is coupled to the input pin IN via the fourth line 4. IN yet another embodiment, the input pin IN may be further coupled to the fifth line 5 after passing through the fourth line 4.

In the above embodiment, the first line 1 may be specifically coupled to the second Pin2 by the collector of the third transistor Q3, and the second line 2 may be coupled to the first Pin1 by the collector of the sixth transistor Q6.

In one embodiment, as the unlocking circuit of the second Pin2, the second charge pump circuit may include a third diode D3, a fourth diode D4, a fourth transistor Q4, a third capacitor C4, and a fourth capacitor C5. Wherein, the third diode D3 and the fourth diode D4 are connected in series, and the positive electrode of the third diode D3 is coupled to an operating voltage, for example, 3.3V as shown in fig. 3. The fourth transistor Q4 has a base coupled to the cathode of the fourth diode D4, an emitter coupled to an operating voltage (e.g., 3.3V as shown in fig. 3) and a collector of the fourth transistor Q4 coupled to the emitter of the fifth transistor Q5.

In this embodiment, one plate of the third capacitor C4 is coupled to the anode of the fourth diode D4, and the other plate of the third capacitor C4 is coupled to the second Pin2. In other words, the upper plate of the third capacitor C4 is located between the third diode D3 and the fourth diode D4 connected in series, and the lower plate of the third capacitor C4 is coupled to the second Pin2. In another embodiment, the bottom plate of the third capacitor C4 may be connected in series with the eighth resistor R8, and then coupled to the second Pin2 through the eighth resistor R8.

In this embodiment, one plate of the fourth capacitor C5 may be coupled to the negative electrode of the fourth diode D4, and the other plate of the fourth capacitor C5 may be grounded.

Further, the second charge pump circuit may further include a seventh resistor R7. One end of the seventh resistor R7 is coupled to the cathode of the fourth diode D4, and the other end of the seventh resistor R7 is grounded.

Therefore, the second self-locking circuit and the second charge pump circuit are respectively a self-locking circuit and an unlocking circuit of the second Pin Pin2, so that the self-locking circuit and the state switching of the circuits can be realized by matching with the first self-locking circuit and the first charge pump circuit.

In one embodiment, with continued reference to fig. 3, circuitry 101 may further include a sixth resistor R6, a twelfth resistor R12, and a thirteenth resistor R13. The sixth resistor R6 may have one end coupled to the first Pin1 and the other end grounded, the twelfth resistor R12 may have one end coupled to the second Pin2 and the other end grounded, and the thirteenth resistor (R13) has one end coupled to the fifth line 5 and the other end grounded. IN this embodiment, the fifth line 5 is coupled to the input pin IN of the driving chip U2 after being merged by the third line 3 and the fourth line 4.

The principle of operation of the present circuitry 101 will be described in detail below in connection with fig. 3.

As shown in fig. 3, in the circuit system 101, when the automobile 100 is in an operating state, the first transistor Q1 in the first charge pump circuit and the fourth transistor Q4 in the second charge pump circuit are in a default closed state. When the requirement of the driving chip U2 is "high", the first Pin1 of the main control chip U1 will output as "high", and at this time, the third triode Q3 is closed by driving the third triode Q3, and then the second triode Q2 is closed again, and the second triode Q2 and the third triode Q3 are always in the closed state by the principle of the self-locking circuit, so that even if the state of the first Pin1 of the main control chip U1 changes, the states of the second triode Q2 and the third triode Q3 will not be affected. And the Pin output of the second Pin Pin2 of the main control chip U1 is pulled down through the first circuit 1, so that an interlocking function is realized. At this time, a high level is transferred to the fifth line 5 through the third line 3, thereby controlling the driving chip U2. When the main control chip U1 fails, the states of the first Pin1 and the second Pin2 of the main control chip U1 are uncertain, may be "high" and may be "low", and when the state of the fifth line 5 is always "high" through the self-locking and interlocking described above, the state will not change, so as to achieve the purpose of executing the continuous operation of the current state.

Further, when the requirement of the driving chip U2 is "low", the second Pin2 of the main control chip U1 will output "high", but the current state of the driving chip U2 is already latched, and needs to be unlocked by the charge pump circuit, and before the second Pin2 outputs "high", the first Pin1 can send out a PWM signal of millisecond level, for example, and the first triode Q1 is driven to be turned off by the positive voltage charge pump. At this time, the self-locking circuit is unlocked. After that, the output of the second Pin2 is high, the sixth triode Q6 is closed by driving the sixth triode Q6, then the fifth triode Q5 is closed again, and the states of the fifth triode Q5 and the sixth triode Q6 are not affected even if the states of the second Pin2 change due to the principle of a self-locking circuit. And the Pin output of the first Pin Pin1 of the main control chip U1 is pulled down through the second circuit 2, so that an interlocking function is realized. At this time, a low level is transmitted to the fifth line 5 through the fourth line 4, thereby controlling the driving chip. When the main control chip U1 fails, the states of the first Pin1 and the second Pin2 of the main control chip U1 are uncertain, may be "high" and may be "low", and when the self-locking and the interlocking are performed, the state of the fifth line 5 is always low and will not change, so that the purpose of executing the continuous running of the current state is achieved.

In summary, each embodiment of the present disclosure utilizes a single main control unit and discrete circuit elements to latch the state output by the main control unit in real time through two interlocking circuits, and output the state to the driving chip, and in the case that the main control unit fails at any moment, the output state before failure will be latched, even if the pin of the main control unit is in an uncertain state, the driving chip will not be affected, and the operation continues with the current state. Therefore, the high cost and high complexity of the complex limp home mode function under the vehicle fault mode can be overcome, and the low-cost and high-robustness functional circuit system for vehicle fault protection can be built based on the single main control unit and the discrete devices. The system can be widely applied to various types of vehicles.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A circuit system for vehicle fault protection, comprising:

a main control chip (U1) comprising a first Pin (Pin 1) and a second Pin (Pin 2);

a driving chip (U2) adapted to drive a vehicle via control of the main control chip (U1) and comprising an input pin (IN);

a first self-locking circuit, one end of which is electrically coupled to the first Pin (Pin 1) and the other end of which is electrically coupled to the input Pin (IN);

a second latching circuit having one end electrically coupled to the second Pin (Pin 2) and the other end electrically coupled to the input Pin (IN), wherein the second latching circuit is electrically coupled to the first Pin (Pin 1) via a second line (2), and wherein the first latching circuit is electrically coupled to the second Pin (Pin 2) via a first line (1) to interlock the first latching circuit and the second latching circuit;

a first charge pump circuit electrically coupled to the first latching circuit and adapted to unlock the first latching circuit upon a state switch; and

a second charge pump circuit is coupled to the second latching circuit and adapted to unlock the second latching circuit upon a state switch.

2. The circuitry of claim 1, wherein the first self-locking circuit comprises a second transistor (Q2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), and a third transistor (Q3), and wherein:

-the emitter of the second transistor (Q2) is coupled to the first charge pump circuit, the base thereof is coupled to the collector of the third transistor (Q3) via the fourth resistor (R4), and the collector thereof is coupled to the input pin (IN) via a third line (3); and

the fifth resistor (R5) has one end coupled to the first Pin (Pin 1), the other end coupled to the base of the third transistor (Q3) and the other end coupled to the collector of the second transistor (Q2) via the third resistor (R3), and the emitter of the third transistor (Q3) is grounded.

3. The circuitry of claim 2, wherein the second self-locking circuit comprises a fifth transistor (Q5), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11), and a sixth transistor (Q6), and wherein:

-said eleventh resistor (R11) has one end coupled to said second Pin (Pin 2), the other end having a branch coupled to the base of said sixth transistor (Q6) and the other branch coupled to the collector of said fifth transistor (Q5) via said ninth resistor (R9);

-the emitter of the fifth transistor (Q5) is coupled to the second charge pump circuit, the base of which is coupled to the collector of the sixth transistor (Q6) via the tenth resistor (R10); and

the sixth transistor (Q6) has its emitter grounded and its collector coupled to the input pin (IN) via a fourth line (4).

4. A circuit system according to claim 3, characterized in that the first line (1) is coupled to the second Pin (Pin 2) by the collector of the third transistor (Q3) and the second line (2) is coupled to the first Pin (Pin 1) by the collector of the sixth transistor (Q6).

5. The circuitry of claim 2, wherein the first charge pump circuit comprises:

a first diode (D1) having an anode coupled to an operating voltage;

-a second diode (D2) connected in series with said first diode (D1);

a first transistor (Q1) having a base coupled to the cathode of the second diode (D2), an emitter coupled to an operating voltage and a collector coupled to the emitter of the second transistor (Q2);

a first capacitor (C1), one plate being coupled to the anode of the second diode (D2) and the other plate being coupled to the first Pin (Pin 1); and

a second capacitor (C2), one plate being coupled to the second diode (D2) cathode and the other plate being grounded.

6. The circuitry of claim 5, wherein the first charge pump circuit further comprises:

a first resistor (R1) having one end coupled to the cathode of the second diode (D2) and the other end grounded; and

and a second resistor (R2) provided between the first Pin (Pin 1) and the first capacitor (C1).

7. The circuitry of claim 3, wherein the second charge pump circuit comprises:

a third diode (D3) having an anode coupled to the operating voltage;

a fourth diode (D4) connected in series with the third diode (D3);

a fourth transistor (Q4) having a base coupled to the cathode of the fourth diode (D4), an emitter coupled to an operating voltage and a collector coupled to the emitter of the fifth transistor (Q5);

a third capacitor (C4), one plate being coupled to the anode of the fourth diode (D4) and the other plate being coupled to the second Pin (Pin 2); and

a fourth capacitor (C5), one plate being coupled to the negative electrode of the fourth diode (D4) and the other plate being grounded.

8. The circuitry of claim 7, wherein the second charge pump circuit further comprises:

a seventh resistor (R7) having one end coupled to the cathode of the fourth diode (D4) and the other end grounded; and

an eighth resistor (R8) is arranged between the second Pin (Pin 2) and the third capacitor (C4).

9. The circuitry of claim 4, further comprising a sixth resistor (R6), a twelfth resistor (R12), and a thirteenth resistor (R13), wherein:

-said sixth resistor (R6) is coupled at one end to said first Pin (Pin 1) and at the other end to ground;

-the twelfth resistor (R12) is coupled at one end to the second Pin (Pin 2) and at the other end to ground; and

the thirteenth resistor (R13) has one end coupled to a fifth line (5) and the other end grounded, and the fifth line (5) is coupled to the input pin (IN) after being converged by the third line (3) and the fourth line (4).

10. A vehicle characterized by comprising a circuit system for vehicle fault protection according to any of claims 1 to 9.