CN117353574A - Electronic system - Google Patents

Electronic system Download PDF

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Publication number
CN117353574A
CN117353574A CN202310760794.0A CN202310760794A CN117353574A CN 117353574 A CN117353574 A CN 117353574A CN 202310760794 A CN202310760794 A CN 202310760794A CN 117353574 A CN117353574 A CN 117353574A
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CN
China
Prior art keywords
power
capacitor
regulator
mode
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310760794.0A
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Chinese (zh)
Inventor
黄志坚
丁明强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/320,442 external-priority patent/US20240012438A1/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN117353574A publication Critical patent/CN117353574A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0063—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with circuits adapted for supplying loads from the battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/20—Charging or discharging characterised by the power electronics converter

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

The invention provides an electronic system with a power supply voltage stabilizer, which can reduce surge current. An output capacitance device coupled between the power supply regulator and the load has a first capacitor and a second capacitor. When the power regulator is in the first power mode, both the first capacitor and the second capacitor are coupled to the power regulator. When the power regulator is in a second power mode using less power than the first power mode, the first capacitor is still coupled to the power regulator, but the second capacitor is disconnected from the power regulator and is thereby protected from discharge by the power regulator.

Description

Electronic system
Technical Field
Embodiments of the present invention relate generally to power conditioning technology and, more particularly, to electronic systems having power regulators.
Background
A power regulator (power regulator) is a DC-DC (direct current to direct current, direct current-to-direct current) power converter or Low Drop Out (LDO) regulator that converts a power supply voltage (e.g., received from a battery) to an output voltage to drive a load.
Surge current is generated when the power supply regulator is switched from the power-off mode to the power-on mode. Inrush current may also occur when switching a power regulator from a low power mode to a normal power mode when dynamic voltage regulation (dynamic voltage scaling, DVS) functions are enabled.
How to reduce the surge current is an important subject in the art.
Disclosure of Invention
The following summary is illustrative only and is not intended to be in any way limiting. That is, the following summary is provided to introduce a selection of concepts, emphasis, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Accordingly, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.
It is an object of the present application to provide an electronic system with a power supply voltage regulator that is capable of reducing surge current.
The invention provides an electronic system, comprising: a power supply voltage stabilizer; and an output capacitor device coupled to the power regulator. Wherein the output capacitance means comprises a first capacitor and a second capacitor; when the power supply voltage stabilizer is in a first power mode, the first capacitor and the second capacitor are electrically coupled with the power supply voltage stabilizer; the first capacitor is electrically coupled to the power regulator when the power regulator is in a second power mode that uses less power than the first power mode, and the second capacitor is disconnected from the power regulator such that the second capacitor is protected from discharge by the power regulator.
In some embodiments, the first power mode is a power-on mode and the second power mode is a power-off mode.
In some embodiments, the first power mode is a normal power mode of a dynamic voltage scaling function, and the second power mode is a low power mode of the dynamic voltage scaling function.
In some embodiments, the electronic system further comprises: and the charge supply is used for coupling the second capacitor when the power supply voltage stabilizer works in the second power mode so as to compensate the electric leakage of the second capacitor.
In some embodiments, when the power regulator is operating in the first power mode, the first capacitor and the second capacitor are both further electrically coupled to a load; and when the power supply voltage regulator operates in the second power mode, the first capacitor is still electrically coupled to the load, but the second capacitor is disconnected from the load.
In some embodiments, when the power regulator is operating in the first power mode, the first capacitor and the second capacitor are both further electrically coupled to a load; and when the power regulator is operating in the second power mode, the first capacitor and the second capacitor are both maintained electrically coupled to the load.
In some embodiments, the power supply voltage regulator includes: a source electrode of the first power MOS transistor is coupled with a power supply voltage, and a drain electrode of the first power MOS transistor is coupled with the first capacitor through a first output end of the power supply voltage stabilizer; a source electrode of the second power MOS transistor is coupled with the power supply voltage, a grid electrode of the second power MOS transistor is coupled with the grid electrode of the first power MOS transistor, and a drain electrode of the second power MOS transistor is coupled with the second capacitor through a second output end of the power supply voltage stabilizer; wherein the second power MOS transistor is turned off when the power regulator operates in the second power mode.
In some embodiments, the power supply voltage regulator further comprises: a first switch coupled between the gate of the first power MOS transistor and the gate of the second power MOS transistor, wherein the first switch is turned on when the power regulator operates in the first power mode and the first switch is turned off when the power regulator operates in the second power mode; and a second switch that is turned on when the power regulator operates in the second power mode to couple the gate of the second power MOS transistor to the power supply voltage.
In some embodiments, the load has a first power terminal coupled to the first output terminal of the power regulator and a second power terminal coupled to the second output terminal of the power regulator.
In some embodiments, the load further comprises: a circuit for receiving power from the first power terminal and the second power terminal; and a third switch coupled between the second power terminal and the circuit, wherein the third switch is turned on when the power regulator is operated in the first power mode and is turned off when the power regulator is operated in the second power mode.
In some embodiments, the power supply voltage regulator further comprises: a charge supply, powered by the power supply voltage,
when the power supply voltage stabilizer works in the second power mode, the charge supply is coupled to the second capacitor through the second output end of the power supply voltage stabilizer so as to compensate the electric leakage of the second capacitor.
In some embodiments, the electronic system further comprises: and a battery for supplying power to the charge supply device to compensate for the leakage of the second capacitor.
In some embodiments, the charge supply includes: and a current source driven by the power supply voltage to compensate for leakage of the second capacitor.
In some embodiments, the charge supply further comprises: a fourth switch that is turned on when the power regulator is operating in the second power mode to couple the current source to the second capacitor through the second output of the power regulator; and a comparator for generating a control signal to control the current source; the first input end of the comparator is coupled to the second output end of the power supply voltage stabilizer through the fourth switch, and the second input end of the comparator is biased at a reference voltage.
In some embodiments, the second capacitor is changed to be disconnected from the power supply voltage regulator during a buck phase of switching from the first power mode to the second power mode.
In some embodiments, the second capacitor is changed to be coupled to the power supply regulator during a boost phase of switching from the second power mode to the first power mode.
In an embodiment of the present invention, when the power regulator is operated in the second power mode, a large amount of charge is stored in the second capacitor, so that when the power regulator switches back to the first power mode to raise its output voltage, the surge current will be reduced by the charge held by the second capacitor.
These and other objects of the present invention will be readily understood by those skilled in the art after reading the following detailed description of the preferred embodiments as illustrated in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings.
Drawings
The accompanying drawings, in which like numerals indicate like components, illustrate embodiments of the invention. The accompanying drawings are included to provide a further understanding of embodiments of the disclosure, and are incorporated in and constitute a part of the embodiments of the disclosure. The drawings illustrate implementations of embodiments of the present disclosure and, together with the description, serve to explain principles of embodiments of the present disclosure. It is to be understood that the drawings are not necessarily to scale, because some components may be shown out of scale from actual implementation to clearly illustrate the concepts of the embodiments of the disclosure.
Fig. 1 is a block diagram of an electronic system 100, shown according to an exemplary embodiment of the present invention.
Fig. 2 is an electronic system 200 according to another exemplary embodiment of the invention.
Fig. 3 is a control scheme illustrating the output capacitance device 108 according to an exemplary embodiment of the present invention.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. It will be apparent, however, that one or more embodiments may be practiced without these specific details, and that different embodiments may be combined as desired and should not be limited to the embodiments set forth in the drawings.
Detailed Description
The following description is of preferred embodiments of the invention, which are intended to illustrate the technical features of the invention, but not to limit the scope of the invention. Certain terms are used throughout the description and claims to refer to particular elements, and it will be understood by those skilled in the art that manufacturers may refer to a like element by different names. Therefore, the present specification and claims do not take the difference in names as a way of distinguishing elements, but rather take the difference in functions of elements as a basis for distinction. The terms "element," "system," and "apparatus" as used in the present invention may be a computer-related entity, either hardware, software, or a combination of hardware and software. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …". Furthermore, the term "coupled" means an indirect or direct electrical connection. Thus, if one device is coupled to another device, that device can be directly electrically connected to the other device or indirectly electrically connected to the other device through other devices or connection means.
Wherein corresponding numerals and symbols in the various drawings generally refer to corresponding parts, unless otherwise indicated. The drawings are clearly illustrative of relevant portions of the embodiments and are not necessarily drawn to scale.
The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved, substantially to achieve the technical effect to be achieved. For example, "substantially equal" refers to a manner in which a technician can accept a certain error from "exactly equal" without affecting the accuracy of the result.
Fig. 1 is a block diagram illustrating an electronic subsystem (electronic system) 100, which may be a cell phone, tablet computer, or any mobile electronic device, in accordance with an exemplary embodiment of the present invention. The electronic system 100 uses a power regulator (power regulator) 102 to convert a power supply voltage Vin to an output voltage Vout to drive a load 106. The supply voltage Vin may be provided by a battery 104 of the electronic system 100. Load 106 may be a central processing unit (central processing unit, CPU) or any chip in electronic system 100.
Further, the electronic system 100 also includes an output capacitor device (output capacitance device) 108 coupled between the power regulator 102 and the load 106 (or, the output capacitor device 108 is coupled to the power regulator 102 and the load 106 via an output terminal of the power regulator 102). The output capacitance means 108 comprises a first capacitor C1 and a second capacitor C2, instead of being implemented by a single capacitor (single capacitor). The power regulator 102 may switch between different power modes (power modes). In different power modes, capacitors C1 and C2 are coupled to power regulator 102 in different ways.
In an exemplary embodiment, the power regulator 102 may be switched between a first power mode and a second power mode. In some examples, the output voltage Vout in the first power mode is greater than the output voltage Vout in the second power mode. In other examples, the second power mode is more power efficient than the first power mode. When the power regulator 102 is operating in the first power mode, the first capacitor C1 and the second capacitor C2 are electrically coupled (also referred to as "connected" or "electrically connected") to the power regulator 102 and are electrically coupled to the load 106. When the power regulator 102 is operating in the second power mode, the first capacitor C1 is still electrically coupled to the power regulator 102 and the load 106, but the second capacitor C2 is disconnected from the power regulator 102 and the load 106. Thus, in the second power mode, the second capacitor C2 is protected from being discharged by the power regulator 102. It should be noted that the output capacitor device 108 shown in the drawings is only an example structure, and the present invention is not limited to this example, and the output capacitor device 108 of the present invention can be implemented as all the capacitor devices that can realize that the first capacitor C1 and the second capacitor C2 are electrically coupled to the power regulator 102 and the load 106 in the first power mode, and that the second capacitor C2 is disconnected from the power regulator 102 and the load 106 in the second power mode (but the first capacitor is still electrically coupled to the power regulator 102 and the load 106).
In this way, when the power supply regulator 102 is operating in the second power mode (e.g., the second power mode uses less power than the first power mode), a substantial amount of charge remains in the isolated (isolated) second capacitor C2. When the power regulator 102 switches back to the first power mode to boost (also referred to as "boost") the output voltage Vout, the second capacitor C2 is reconnected to the power regulator 102. The power regulator 102 switched back to the first power mode will not generate a significant inrush current (huge inrush current) due to the charge previously stored in the second capacitor C2.
In an exemplary embodiment, the first power mode is a power-on mode (power-on mode) and the second power mode is a power-off mode (power-off mode). For example, in the power-off mode, the output voltage Vout is 0V (volt). In the power-on mode, the output voltage Vout is Von volts. In the conventional technology, when the power supply voltage regulator is switched from the power-off mode to the power-on mode, the surge charge Δqold is von×ctotal, where Ctotal is c1+c2. However, in the electronic system 100 provided by the present invention, when the power regulator 102 is switched from the power-off mode to the power-on mode, the surge charge Δqnew is von×c1, which is lower than Δqold. Thus, the surge current is reduced, and less surge charge is wasted.
In another exemplary embodiment, the power regulator 102 has a dynamic voltage scaling (dynamic voltage scaling, DVS) function. For example, the first power mode is a normal power mode (normal-power mode), and the second power mode is a low-power mode (low-power mode). In the normal power mode, the output voltage Vout is Vhigh volts. In the low power mode, the output voltage Vout is Vlow volts, where Vlow is less than Vhigh. In the conventional technology, when switching the power supply voltage regulator from the low power mode to the normal power mode, the surge charge Δqold is (Vhigh-Vlow) ×ctotal, where Ctotal is c1+c2. However, in the electronic system 100 provided by the present invention, when the power regulator 102 is switched from the low power mode to the normal power mode, the surge charge Δqnew is (Vhigh-Vlow) ×c1, which is lower than Δqold. Thus, the surge current is reduced, and less surge charge is wasted.
As shown, the electronic system 100 further includes a charge provider (charge supplier) 110. When the power regulator 102 operates in the second power mode, the charge supply 110 is coupled to the second capacitor C2 to compensate for leakage (leakage) of the isolated second capacitor C2. The battery 104 may also provide power to the charge supply 104.
In some other examples, when the power supply regulator 102 is operating in the second power mode, the second capacitor C2 is still electrically coupled to the load 106. For example, the second capacitor C2 may be selectively coupled to the power supply regulator through one switch, and the second capacitor C2 may also be selectively coupled to the load through another switch.
Fig. 2 depicts an electronic system 200 according to another exemplary embodiment of the invention.
The power supply regulator 202 includes a first power MOS transistor (e.g., a PMOS transistor) Ml and a second power MOS transistor (e.g., another PMOS transistor) M2. The source of the first power MOS transistor M1 is coupled to the power voltage Vin, and the drain of the first power MOS transistor M1 is coupled to the first capacitor C1 through the first output terminal Vo1 of the power regulator 202. The source of the second power MOS transistor M2 is coupled to the power voltage Vin, the gate of the second power MOS transistor M2 is coupled to the gate of the first power MOS transistor M1, and the drain of the second power MOS transistor M2 is coupled to the second capacitor C2 through the second output terminal Vo2 of the power regulator 202. When the power supply regulator 202 is operating in the second power mode, the second power MOS transistor M2 is turned off (i.e., not turned on) to disconnect the second capacitor C2 from the power supply regulator 202.
In the present embodiment, the power supply voltage regulator 202 further includes a first switch S1 and a second switch S2. The first switch S1 is coupled between the gate of the first power MOS transistor M1 and the gate of the second power MOS transistor M2. The first switch S1 is on when the power regulator 202 is operating in the first power mode and is off when the power regulator 202 is operating in the second power mode. The second switch S2 is turned on when the power regulator 202 operates in the second power mode to couple the gate of the second power MOS transistor M2 to the power voltage Vin. Thus, in the second power mode, the second power MOS transistor M2 is truly off (indeed turned off), and thus, the second capacitor C2 is completely disconnected from the power supply regulator 202.
In fig. 2, the load 206 has a first power supply terminal Vi1 and a second power supply terminal Vi2, the first power supply terminal Vi1 is coupled to the first output terminal Vo1 of the power regulator 202, and the second power supply terminal Vi2 is coupled to the second output terminal Vo2 of the power regulator 202. The load 206 includes a circuit 212 (e.g., an input circuit or a processing circuit, etc.) that receives power from the first power source terminal Vi1 and the second power source terminal Vi 2. The third switch S3 is coupled between the second power terminal Vi2 and the circuit 212. When the power regulator 202 is operating in the first power mode, the third switch S3 is on. When the power supply regulator 202 is operating in the second power mode, the third switch S3 is open. In an embodiment of the invention, the third switch S3 is optional.
Fig. 2 also shows a charge supply 210 incorporated into the power regulator 202. The charge supply 210 is powered by a supply voltage Vin provided by the battery 204. When the power regulator 202 operates in the second power mode, the charge supply 210 is coupled to the second capacitor C2 through the second output Vo2 of the power regulator 202 to compensate for the leakage of the second capacitor C2.
Details of the charge supply 210 are described in this paragraph. The charge supply 210 includes a current source (current source) Ibias, a fourth switch S4, and a comparator Comp. The current source Ibias is driven by the supply voltage Vin. When the power regulator 202 operates in the second power mode, the fourth switch S4 is turned on to couple the current source Ibias to the second capacitor C2 through the second output Vo2 of the power regulator 202 to compensate for the leakage current of the second capacitor C2. The comparator Comp is used to generate a control signal CS to control the current source Ibias. The first input "-" of the comparator Comp is coupled to the second output Vo2 of the power regulator 202 through the fourth switch S4, and the second input "+" of the comparator Comp is biased at the reference voltage Vref. In this configuration, when the second capacitor C2 is isolated from the power supply regulator 202 in the second power mode and drops to a lower voltage level (lower voltage level), the current source Ibias can adaptively compensate for leakage loss (leakage loss).
Fig. 3 illustrates a control scheme of the output capacitance device 108 according to an exemplary embodiment of the present invention.
In phase 0 (labeled "phase 0" in the figure), the power regulator 102 is in the first power mode. In phase 2 (labeled "phase 2" in the figure), the power regulator 102 is in the second power mode. Phase 1 (labeled "phase 1" in the figure) refers to a step-down phase (voltage-swing phase) that switches from a first power mode to a second power mode. During phase 1, the second capacitor C2 is changed to be disconnected from the power regulator 102 (labeled "on→off" in the figure, i.e., C2 is changed from being on to being off from the power regulator 102). Phase 3 refers to a boost phase (voltage-rising phase) that switches from the second power mode to the first power mode. During phase 3 (labeled "phase 3" in the figure), the second capacitor C2 is changed to be coupled to the power regulator 102 (labeled "off→on" in the figure), i.e., C2 is changed from being off from the power regulator 102 to being on to the power regulator 102.
In the claims, ordinal terms such as "first," "second," "third," etc., are used to modify a claim element, and do not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a same name from another element having a same name using the ordinal term.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art), e.g., combinations or alternatives of the different features in the different embodiments. The scope of the following claims is, therefore, to be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (16)

1. An electronic system, comprising:
a power supply voltage stabilizer; and
an output capacitor device coupled to the power regulator;
wherein:
the output capacitance means comprises a first capacitor and a second capacitor;
when the power supply voltage stabilizer is in a first power mode, the first capacitor and the second capacitor are electrically coupled with the power supply voltage stabilizer;
the first capacitor is electrically coupled to the power regulator when the power regulator is in a second power mode that uses less power than the first power mode, and the second capacitor is disconnected from the power regulator such that the second capacitor is protected from discharge by the power regulator.
2. The electronic system of claim 1, wherein the first power mode is a power-on mode and the second power mode is a power-off mode.
3. The electronic system of claim 1, wherein the first power mode is a normal power mode of a dynamic voltage scaling function and the second power mode is a low power mode of the dynamic voltage scaling function.
4. The electronic system of claim 1, wherein the electronic system further comprises:
and the charge supply is used for coupling the second capacitor when the power supply voltage stabilizer works in the second power mode so as to compensate the electric leakage of the second capacitor.
5. The electronic system of claim 1, wherein:
when the power supply voltage stabilizer works in the first power mode, the first capacitor and the second capacitor are electrically coupled to a load; and
when the power regulator operates in the second power mode, the first capacitor is still electrically coupled to the load, but the second capacitor is disconnected from the load.
6. The electronic system of claim 1, wherein:
when the power supply voltage stabilizer works in the first power mode, the first capacitor and the second capacitor are electrically coupled to a load; and
when the power regulator operates in the second power mode, both the first capacitor and the second capacitor are maintained electrically coupled to the load.
7. The electronic system of claim 1, wherein the power regulator comprises:
a source electrode of the first power MOS transistor is coupled with a power supply voltage, and a drain electrode of the first power MOS transistor is coupled with the first capacitor through a first output end of the power supply voltage stabilizer;
a source electrode of the second power MOS transistor is coupled with the power supply voltage, a grid electrode of the second power MOS transistor is coupled with the grid electrode of the first power MOS transistor, and a drain electrode of the second power MOS transistor is coupled with the second capacitor through a second output end of the power supply voltage stabilizer;
wherein the second power MOS transistor is turned off when the power regulator operates in the second power mode.
8. The electronic system of claim 7, wherein the power regulator further comprises:
a first switch coupled between the gate of the first power MOS transistor and the gate of the second power MOS transistor, wherein the first switch is turned on when the power regulator operates in the first power mode and the first switch is turned off when the power regulator operates in the second power mode; and
a second switch is turned on when the power regulator is operating in the second power mode to couple the gate of the second power MOS transistor to the power supply voltage.
9. The electronic system of claim 7, wherein the load has a first power terminal and a second power terminal, the first power terminal is coupled to the first output terminal of the power regulator, and the second power terminal is coupled to the second output terminal of the power regulator.
10. The electronic system of claim 9, wherein the load further comprises:
a circuit for receiving power from the first power terminal and the second power terminal; and
a third switch coupled between the second power terminal and the circuit,
wherein the third switch is turned on when the power regulator is operated in the first power mode, and is turned off when the power regulator is operated in the second power mode.
11. The electronic system of claim 7, wherein the power regulator further comprises:
a charge supply, powered by the power supply voltage,
when the power supply voltage stabilizer works in the second power mode, the charge supply is coupled to the second capacitor through the second output end of the power supply voltage stabilizer so as to compensate the electric leakage of the second capacitor.
12. The electronic system of claim 4 or 11, further comprising:
and a battery for supplying power to the charge supply device to compensate for the leakage of the second capacitor.
13. The electronic system of claim 4 or 11, wherein the charge supply comprises:
and a current source driven by the power supply voltage to compensate for leakage of the second capacitor.
14. The electronic system of claim 13, wherein the charge supply further comprises:
a fourth switch that is turned on when the power regulator is operating in the second power mode to couple the current source to the second capacitor through the second output of the power regulator; and
a comparator for generating a control signal to control the current source;
the first input end of the comparator is coupled to the second output end of the power supply voltage stabilizer through the fourth switch, and the second input end of the comparator is biased at a reference voltage.
15. The electronic system of claim 1, wherein the second capacitor is changed to be disconnected from the power regulator during a buck phase of switching from the first power mode to the second power mode.
16. The electronic system of claim 15, wherein the second capacitor is changed to be coupled to the power supply regulator during a boost phase of switching from the second power mode to the first power mode.
CN202310760794.0A 2022-07-05 2023-06-26 Electronic system Pending CN117353574A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/367,656 2022-07-05
US18/320,442 2023-05-19
US18/320,442 US20240012438A1 (en) 2022-07-05 2023-05-19 Electronic system using a power regulator with reduced inrush current

Publications (1)

Publication Number Publication Date
CN117353574A true CN117353574A (en) 2024-01-05

Family

ID=89354595

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310760794.0A Pending CN117353574A (en) 2022-07-05 2023-06-26 Electronic system

Country Status (1)

Country Link
CN (1) CN117353574A (en)

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