CN113238604A - Constant voltage control circuit, chip and system - Google Patents
Constant voltage control circuit, chip and system Download PDFInfo
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Abstract
The invention discloses a constant voltage control circuit, a chip and a system, which comprise an error amplifier circuit, a ramp wave generating circuit, a square wave generating circuit and a logic processing unit circuit; the error amplifier circuit outputs a first comparison voltage, the ramp wave generating circuit outputs a second comparison voltage after receiving the first fixed voltage and the second fixed voltage, the square wave generating circuit outputs a third comparison voltage and a fourth comparison voltage after receiving the first comparison voltage, the second comparison voltage and the third fixed voltage respectively, the logic processing unit circuit outputs a logic control voltage signal after receiving the third fixed voltage, the first comparison voltage, the third comparison voltage and the fourth comparison voltage, and the charge and discharge of the first capacitor and the energy storage capacitor are carried out by controlling the on-off of the second power tube, so that the voltage at the output end is stable and unchanged. The invention can achieve the effect of completely floating the ground, realize that the power chip of the floating structure can control the output voltage accurately, and the internal circuit has simple structure, the cost and the technological requirement are greatly reduced.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a constant-voltage control circuit, a chip and a system adopting a floating structure.
Background
In order to meet the requirement of occasions with higher input voltage, a switching power supply system with higher withstand voltage is needed; for example, in a 48V electric vehicle system, the maximum voltage when the battery is fully charged reaches 56V, the motor is directly powered by the battery, but the controller and other circuits need a switching power supply to perform voltage reduction and conversion on the voltage of the battery; under normal conditions, only a voltage reduction conversion chip with the withstand voltage of about 60V needs to be used, but due to the existence of the motor during use, the highest reverse voltage peak can exist when the motor is started or stopped, the same reverse voltage peak is superposed on a power line, and the peak voltage of more than 100V can appear; exceeding the withstand voltage of the power chip, the peak voltage easily causes the power chip to fail.
In a power supply system with a traditional floating structure, an internal control chip gets power from an output end, the ground of the control chip is pulled to a power supply input end when a power tube is conducted, the ground of the control chip is pulled to the ground of a power supply when the power tube is turned off, and the internal reference voltage is not fixed relative to the ground of the power supply, so that a control circuit cannot directly collect the output voltage and compare the output voltage with the internal reference voltage to control the size of the output voltage.
In a power supply system with a traditional floating structure, an internal control chip gets power from an output end, the ground of the control chip is pulled to a power supply input end when a power tube is conducted, the ground of the control chip is pulled to the ground of a power supply when the power tube is turned off, and an internal reference voltage is not fixed relative to the ground of the power supply.
Disclosure of Invention
The invention aims to solve the technical problems that the existing power supply chip has low voltage resistance, can not meet the requirements of step-down conversion and accurate control of output voltage of an electric vehicle controller, and the existing floating structure has complex internal constant voltage circuit and higher cost. The invention adopts a mode of a floating structure with a simpler internal constant voltage circuit to solve the technical problem, the reference ground of the power constant voltage control chip is not the same as the input and the output of the power, so that the power supply voltage of the logic part of the power constant voltage control chip is not related to the input end, namely the voltage resistance of the logic part circuit can be far lower than the voltage of the system input end, and the output voltage can be accurately controlled.
The invention provides a constant voltage control circuit in a first aspect, which comprises an error amplifier circuit, a ramp wave generating circuit, a square wave generating circuit and a logic processing unit circuit;
the error amplifier circuit comprises an error amplifier, and the error amplifier receives a reference voltage and a voltage of a VFB pin of the constant voltage control chip and then outputs a first comparison voltage;
the ramp wave generating circuit comprises a first comparator, a second comparator and a first logic gate circuit connected with the output ends of the first comparator and the second comparator, the output end of the first logic gate circuit is connected with a grid of a first power tube connected with a third capacitor in parallel, the inverting input ends of the first comparator and the second comparator correspondingly receive a first fixed voltage and a second fixed voltage, the non-inverting input ends of the first comparator and the second comparator are connected with the drain electrode of the first power tube,
the first comparator and the second comparator output a second comparison voltage after detecting the voltage of the third capacitor, and the first power tube controls the charge and discharge of the third capacitor to adjust a signal of the second comparison voltage;
the square wave generating circuit comprises a third comparator and a fourth comparator, wherein the third comparator outputs a third comparison voltage, the fourth comparator outputs a fourth comparison voltage, the non-inverting input end of the third comparator is connected with the first comparison voltage, the inverting input end of the third comparator is connected with the second comparison voltage, the inverting input end of the fourth comparator is connected with the second comparison voltage, and the non-inverting input end of the fourth comparator is connected with the third fixed voltage;
the logic processing unit circuit comprises a fifth comparator and a second logic gate circuit, wherein the inverting input end of the fifth comparator is connected with a first comparison voltage, the non-inverting input end of the fifth comparator is connected with a third fixed voltage, the second logic gate circuit is connected with the output ends of the fifth comparator, the third comparator and the fourth comparator and outputs a logic control voltage signal for controlling the on-off of an external second power tube through an OR gate, and the charging and discharging of an external energy storage capacitor are controlled through the on-off of the second power tube, so that a constant voltage is realized;
wherein the first fixed voltage is greater than a third fixed voltage, which is greater than the second fixed voltage;
when the first comparison voltage is greater than the third fixed voltage, the logic control voltage signal is consistent with a fourth comparison voltage signal, and when the first comparison voltage is less than the third fixed voltage, the logic control voltage signal is consistent with a third comparison voltage signal.
Through controlling the voltage stability of the VFB pin of the constant voltage control chip is constant, the logic control voltage signal can be controlled to be constant, and the output voltage of the constant voltage control chip is stable.
As a further improvement, the first logic gate circuit comprises a first not gate, a first nand gate and a second nand gate, the output ends of the first nand gate and the second nand gate are respectively and correspondingly connected to the input end of the other nand gate, and the output end of the first nand gate is connected with the gate of the first power tube.
As a further improvement, the constant voltage control chip is connected with a charge-discharge circuit,
the charging and discharging circuit comprises a first diode, a second diode, a first inductor, a first capacitor, an energy storage capacitor, a first divider resistor and a second divider resistor, wherein a VFB pin is connected with one end of the first divider resistor and one end of the second divider resistor, the other ends of the first divider resistor and the second divider resistor are respectively connected to two poles of the first capacitor, one pole of the first capacitor is connected to one end of the first inductor, the other pole of the first capacitor is connected with the cathode of the second diode, the other end of the first inductor is connected with the anode of the energy storage capacitor, the cathode of the energy storage capacitor is connected with the anode of the first diode, the cathode of the first diode is connected with a first inductor connecting pin of the constant voltage control chip, and load resistors are connected in parallel to two ends of the energy storage capacitor; when the second power tube is switched on, an input end power supply connected with a pin of the constant voltage control chip VIN charges and stores energy for the first inductor and the energy storage capacitor, and simultaneously supplies power for a load at the rear end, the first capacitor is subjected to partial pressure discharge through the first divider resistor and the second divider resistor, during the turn-off period of the second power tube, the first inductor charges the energy storage capacitor through the first diode and charges the first capacitor through the second diode, and the energy storage capacitor discharges through the rear load.
As an embodiment, the on/off of the second power tube is affected by the logic control voltage signal, and when the logic control voltage signal is at a high level, the second power tube is turned on, otherwise, the second power tube is turned off.
When the power supply is just powered on, the logic control voltage signal works at a fixed duty ratio, after the logic control voltage signal is converted into a variable signal, the duty ratio is adjusted according to the voltage at two ends of the first capacitor, and after the second power tube in each period is turned off, the voltage at two ends of the first capacitor is clamped to the voltage at two ends of the energy storage capacitor.
As a further improvement, the input voltage at the inverting input end of the first comparator can be controlled by switching on and off the second power tube, so as to influence the output logic control voltage signal.
In a second aspect of the present invention, a constant voltage control chip is provided, where the constant voltage control chip includes the constant voltage control circuit, the constant voltage control circuit is connected to and controls a logic driving circuit, and the logic driving circuit is connected to and controls the charging and discharging circuit through a second power tube, so as to control the voltage of the VFB pin of the constant voltage control chip to be stable and unchanged.
In a third aspect of the present invention, a constant voltage control system is provided, where the constant voltage control system has the constant voltage control chip, and the constant voltage control chip is connected to the charge and discharge circuit, and regulates the voltage of the VFB pin of the constant voltage control chip by controlling the state of the second power transistor in the constant voltage control chip, so as to maintain the voltage at the output terminal stable.
The invention controls the state of the second power tube according to the logic control voltage signal output by the constant voltage control circuit, so as to regulate and control the output voltage, and controls the voltage stabilization of the output end by utilizing the charge-discharge circuit.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
FIG. 1 is a schematic diagram of an embodiment of a constant voltage control system according to the present invention.
Fig. 2 is a schematic diagram of an internal circuit of the constant voltage control chip according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a constant voltage control circuit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a ramp generated by the ramp generating circuit according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a square generated by the square wave generating circuit according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The constant voltage control circuit 500 shown in fig. 3 includes an error amplifier circuit 5001, a ramp wave generating circuit 5002, a square wave generating circuit 5003, and a logic processing unit circuit 5004.
The error amplifier circuit 5001 includes an error amplifier OP1, the inverting input terminal of the error amplifier OP1 is connected to the VFB pin of the constant voltage control chip, the VFB voltage is the voltage of the VFB pin of the chip, the non-inverting input terminal of the error amplifier OP1 is connected to a reference voltage VREF, the VREF voltage is provided by an internal reference voltage source circuit, and the error amplifier OP1 outputs a first comparison voltage VA according to the voltage of the VFB pin and the reference voltage VREF.
The output end of the error amplifier OP1 is connected to the third resistor R3 and the fourth capacitor C4 in sequence and then grounded.
The error amplifier circuit 5001, the ramp wave generating circuit 5002, the square wave generating circuit 5003 and the logic processing unit circuit 5004 are powered by a voltage VDD.
When the VFB voltage is relatively low, the error amplifier OP1 outputs a relatively high voltage value VA, when the VFB voltage rises to approach the VREF voltage, the VA voltage slowly decreases from the relatively high voltage value, and the first comparison voltage VA decreases as the VFB voltage increases and increases as the VFB voltage decreases.
The ramp wave generating circuit 5002 comprises a first comparator COMP1, a second comparator COMP2, and a first logic gate circuit connected with output ends of the first comparator COMP1 and the second comparator COMP2, wherein the output end of the first logic gate circuit is connected with the gate of a first power tube M1, an inverting input end of the first comparator COMP1 is connected with a first fixed voltage V1, an inverting input end of the second comparator COMP2 is connected with a second fixed voltage V2, a non-inverting input end of the first comparator COMP1 and a non-inverting input end of the second comparator COMP2 are connected with the drain of the first power tube M1, a third capacitor C3 is connected in parallel between the drain and the source of the first power tube M1, and the charging and discharging of the third capacitor C3 are controlled by controlling the on-off of the first power tube M1 to output a second comparison voltage VB.
The positive end of the third capacitor C3 IS connected to a constant current source IS1, the negative end IS grounded, and the constant current source IS1 IS a current source.
The first fixed voltage V1 and the second fixed voltage V2 are provided by the internal voltage stabilizing circuit in FIG. 2, the voltage of the first fixed voltage V1 is higher than that of the second fixed voltage V2, the non-inverting terminals of the first comparator COMP1 and the second comparator COMP2 are connected with the positive terminal of the third capacitor C3, the inverting terminal of the first comparator COMP1 is connected with the first fixed voltage V1, and the inverting terminal of the second comparator COMP2 is connected with the second fixed voltage V2; an output end of the first comparator COMP1 is connected to one input end of a first NAND gate NAND1 through a first NOT gate NOT1, another input end of the first NAND gate NAND1 is connected to an output end of the second NAND gate NAND2, an output end of the second comparator COMP2 is connected to one input end of a second NAND gate NAND2, and another input end of the second NAND gate NAND2 is connected to an output end of the first NAND gate NAND 1.
The first comparator COMP1 and the second comparator COMP2 detect the voltage of the third capacitor C3 and then output a second comparison voltage VB, and the signal of the second comparison voltage VB is adjusted by charging and discharging the third capacitor C3.
When the power IS turned on, the third capacitor C3 IS charged through the current source IS1, the voltage of the third capacitor C3 starts to rise from 0V at a fixed slope IS1/C3, the non-inverting terminals of the first comparator COMP1 and the second comparator COMP2 detect the voltage of the third capacitor C3, the voltage of the third capacitor C3 IS lower than the voltages of the second fixed voltage V2 and the first fixed voltage V1 in an initial state, and the first comparator COMP1 and the second comparator COMP2 output low levels at the same time; the low level output by the second comparator COMP2 is connected to one end of the second NAND gate NAND2, at this time, regardless of the state of the other end, the output of the second NAND gate NAND2 is always high level, the low level output by the first comparator COMP1 is converted into high level through the first NOT gate NOT1, at this time, the output level of the first NAND gate NAND1 is determined by the output level of the second NAND gate NAND2, the second NAND gate NAND2 outputs high level, the output of the first NAND gate NAND1 is low level, the low level is connected to the control end gate of the first power tube M1, the first power tube M1 is disconnected, and the third capacitor C3 continues to be charged.
When the voltage of the third capacitor C3 is charged to be higher than the second fixed voltage V2 and lower than the first fixed voltage V1, at this time, the second comparator COMP2 outputs a high level, the first comparator COMP1 outputs a low level, the high level output by the second comparator COMP2 is connected to one end of the second NAND gate NAND2, since the other end of the second NAND gate NAND2 is connected to the output end of the first NAND gate NAND1, the output level of the second NAND gate NAND2 is determined by the output level of the first NAND gate 1, and at the same time, the low level output by the first comparator COMP1 is converted to a high level through the NOT gate NOT1 and connected to one end of the first NAND gate 1, the output level of the first NAND gate 1 is determined by the output level of the second NAND gate 2, and if the last state of the first NAND gate 1 outputs a low level, the first power transistor M1 remains off and the voltage of the third capacitor C3 continues to rise.
When the voltage of the third capacitor C3 is higher than the first fixed voltage V1 and the second fixed voltage V2, the first comparator COMP1 and the second comparator COMP2 output a high level at the same time, the high level output by the first comparator COMP1 is converted into a low level through the NOT gate NOT1, the low level is connected to one end of the first NAND gate NAND1, at this time, the first NAND gate NAND1 outputs a high level regardless of the state of the second NAND gate NAND2, the first power transistor M1 is turned on, and the third capacitor C3 is rapidly discharged through the M1.
The first power transistor M1 is turned on to discharge the third capacitor C3, when the voltage of the third capacitor C3 is lowered to be lower than the first fixed voltage V1 but higher than the second fixed voltage V2, the second comparator COMP2 outputs a high level, the output level of the first NAND gate NAND1 is determined by the output level of the second NAND gate NAND2, and the two states are opposite and affect each other, so that the output of the first NAND gate 1 is maintained in the last output state, and the last state of the first NAND gate 1 outputs a high level, so that the first power transistor M1 is kept on, and the voltage of the third capacitor C3 continues to drop.
When the third capacitor C3 continues to discharge until the voltage is lower than the second fixed voltage V2, the first NAND gate NAND1 outputs a low level again, so that the first power transistor M1 is turned off, and the third capacitor C3 starts to charge again.
Repeating the above process, since the discharging time of the third capacitor C3 is very short and can be ignored with respect to the charging time, a periodic ramp wave is generated across the third capacitor C3, the amplitude of the periodic ramp wave is the first fixed voltage V1 minus the second fixed voltage V2, the peak of the voltage is V1, and the frequency formula is as follows:
in the above formula (1), IS1 IS the current of the constant current source IS1, C3 IS the capacitance of the third capacitor C3, V1 and V2 are the voltage values at V1 and V2, respectively, and the ramp wave generating circuit generates a ramp wave with a fixed frequency as shown in fig. 4.
According to the magnitude relation between the voltage of the third capacitor C3 and the first and second fixed voltages V1, V2, the level signals output by the first and second comparators COMP1, COMP2 can be controlled, so as to control the on/off of the first power tube M1, and control the voltage across the third capacitor C3, that is, control the second comparison voltage VB signal output by the ramp wave generating circuit 5002.
The square wave generating circuit 5003 includes a third comparator COMP3 for outputting a third comparison voltage VD and a fourth comparator COMP4 for outputting a fourth comparison voltage VC, a non-inverting input terminal of the third comparator COMP3 is connected to the first comparison voltage VA and an inverting input terminal thereof is connected to the second comparison voltage VB, an inverting input terminal of the fourth comparator COMP4 is connected to the second comparison voltage VB and a non-inverting input terminal thereof is connected to the third fixed voltage V3.
The square wave generating circuit 5003 is a conventional power chip circuit, the circuit and principle thereof are not described in detail, and the generated square wave is shown in fig. 5.
The logic processing unit circuit 5004 includes a fifth comparator COMP5 and a second logic gate circuit, an inverting input terminal of the fifth comparator COMP5 is connected to the first comparison voltage VA and a non-inverting input terminal thereof is connected to the third fixed voltage V3, and the second logic gate circuit is connected to output terminals of the fifth comparator COMP5, the third comparator COMP3 and the fourth comparator COMP4 and outputs a logic control voltage.
The second logic gate circuit comprises a second NOT gate NOT2, a first AND gate AND1 AND a second AND gate AND2, one end of the first AND gate AND1 is connected with the output end of the fifth comparator COMP5, the other end of the first AND gate AND 353525 is connected with the output end of the third comparator COMP3, the input end of the second NOT gate NOT2 is connected with the output end of the fifth comparator COMP5, the output end of the second AND gate AND2 is connected, the other end of the second AND gate AND2 is connected with the output end of the fourth comparator COMP4, AND the output ends of the first AND gate AND1 AND the second AND gate AND2 are connected with the OR gate OR1 AND output a logic control voltage VO signal.
The logic control voltage VO signal controls the logic driving circuit 600 in fig. 2 to control the state of the MOS switch M2 in the constant voltage control chip 1000, and when VO is at a high level, the second power transistor M2 is turned on, otherwise, M2 is turned off.
Comparing the voltage levels of the first comparison voltage VA AND the third fixed voltage V3, if the voltage level of the first comparison voltage VA is higher than the third fixed voltage V3, the fifth comparator COMP5 outputs a low level, the second NOT gate NOT2 outputs a high level, the first AND gate AND1 outputs a low level, the output level of the second AND gate AND2 is the same as the output level of the fourth comparison voltage VC, the output level of the OR gate OR1 is determined by the output level of the fourth comparison voltage VC, if the voltage level of VA is lower than V3, the fifth comparator COMP5 outputs a high level, the second NOT gate NOT2 outputs a low level, the second AND gate ADN2 outputs a low level, the output level of the first AND gate AND1 is the same as the output level of the third comparison voltage VD, AND the output level of the OR gate OR1 is determined by the output level of the third comparison voltage VD.
The first fixed voltage V1 is greater than the third fixed voltage V3, the third fixed voltage V3 is greater than the second fixed voltage V2, V1, V2, and V3 are preset reference voltages, the voltages of V1, V2, and V3 are provided by the internal voltage stabilizing circuit in fig. 2, the VFB pin is an external input pin, and VO is a logic output control pin, which provides a logic control level for the logic driving circuit 600 in fig. 2.
When the first comparison voltage VA is greater than the third fixed voltage V3, the signal of the logic control voltage VO is consistent with the signal of the fourth comparison voltage VC, and when the first comparison voltage VA is less than the third fixed voltage V3, the signal of the logic control voltage VO is consistent with the signal of the third comparison voltage VD.
When the power is turned on, the voltage of an input end, namely VDC, is established from low to high, and when the voltage of the input end, namely VDC, is higher than an internally set undervoltage locking value, the constant voltage control circuit starts to work; since the voltage of the first capacitor C1 is at a low level, the voltage of the first capacitor C1 is divided by the second voltage dividing resistor R2 and the first voltage dividing resistor R1, and the divided voltage is connected to the VFB pin of the constant voltage control chip 1000, the voltage at the VFB pin is at a low level; because the voltage of the VFB pin is relatively low, the first comparison voltage VA output by the error amplifier OP1 is a high level, and the voltage VA is higher than the voltage V3, referring to the circuit in the logic processing unit circuit 5004, when the voltage VA is higher than the voltage V3, the level of VO is consistent with the level of the fourth comparison voltage VC, and since VC is a square wave with a fixed duty cycle, VO is a square wave with a fixed duty cycle, the constant voltage control chip 1000 operates with a fixed duty cycle when it is powered on.
During the period that the second power tube M2 is turned on, the input end power VDC connected to the pin of the constant voltage control chip VIN charges and stores energy to the first inductor L1 and the energy storage capacitor COUT, and simultaneously supplies power to the load at the rear end, the first capacitor C1 discharges through the voltage dividing resistor, during the period that the second power tube M2 is turned off, the first inductor L1 charges the energy storage capacitor COUT through the schottky diode D1 and supplies power to the rear stage, and simultaneously the first inductor L1 charges the first capacitor C1 through the second diode D2, because the duty ratio is fixed when power is turned on and the duty ratio D = VOUT/VIN, the value of D is not changed, where VOUT is the output voltage and VIN is the VDC voltage, and as the establishment of the input voltage VIN is completed and the value of D is fixed, the output voltage (i.e., the voltage on the energy storage capacitor COUT) VOUT continues to rise.
During the turn-off period of the second power transistor M2, the first inductor L1 charges the energy storage capacitor COUT and the first capacitor C1, when the voltage of the energy storage capacitor COUT rises and the voltage across the first inductor L1 is clamped by the energy storage capacitor COUT, so that the voltage of the first capacitor C1 continues to rise, that is, the VFB voltage continues to rise, referring to the error amplification circuit 5001 in fig. 3, the VFB voltage continues to rise, so that the voltage VA at the output terminal VA of the error amplifier OP1 starts to fall, when the voltage VA falls below V3, referring to the logic processing unit circuit 5004, when the voltage VA is below V3, the level of VO is consistent with the level of the third comparison voltage VD, because the duty ratio of VD increases with the rise of the voltage VA and decreases with the fall of the voltage of the VA, the duty ratio VIN of VO further decreases, and since the input voltage is fixed, and D = VOUT/VOUT, as the duty cycle D decreases, the output voltage VOUT also decreases.
When VOUT is decreased to be lower than a predetermined value, that is, the voltage across the energy storage capacitor COUT is lower than a predetermined value, during the turn-off of the power transistor, the first inductor L1 charges the energy storage capacitor COUT and the first capacitor C1, and the voltage across the first inductor L1 is clamped by the energy storage capacitor COUT, because the voltage across the first capacitor C1 only supplies power to the two voltage dividing resistors, namely, the second voltage dividing resistor R2 and the first voltage dividing resistor R1, and the voltage across the first capacitor C1 does not suddenly decrease, the voltage across the first capacitor C1 is higher than the voltage across the energy storage capacitor COUT within several switching cycles, and therefore the first inductor L1 cannot charge the first capacitor C1 after the turn-off of the second power transistor M2.
Because the first capacitor C1 supplies power to the second divider resistor R2 and the first divider resistor R1, and the capacity of the first capacitor C1 is relatively small, the voltage of the first capacitor C1 will decrease quickly, that is, the VFB voltage decreases with reference to the error amplification circuit 5001, so that the voltage of the output end VA of the error amplifier increases, the duty ratio of the voltage VD of the output end of the third comparator COMP3 starts to increase, and the duty ratio of VO increases, that is, the duty ratio of the chip increases due to the existence of the logic processing unit circuit 5004; at this time, as the input voltage is unchanged, the duty ratio of the chip is increased, and according to the formula D = VOUT/VIN of the duty ratio, it can be known that the voltage at the output end (i.e., the voltage of the energy storage capacitor COUT) is increased, when the voltage of the energy storage capacitor COUT is increased to be higher than the voltage of the first capacitor C1, at this time, the first inductor L1 may charge the first capacitor C1 during the turn-off period of the power transistor, and when the voltage of the energy storage capacitor COUT is increased again to be higher than the set voltage value, the VA voltage is reduced, so that the duty ratio of VO is reduced, i.e., the duty ratio of the chip is reduced; after multiple cycles, when the energy storage capacitor COUT is stabilized to a set value, that is, the voltage VFB divided by the voltage of the first capacitor C1 through the second voltage dividing resistor R2 and the first voltage dividing resistor R1 can stabilize the VA voltage and does not change any more, that is, the duty ratio is also stable and unchanged; the voltage at the output end is stable and unchanged.
In the above embodiments, the first logic gate circuit and the second logic gate circuit may be designed alternatively as needed, as long as the output voltage signals are the same.
In some embodiments, according to the above embodiments, a person skilled in the art may perform inverse connection on the error amplifier OP1, the first comparator COMP1, the second comparator COMP2, the first logic gate circuit, the second logic gate circuit, the first fixed voltage V1, the second fixed voltage V2, the third fixed voltage V3, the second comparison voltage VB, the third comparison voltage VD, and the fourth comparison voltage VC, and adjust the voltage magnitude relationship between the first fixed voltage V1, the second fixed voltage V2, and the third fixed voltage V3, so as to achieve the same control effect and output the same voltage signal.
Referring to fig. 3 and fig. 2, a constant voltage control chip 1000 includes the constant voltage control circuit 500, the constant voltage control circuit 500 is connected to control a logic driving circuit 600, the logic driving circuit 600 is connected to control a second power transistor M2, when the logic driving circuit 600 outputs a high level, the second power transistor M2 is turned on, otherwise, the second power transistor M2 is turned off.
The constant voltage control chip 1000 further includes an internal voltage stabilizing circuit and reference source circuit 100, a soft start circuit 200, a low voltage protection circuit 300, and an overcurrent protection circuit 400.
The low voltage protection circuit 300 is used for detecting the voltage on the second capacitor C2 for supplying power to the inside, and when the voltage of C2 is lower than a set value, a signal is given to the logic driving circuit 600 to control the second power tube M2 to be turned off.
The over-current protection circuit 400 is used to detect the current value flowing through the internal second power transistor M2, and when the current value is greater than a set value, a signal is sent to the logic driving circuit 600 to control the second power transistor M2 to turn off.
The soft start circuit 200 is used to eliminate the surge current generated by the switching power supply at the start moment.
The logic driving circuit 600 is used to drive the second power transistor M2 to turn on and off, when the circuit outputs a high level, the second power transistor M2 turns on, and when the circuit outputs a low level, the second power transistor M2 turns off.
The VIN pin is the input of whole constant voltage control chip, and the VCC pin is the power supply pin of inside chip, does the inside whole logic circuit power supply of constant voltage control chip, this circuit work always provides stable VCC power for inside logic circuit.
The state of the second power tube M2 in the constant voltage control chip 1000 is controlled by the logic control voltage VO signal, and then the voltage of the VFB pin of the constant voltage control chip 1000 is controlled, and the charging and discharging circuit connected to the constant voltage control chip 1000 is controlled to work until the output voltage of the constant voltage control chip 1000 is stable.
In the above embodiment, the charge and discharge circuit includes a first diode, a second diode, a first inductor, a first capacitor, an energy storage capacitor, a first divider resistor and a second divider resistor, the VFB pin connects one end of the first divider resistor and the second divider resistor, the other end of the first divider resistor and the other end of the second divider resistor are respectively connected to two poles of the first capacitor, one pole of the first capacitor is connected to one end of the first inductor, the other pole is connected to the negative pole of the second diode, the other end of the first inductor is connected to the positive pole of the energy storage capacitor, the negative pole of the energy storage capacitor is connected to the positive pole of the first diode, the negative pole of the first diode is connected to the first inductor connection pin of the constant voltage control chip, and the two ends of the energy storage capacitor are further connected in parallel with the load resistor.
The charging and discharging circuit comprises a discharging circuit and a charging circuit, the first capacitor C1, the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 form a discharging loop, the energy-storage capacitor and the load resistor RL form a discharging loop, the first inductor L1, the first capacitor C1 and the second diode D2 form a charging loop, and the first inductor L1, the first diode D1 and the energy-storage capacitor COUT form a charging loop.
When the second power tube M2 is turned on, the input terminal power VDC connected to the VIN pin of the constant voltage control chip 1000 charges and stores energy to the first inductor L1 and the energy storage capacitor COUT, and simultaneously supplies power to the load at the rear end, and the first capacitor discharges through the first voltage dividing resistor and the second voltage dividing resistor; when the second power transistor M2 is turned off, the first inductor L1 charges the energy storage capacitor COUT through the first diode D1, and the first inductor L1 charges the first capacitor C1 through the second diode D2, and the energy storage capacitor COUT is discharged through the rear load resistor RL.
As an embodiment, the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 may be integrally packaged in the constant-voltage control chip 1000, or may be externally installed, or the second power transistor may be packaged or externally installed, or may be changed according to different implementation requirements.
Referring to fig. 1 and 3, a constant voltage control system includes the constant voltage control chip 1000, a VFB pin of the constant voltage control chip 1000 is connected to one ends of a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, the other ends of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are respectively connected to two poles of a first capacitor C1, one pole of the first capacitor C1 is connected to one end of a first inductor L1, the other pole of the first capacitor C1 is connected to a cathode of a second diode D2, the other end of the first inductor L1 is connected to an anode of a storage capacitor COUT, the cathode of the storage capacitor COUT is connected to an anode of a first diode D1, a cathode of the first diode D1 is connected to a first inductor L1 connection pin VSW of the constant voltage control chip 1000, and the first diode D1 is a base diode.
In addition, the input end power VDC is a direct current power supply, the anode of the input end power VDC is connected with the VIN pin of the constant voltage control chip 1000, the VCC pin of the constant voltage control chip 1000 is connected with a fourth resistor R4, the resistor of the fourth resistor R4 is 330K, the VSW pin is connected with a second capacitor C2, the other end of the second capacitor C2 is connected with the cathode of a third diode D3, the energy storage capacitor COUT is connected in parallel with a load resistor RL, and one end of the energy storage capacitor COUT is grounded GND.
The voltage of the external first capacitor C1 is divided to the VFB pin of the chip by the first voltage dividing resistor R1 and the second voltage dividing resistor R2, the voltage of the VFB pin and the internal reference voltage generate a first comparison voltage VA signal through the error amplifying circuit 5001, the third comparator COMP3 in the square wave generating circuit 5003 compares the first comparison voltage VA signal with the second comparison voltage VB signal generated by the ramp wave generating circuit 5002 to output a third comparison voltage VD signal whose duty ratio changes with the voltage change of the first comparison voltage VA, and the fourth comparator COMP4 in the square wave generating circuit 5003 compares the third fixed voltage V3 with the VB ramp wave signal generated by the ramp wave generating circuit 5002 to output a fourth comparison voltage VC signal whose duty ratio is fixed; the VA voltage is compared with the V3 voltage by the fifth comparator COMP5 in the logic processing unit circuit 5004 such that the output VO of the logic processing unit circuit 5004 coincides with the VC signal when the VA voltage is higher than the V3 voltage and the output VO of the logic processing unit circuit 5004 coincides with the VD signal when the VA voltage is lower than the V3 voltage.
When the voltage of the first capacitor C1 is lower immediately after power-on, and therefore the voltage of the VFB pin is lower, the voltage VA at the output terminal of the error amplifying circuit 5001 is at a high level, and the voltage of the VA is higher than the set voltage V3, so the VO signal output by the logic processing unit circuit 5004 is the constant duty ratio signal VC, and the constant voltage control chip 1000 operates at a constant duty ratio.
When the second power tube M2 is turned on, the input end power VDC charges the first inductor L1 and the energy storage capacitor COUT, and simultaneously supplies power to the rear-stage load, and when the power tube is turned off, the first inductor L1 charges the energy storage capacitor COUT and the first capacitor C1, and the voltage at the two ends of the first inductor L1 is clamped to the voltage at the two ends of the energy storage capacitor COUT, so that the voltage at the two ends of the first capacitor C1 is also clamped to the voltage at the two ends of the energy storage capacitor COUT.
As the voltage of the energy storage capacitor COUT rises, that is, the voltage of the first capacitor C1 rises, so that the VFB voltage rises, the voltage of VA drops due to the rise of the VFB voltage in the reference error amplifying circuit 5001, and when the voltage of VA drops below V3, the VO signal output by the logic processing unit circuit 5004 is the variable duty ratio signal VD. When the voltage of the input power VDC is fixed, the duty ratio of the constant voltage control chip 1000 is increased as the VA voltage is increased and decreased as the VA voltage is decreased.
If the voltage of the energy-storage capacitor COUT is higher than the set value, that is, the voltage of the first capacitor C1 is higher than the set value, the VFB voltage is higher than the VREF voltage, the VA voltage is decreased, so the duty ratio is decreased, and as the duty ratio D is decreased, and D = VOUT/VIN, VIN is the voltage of the input terminal VDC, since VIN is fixed, the VOUT voltage (i.e., the voltage of the energy-storage capacitor COUT) is decreased, and as the VOUT voltage (i.e., the voltage of the energy-storage capacitor COUT) is decreased, the voltage of the first capacitor C1 is decreased, that is, the VFB voltage is decreased, referring to the error amplifying circuit 5001 in fig. 3, the decrease of the VFB voltage increases the voltage of VA, as the VA voltage increases, the duty ratio increases, as the duty ratio D increases, and D = VOUT/VIN is fixed, and the VOUT voltage increases accordingly, after many cycles, when the voltage of the energy-storage capacitor COUT is stabilized to the set voltage value, that is, the VFB voltage divided by the voltage of the first capacitor C1 through the second voltage dividing resistor R2 and the first voltage dividing resistor R1 can stabilize the VA voltage and no longer change, that is, the output terminal voltage is stable and unchanged when the duty ratio is stable and unchanged.
If the voltage of the energy storage capacitor COUT is lower than the set value, that is, the voltage of the first capacitor C1 is lower than the set value, so the VFB voltage is lower than the VREF voltage, so the VA voltage increases, so the duty ratio increases, and as the duty ratio D increases, and D = VOUT/VIN, VIN is fixed, the VOUT voltage (that is, the voltage of the energy storage capacitor COUT capacitor) increases, and as the VOUT voltage increases, the voltage of the first capacitor C1 also increases, that is, the VFB voltage increases, the reference error amplifying circuit 5001, the voltage of VA decreases due to the increase of the VFB voltage, and as the VA voltage decreases, the duty ratio decreases, and as the duty ratio D decreases, and as D = VOUT/VIN, VIN is fixed, the VOUT voltage decreases, and after many cycles, when the voltage of the energy storage capacitor COUT is stabilized to the set voltage value, that is, the voltage of the first capacitor C1 is stabilized by the voltage divided by the second voltage divider resistor R2 and the first voltage divider resistor R1, so that the VFB voltage of the VA voltage does not change any more stably And when the duty ratio is stable and unchanged, the voltage of the output end is stable and unchanged.
In addition, in a steady state, during the period when the second power transistor M2 is turned off, the voltage of the first capacitor C1 is finally clamped to the voltage across the energy storage capacitor COUT, i.e., the VOUT voltage.
During the conduction period of the second power transistor M2, the first capacitor C1 discharges only through the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, the first capacitor C1, the second voltage-dividing resistor R2 and the first voltage-dividing resistor R1 form an RC discharge circuit, and the initial voltage value on the first capacitor C1 is VOUT, formula (2) of the RC discharge circuit:
wherein R1 and R2 are resistance values of the first divider resistor R1 and the second divider resistor R2, respectively, t is time, C1 is the capacity of the first capacitor C1, U isC1Is the voltage across the first capacitor C1, UOIs the initial voltage across the first capacitor C1, i.e., the VOUT voltage.
The switching frequency of the constant voltage control chip 1000 is about 100KHz under normal conditions, and the voltage of the first capacitor C1 is allowed to fluctuate by about 1%, i.e. the voltage of the first capacitor C1 is allowed to decrease to 0.99 times of U during the conduction period of the second power transistor M2OSince the value of (R1 + R2) × C1 is about 0.000995, the capacity of the external first capacitor C1 is usually set to about 33nF, and the sum of the resistances of the first divider resistor R1 and the second divider resistor R2 is set to about 30K Ω.
In a power-on state, the VO signal output by the constant voltage control circuit 500 is a constant duty ratio signal, at this time, a power chip connected to the constant voltage control circuit 500 operates at a constant duty ratio, when a power tube connected to the power chip is turned on, an input power VDC of the constant voltage control chip charges the first inductor L1 and the energy storage capacitor COUT, when the power tube is turned off, the first inductor L1 charges the energy storage capacitor COUT and the first capacitor C1, and simultaneously, the voltage on the first capacitor C1 is clamped to the voltage at two ends of the energy storage capacitor COUT.
The invention can achieve the effect of completely floating the ground, solves the problem that the power supply chip of the floating ground structure can not accurately control the output voltage, has simple internal circuit structure and greatly reduces the cost and the process requirement.
For those skilled in the art, the above embodiments are not described in detail, and can be understood from the accompanying drawings, which do not affect the implementation of the present invention.
In the above embodiments, the components of each circuit or module may be replaced by circuits or modules with the same function, and the circuit structure that realizes the same function may also be replaced by other known circuit structures, and the present invention is not described in detail.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A constant voltage control circuit comprises an error amplifier circuit, a ramp wave generating circuit, a square wave generating circuit and a logic processing unit circuit; it is characterized in that the preparation method is characterized in that,
the error amplifier circuit comprises an error amplifier, and the error amplifier receives a reference voltage and a voltage of a VFB pin of the constant voltage control chip and then outputs a first comparison voltage;
the ramp wave generating circuit comprises a first comparator, a second comparator and a first logic gate circuit connected with the output ends of the first comparator and the second comparator, the output end of the first logic gate circuit is connected with a grid of a first power tube connected with a third capacitor in parallel, the inverting input ends of the first comparator and the second comparator correspondingly receive a first fixed voltage and a second fixed voltage, the non-inverting input ends of the first comparator and the second comparator are connected with the drain electrode of the first power tube, and the first comparator and the second comparator detect the voltage of the third capacitor and then output a second comparison voltage;
the square wave generating circuit comprises a third comparator and a fourth comparator, wherein the non-inverting input end of the third comparator receives a first comparison voltage, the inverting input end of the third comparator receives a second comparison voltage and then outputs a third comparison voltage, and the inverting input end of the fourth comparator receives the second comparison voltage, and the non-inverting input end of the fourth comparator receives a third fixed voltage and then outputs a fourth comparison voltage;
the logic processing unit circuit receives the first comparison voltage, the third comparison voltage, the fourth comparison voltage and the third fixed voltage signal and then outputs a logic control voltage signal for controlling the on-off of an external second power tube, and the charge and discharge of an external energy storage capacitor are controlled through the on-off of the second power tube, so that constant voltage is realized.
2. The constant voltage control circuit according to claim 1, wherein the logic processing unit circuit includes a fifth comparator and a second logic gate circuit, wherein the non-inverting input terminal of the fifth comparator is connected to the third fixed voltage and the inverting input terminal of the fifth comparator is connected to the second logic gate circuit after receiving the first comparison voltage, and the second logic gate circuit is connected to the output terminals of the fifth comparator, the third comparator and the fourth comparator and outputs a logic control voltage signal through an or gate;
when the first comparison voltage is greater than the third fixed voltage, the logic control voltage signal is consistent with a fourth comparison voltage signal, and when the first comparison voltage is less than the third fixed voltage, the logic control voltage signal is consistent with a third comparison voltage signal;
wherein the first fixed voltage is greater than a third fixed voltage, which is greater than the second fixed voltage;
and when the logic control voltage signal is at a high level, the second power tube is switched on, otherwise, the second power tube is switched off.
3. The constant voltage control circuit of claim 1, wherein the first logic gate circuit comprises a first not gate, a first nand gate and a second nand gate, the output of the first comparator is connected to one input of the first nand gate after passing through the first not gate, the other input of the first nand gate is connected to the output of the second nand gate, the output of the first nand gate is connected to one input of the second nand gate, the output of the first nand gate is connected to the gate of the first power transistor, and the other input of the second nand gate is connected to the output of the second comparator;
the second logic gate circuit comprises a second NOT gate, a first AND gate, a second AND gate and an OR gate, the first AND gate is connected with the output end of the fifth comparator and the third comparison voltage, the second NOT gate is connected with the output end of the fifth comparator and then outputs to one input end of the second AND gate, the other input end of the second AND gate is connected with the fourth comparison voltage, and the OR gate is connected with the first AND gate and the second AND gate and then outputs a logic control voltage signal.
4. The constant voltage control circuit according to claim 2, wherein when the second power transistor is turned on, the constant voltage control chip charges a first inductor and an energy storage capacitor connected thereto through an input power supply; when the second power tube is turned off, the first inductor charges the energy storage capacitor through the first diode and charges the first capacitor through the second diode.
5. The constant voltage control circuit according to claim 4, wherein a charge and discharge circuit is connected to the constant voltage control chip, the charging and discharging circuit comprises a first diode, a second diode, a first inductor, a first capacitor, an energy storage capacitor, a first divider resistor and a second divider resistor, the VFB pin is connected with one ends of a first divider resistor and a second divider resistor, the other ends of the first divider resistor and the second divider resistor are respectively connected with two poles of a first capacitor, one pole of the first capacitor is connected to one end of the first inductor, the other pole of the first capacitor is connected to the cathode of the second diode, the other end of the first inductor is connected with the anode of the energy storage capacitor, the cathode of the energy storage capacitor is connected with the anode end of the first diode, the cathode end of the first diode is connected with the first inductor connecting pin of the constant voltage control chip, and the two ends of the energy storage capacitor are connected with the load resistor in parallel.
6. The constant voltage control circuit according to claim 5, wherein when the second power transistor is turned on, the first capacitor is discharged in a divided manner through the first voltage dividing resistor and the second voltage dividing resistor; and during the turn-off period of the second power tube, the energy storage capacitor is discharged through the rear-stage load.
7. The constant voltage control circuit according to claim 6, wherein when the voltage across the first capacitor is higher than the voltage across the energy storage capacitor, the first inductor no longer charges the first capacitor, the voltage across the first capacitor is divided by the voltage dividing resistor, and the voltage at the VFB pin is stabilized to stabilize the first comparison voltage, so that the output voltage of the constant voltage control chip is stabilized.
8. The constant voltage control circuit according to any one of claims 1 to 7, wherein the VFB pin voltage at the inverting input of the first comparator is controlled by switching the second power transistor on and off to adjust the output logic control voltage signal; when the second power tube is turned off, the voltage at two ends of the first capacitor connected with the VFB pin of the constant voltage control chip through the divider resistor is clamped to the voltage at two ends of the energy storage capacitor, namely the output voltage.
9. A constant voltage control chip, comprising the constant voltage control circuit of any one of claims 1 to 8, wherein the constant voltage control circuit is connected to control a logic driving circuit, and the logic driving circuit is connected to control the charging or discharging of an external charging and discharging circuit through a second power tube.
10. A constant voltage control system, characterized in that the constant voltage control system comprises the constant voltage control circuit of any one of claims 1 to 8 or the constant voltage control chip of claim 9.
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