CN117352389A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117352389A
CN117352389A CN202210745172.6A CN202210745172A CN117352389A CN 117352389 A CN117352389 A CN 117352389A CN 202210745172 A CN202210745172 A CN 202210745172A CN 117352389 A CN117352389 A CN 117352389A
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China
Prior art keywords
layer
work function
forming
etching
semiconductor structure
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陈卓凡
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210745172.6A priority Critical patent/CN117352389A/en
Publication of CN117352389A publication Critical patent/CN117352389A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a plurality of transistor areas; forming an etching stop layer on the substrate; forming a barrier layer on the surface of the etching stop layer, wherein the barrier layer exposes the etching stop layer on any transistor area; and performing a plurality of circulation processes until work function structures are respectively formed on each transistor region and the thicknesses of the work function structures are different, wherein each work function structure comprises a plurality of work function layers, and each circulation process comprises: forming a work function layer on the transistor areas, wherein the work function layer is positioned on the exposed surface of the etching stop layer; after forming the work function layer, patterning the barrier layer to expose the surface of the etch stop layer in any transistor region. The method for forming the semiconductor structure enables the threshold voltage of the transistor to be more stable, and improves the performance of the device.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure.
Background
As semiconductor device sizes continue to decrease, finfet devices are widely used in integrated circuit devices.
In the fabrication process of fin field effect transistors, work function metal (Work Function Metal, WFM) is typically formed on a high K dielectric layer, and the threshold voltage of the field effect transistor can be adjusted by adjusting the thickness of the work function metal layer.
Currently, an etching process is generally used to achieve thickness adjustment of the work function metal layer. However, in the prior art, during the etching process of adjusting the thickness of the work function metal layer, the work function metal layer is easily damaged excessively, thereby affecting the threshold voltage of the field effect transistor and further affecting the device performance.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which reduces the extra damage to the work function metal layer in the process of etching the work function metal layer, thereby stabilizing the threshold voltage of the field effect transistor and improving the performance of the device.
In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a plurality of transistor areas; forming an etching stop layer on the substrate; forming a barrier layer on the surface of the etching stop layer, wherein the barrier layer exposes the etching stop layer on any transistor area; and performing a plurality of circulation processes until work function structures are respectively formed on each transistor region and the thicknesses of the work function structures are different, wherein each work function structure comprises a plurality of work function layers, and each circulation process comprises: forming a work function layer on the transistor areas, wherein the work function layer is positioned on the exposed surface of the etching stop layer; after forming the work function layer, patterning the barrier layer to expose the surface of the etch stop layer in any transistor region.
Optionally, the number of the transistor areas is n+1, the number of the cyclic processes is N, and N is a natural number greater than 1; the work function structure comprises a plurality of work function layers, and the maximum number of the work function layers is N.
Optionally, the value range of N is 1-10.
Optionally, an ith work function layer is formed in the ith circulation process, the ith work function layer is positioned on the exposed surface of the etching stop layer and the surface of the ith-1 work function layer, the ith-1 work function layer is the work function layer formed in the ith-1 circulation process, and the value range of i is more than 1 and less than or equal to N.
Optionally, a first work function layer exposing a portion of the etch stop layer is formed in the 1 st cycle process.
Optionally, in the ith cyclic process, the method for patterning the barrier layer includes: forming a patterned layer on the ith work function layer, wherein the patterned layer is internally provided with a pattern opening exposing any transistor area, and the pattern opening is positioned on part of the barrier layer; and etching the first work function layer to the ith work function layer and the barrier layer by taking the patterned layer as a mask until the surface of the etching stop layer is exposed.
Optionally, the material of the barrier layer comprises amorphous silicon.
Optionally, the process of etching the first work function layer to the i-th work function layer is the same as the process of etching the barrier layer.
Optionally, the process of etching the barrier layer includes a wet etching process.
Optionally, the process parameters for etching the barrier layer include: the etching liquid comprises ammonia water.
Optionally, the material of the barrier layer includes silicon nitride.
Optionally, the process of etching the first work function layer to the i-th work function layer is different from the process of etching the barrier layer.
Optionally, the process parameters for etching the barrier layer include: the etching liquid comprises phosphoric acid; the process parameters for etching the first work function layer to the ith work function layer comprise: the etching liquid comprises ammonia water. Optionally, the method for forming the patterned layer includes: forming an initial patterning layer and a photoetching pattern layer positioned on the initial patterning layer on the ith work function layer, wherein the photoetching pattern layer is provided with a photoetching pattern opening exposing any transistor area, and the photoetching pattern opening is positioned on part of the barrier layer; and etching the initial patterning layer by taking the photoetching pattern layer as a mask until the surface of the ith work function layer is exposed, so as to form the patterning layer.
Optionally, the process of etching the initial patterned layer includes a dry etching process.
Optionally, the barrier layer has a thickness greater than 10 angstroms.
Optionally, the thickness of the ith work function layer ranges from 5 angstroms to 30 angstroms.
Optionally, before forming the etching stop layer, the method for forming the semiconductor structure further includes: and forming a gate dielectric layer on the substrate and an initial work function layer on the gate dielectric layer.
Optionally, the material of the initial work function layer comprises titanium nitride.
Optionally, the material of the etching stop layer comprises tantalum nitride; the material of the work function structure comprises titanium nitride.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure, the barrier layer is formed on the etching stop layer before the work function structure is formed, so that the barrier layer blocks the mutual diffusion between the work function layer and the etching stop layer in the subsequent process of forming the work function structure, the integrity of the etching stop layer is protected, the influence of the etching stop layer in the patterning process of the barrier layer is reduced, the thickness loss of the etching stop layer is reduced, the influence on the threshold voltage of a transistor device is reduced, and the device performance is ensured.
Further, when the material of the barrier layer is amorphous silicon, the process of etching the barrier layer is the same as the process of etching the work function layer, so that the etching of the barrier layer and the etching of the work function layer can be simultaneously completed by using the same process, thereby saving the process steps.
Drawings
Fig. 1 to 3 are schematic cross-sectional views illustrating a process of forming a semiconductor structure;
fig. 4 to 14 are schematic cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background art, in the existing etching process for adjusting the thickness of the work function metal layer, the work function metal layer is easily damaged excessively, so that the threshold voltage of the field effect transistor is affected, and the device performance is further affected.
Fig. 1-3 are cross-sectional views of a semiconductor structure formation process.
Referring to fig. 1, a substrate 100 is provided; an initial work function layer 101 is formed on the substrate 100, an etch stop layer 102 is formed on the initial work function layer 101, a work function structure 103 is formed on the etch stop layer 102, and an initial patterning layer 104 is formed on the work function structure 103.
Specifically, the material of the etching stop layer 102 includes tantalum nitride; the material of the work function structure 103 comprises titanium nitride.
Referring to fig. 2, the initial patterned layer 104 is etched to form a via 105 and a patterned layer 106, wherein the via 105 exposes a portion of the work function structure 103.
The method of etching the initial patterned layer 104 includes a dry etching process.
Referring to fig. 3, the work function structure 103 is etched using the patterned layer 106 as a mask.
During the etching process of the initial patterned layer 104, the etching process aggravates the diffusion between the etching stop layer 102 and the work function structure 103, so that the etching stop layer 102 is also greatly damaged while the work function structure 103 is etched later, so that the thickness of the etching stop layer 102 is reduced, thereby influencing the threshold voltage of the transistor and influencing the device performance.
In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, wherein a blocking layer is formed on an etching stop layer before forming a work function structure, so that the blocking layer blocks the interdiffusion between the work function layer and the etching stop layer in the subsequent process of forming the work function structure, thereby protecting the etching stop layer, reducing the thickness loss of the etching stop layer after forming the work function structure, reducing the influence on the threshold voltage of a transistor, and ensuring the performance of a device.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 14 are schematic cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 201 is provided, the substrate 201 including a plurality of transistor regions.
The transistor devices are arranged in the transistor areas, and the required operating voltages of the transistor devices in the transistor areas are different. Work function structures with different thicknesses are formed on the transistor areas, so that the work function structures can meet the working voltage required by the transistor devices on the transistor areas.
In this embodiment, the number of the transistor areas is 6, and the transistor areas are respectively a first transistor area I, and a PFET ultra-low voltage threshold device (pulsut) is arranged in the first transistor area I; a second transistor region II having a PFET low voltage threshold device (PLVT) therein; a third transistor region III having a PFET standard voltage threshold device (PSVT) therein; a fourth transistor region IV having an NFET standard voltage threshold device (NSVT) therein; a fifth transistor region V having an NFET low voltage threshold device (NLVT) therein; a sixth transistor region VI; and an NFET ultra low voltage threshold device (NULVT) is arranged in the sixth transistor region VI. Therefore, the thicknesses of the functional structures required in the first transistor area I to the sixth transistor area VI are sequentially decreased to meet the operating voltage requirement of the transistor devices in each transistor area.
The material of the substrate 201 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like. Specifically, in this embodiment, the material of the substrate 201 is silicon.
Referring to fig. 5, a gate dielectric layer (not shown) on the substrate 201 and an initial work function layer 202 on the gate dielectric layer are formed; forming an etch stop layer 203 on the initial work function layer 202; a barrier layer 204 is formed on the surface of the etching stop layer 203, and the barrier layer 204 exposes the etching stop layer 203 on any transistor region.
The etch stop layer 203 serves as a stop layer for the etching process during subsequent formation of the work function structure.
The barrier layer 204 has the function of blocking the mutual diffusion between the work function layer subsequently formed on the barrier layer 204 and the etching stop layer 203, and protecting the integrity of the etching stop layer 203, thereby reducing the influence of the etching process on the etching stop layer 203 and reducing the thickness loss of the etching stop layer 203 in the subsequent etching of the work function layer and the barrier layer 204.
In this embodiment, the work function layer subsequently formed on the first transistor area I does not need to be etched, and the etching stop layer 203 on the first transistor area I does not need to be protected by the barrier layer 204, so that the barrier layer 204 exposes the etching stop layer 203 on the first transistor area I.
In this embodiment, the thickness of the blocking layer 204 is greater than 10 angstroms, so that the blocking layer 204 can better block the interdiffusion between the work function layer formed later and the etching stop layer 203.
The method for forming the barrier layer 204 includes: depositing an initial barrier layer (not shown) on the etch stop layer 203; the initial barrier layer is etched until the etch stop layer 203 on the first transistor region I is exposed to form a barrier layer 204.
In this embodiment, the material of the barrier layer 204 comprises amorphous silicon. The process of depositing the initial barrier layer includes an atomic layer deposition process.
In another embodiment, the material of the barrier layer comprises silicon nitride.
In this embodiment, the material of the etching stop layer 203 includes tantalum nitride.
In this embodiment, the material of the initial work function layer 202 includes titanium nitride.
After the barrier layer 204 is formed, a plurality of circulation processes are performed until work function structures are formed on each transistor region, respectively, and the thicknesses of the work function structures are different, wherein the work function structures comprise a plurality of work function layers, and each circulation process comprises: forming a work function layer on the transistor areas, wherein the work function layer is positioned on the exposed surface of the etching stop layer 203; after forming the work function layer, the barrier layer 204 is patterned to expose the surface of the etch stop layer 203 in any transistor region.
Specifically, the number of the cyclic processes is N, the number of the transistor areas is n+1, and N is a natural number greater than 1; the work function structure comprises a plurality of work function layers, and the maximum number of the work function layers is N.
Wherein a first work function layer exposing a portion of the etch stop layer is formed in the 1 st cycle process.
And forming an ith work function layer in the ith circulating process, wherein the ith work function layer is positioned on the exposed surface of the etching stop layer and the surface of the ith-1 layer work function layer, the ith-1 layer work function layer is the work function layer formed in the ith-1 circulating process, and the value range of i is more than 1 and less than or equal to N.
In this embodiment, the number of the cyclic processes is 5. The maximum number of layers of the work function layer included in the formed work function structure is 5.
Specifically, the process of forming the work function structure is shown in fig. 6 to 14.
First, a 1 st cycle process is performed to form a first work function layer 211 exposing a portion of the etch stop layer 203. Specifically, the process of performing the 1 st cycle is shown in fig. 6 to 9.
Referring to fig. 6, a first work function layer 211 is formed on each transistor region.
The first work function layer 211 is located on the surface of the etching stop layer 203 in the first transistor area I, and is also located on the surface of the blocking layer 204 in the second transistor area II, the third transistor area III, the fourth transistor area IV, the fifth transistor area V, and the sixth transistor area VI.
In this embodiment, the material of the first work function layer 211 includes titanium nitride.
The thickness of the first work function layer 211 ranges from 5 angstroms to 30 angstroms. The forming process of the first work function layer 211 includes an atomic layer deposition process.
Referring to fig. 7, an initial patterned layer 220 and a photoresist layer 221 on the initial patterned layer 220 are formed on the first work function layer 211, wherein the photoresist layer 221 has a photoresist opening (not shown) exposing the second transistor region II, and the photoresist opening is located on a portion of the barrier layer 204.
The initial patterned layer 220 is subsequently patterned to form patterned layer 222, which serves as a mask for etching the first work function layer 211 as well as the barrier layer 204.
In this embodiment, the initial patterning layer 220 includes an anti-reflection layer (not shown) and a low temperature oxide layer (not shown) on the anti-reflection layer.
The photolithographic patterning layer 221 is subsequently used as a mask to etch the initial patterning layer 220, thereby transferring the photolithographic pattern to the initial patterning layer 220 to form a patterned layer.
With continued reference to fig. 8, the initial patterned layer 220 is etched using the photolithographic patterned layer 221 as a mask until the surface of the first work function layer 211 is exposed to form the patterned layer 222.
The patterned layer 222 has a patterned opening (not shown) exposing the second transistor region II, and the patterned opening is located on a portion of the barrier layer 204.
In this embodiment, the process of etching the initial patterned layer 220 includes a dry etching process.
In the process of etching the initial patterned layer 220, the temperature of the surface of the semiconductor structure is increased, and due to the existence of the barrier layer 204 between the first work function layer 211 and the etching stop layer 203, the diffusion aggravation condition caused by the temperature change between the first work function layer 211 and the etching stop layer 203 is reduced, so that the integrity of the etching stop layer 203 is protected, the influence of the subsequent process of etching the first work function layer 211 and the barrier layer 204 on the etching stop layer 203 is reduced, and the thickness damage to the etching stop layer 203 is reduced.
Referring to fig. 9, the first work function layer 211 and the barrier layer 204 are etched using the patterned layer 222 as a mask until the surface of the etching stop layer 203 is exposed.
Specifically, the first work function layer 211 and the barrier layer 204 have openings (not shown) therein, and the openings expose the surface of the etching stop layer 203 on the second transistor region II.
The effect of etching the first work function layer 211 is to remove the first work function layer 211 on the second transistor region II on the basis of maintaining the first work function layer 211 on the first transistor region I, so that the thicknesses of the work function structures on the first transistor region I and the second transistor region II are different after a plurality of work function layers on the first work function layer 211 are formed subsequently.
Since the diffusion degree between the first work function layer 211 and the etching stop layer 203 is smaller, the etching process has less influence on the etching stop layer 203 in the process of etching the first work function layer 211 and the barrier layer 204, thereby reducing the thickness damage to the etching stop layer 203.
In this embodiment, the material of the barrier layer 204 comprises amorphous silicon; the material of the first work function layer 211 includes titanium nitride; the process of etching the first work function layer 211 is the same as the process of etching the barrier layer 204. Since the first work function layer 211 and the barrier layer 204 can be etched simultaneously by the same etching process, the steps of the etching process are saved.
Specifically, the process of etching the barrier layer 204 and the first work function layer 211 includes a wet etching process. The parameters of the wet etching process include: the etching liquid comprises ammonia water.
In another embodiment, the material of the barrier layer comprises amorphous silicon; the material of the first work function layer comprises titanium nitride. The process of etching the barrier layer and the first work function layer includes a dry etching process.
In another embodiment, the material of the barrier layer comprises silicon nitride; the material of the first work function layer comprises titanium nitride. The process of etching the first work function layer is different from the process of etching the barrier layer.
Specifically, after etching the first work function layer, etching the barrier layer. Wherein, the process of etching the first work function layer comprises a wet etching process; the wet etching process parameters comprise: the etching liquid comprises ammonia water. The process of etching the barrier layer comprises a wet etching process; the wet etching process parameters comprise: the etching liquid used comprises phosphoric acid.
Fig. 10 and 11 are schematic cross-sectional structures of the 2 nd cycle process.
Referring to fig. 10, a second work function layer 212 is formed on the surface of the first work function layer 211, and the second work function layer 212 is further located on the exposed surface of the etching stop layer 203.
Specifically, the second work function layer 212 is located on the surface of the first work function layer 211 on the first transistor area I and the surface of the etching stop layer 203 on the second transistor area II. Therefore, the first transistor area I has the first work function layer 211 and the second work function layer 212 thereon, and the second transistor area II has only the second work function layer 212 thereon, so that the overall thickness of the work function layer on the first transistor area I is greater than that on the second transistor area II.
In this embodiment, the second work function layer 212 is further located on the surface of the first work function layer 211 of the third transistor area III, the fourth transistor area IV, the fifth transistor area V, and the sixth transistor area VI.
In this embodiment, the material of the second work function layer 212 includes titanium nitride.
Referring to fig. 11, the first work function layer 211, the second work function layer 212 and the barrier layer 204 are patterned to expose the surface of the etching stop layer 203 in the third transistor region III.
Specifically, the method for patterning the first work function layer 211, the second work function layer 212, and the barrier layer 204 includes: forming a patterned layer (not shown) on the second work function layer 212, wherein the patterned layer has a pattern opening (not shown) exposing the third transistor region III, and the pattern opening is located on a portion of the barrier layer 204; and etching the first work function layer 211, the second work function layer 212 and the barrier layer 204 by using the patterned layer as a mask until the surface of the etching stop layer 203 is exposed.
Since the material of the first work function layer 211 and the material of the second work function layer 212 include titanium nitride, the process of etching the first work function layer 211, the second work function layer 212 and the barrier layer 204 is the same as the process of etching the first work function layer 211 and the barrier layer 204 in fig. 9, and will not be described here.
Fig. 12 to 14 are schematic cross-sectional structures of the 3 rd to 5 th cycle processes, respectively.
Referring to fig. 12, a 3 rd cycle process is performed, which includes: forming a third work function layer 213 on each transistor region, wherein the third work function layer 213 is located on the second work function layer 212 and the exposed surface of the etching stop layer 203; after forming the third work function layer 213, the first to third work function layers 211 to 213 and the barrier layer 204 are patterned to expose the surface of the etch stop layer 203 of the fourth transistor region IV.
Specifically, the method for patterning the first work function layer 211 to the third work function layer 213 and the barrier layer 204 includes: forming a patterned layer (not shown) on the third work function layer 213, wherein the patterned layer has a pattern opening exposing the fourth transistor region IV, and the pattern opening is located on a portion of the barrier layer 204; and etching the first work function layer 211 to the third work function layer 213 and the barrier layer 204 by using the patterned layer as a mask until the surface of the etching stop layer 203 is exposed.
Further, the method of forming the patterned layer includes: forming an initial patterning layer (not shown) having a photolithography pattern opening exposing the fourth transistor region IV on a portion of the barrier layer 204, and a photolithography pattern layer (not shown) on the initial patterning layer on the third work function layer 213; and etching the initial patterning layer by using the photoetching pattern layer as a mask until the surface of the third work function layer 213 is exposed, so as to form the patterning layer.
Referring to fig. 13, a 4 th cycle process is performed, the cycle process including: forming a fourth work function layer 214 on each transistor region, wherein the fourth work function layer 214 is located on the third work function layer 213 and the exposed surface of the etching stop layer 203; after the fourth work function layer 214 is formed, the first to fourth work function layers 211 to 214 and the barrier layer 204 are patterned to expose the surface of the etching stop layer 203 of the fifth transistor region V.
The method for patterning the first to fourth work function layers 211 to 214 and the barrier layer 204 is the same as the method for patterning the first to third work function layers 211 to 213 and the barrier layer 204 in fig. 12, and will not be described herein.
Referring to fig. 14, a 5 th cycle process is performed, the cycle process including: forming a fifth work function layer 215 on each transistor region, wherein the fifth work function layer 215 is positioned on the surfaces of the fourth work function layer 214 and the exposed etching stop layer 203; after the fifth work function layer 215 is formed, the first to fifth work function layers 211 to 215 and the barrier layer 204 are patterned to expose the surface of the etch stop layer 203 of the sixth transistor region VI.
In this embodiment, the method for patterning the first to fifth work function layers 211 to 215 and the barrier layer 204 is the same as the method for patterning the first to third work function layers 211 to 213 and the barrier layer 204 in fig. 12, and is not repeated here.
The first work function layer 211 to the fifth work function layer 215 together form a work function structure (not shown) on the etching stop layer 203, and the thickness of the work function structure is different from one transistor region to another.
By performing the 5-cycle process, work function structures with different thicknesses are formed on the first transistor region I to the sixth transistor region VI, respectively, so as to satisfy different operating voltages required by the transistor devices on the first transistor region I to the sixth transistor region VI.
Specifically, the number of layers of the work function layers on the first transistor region I to the sixth transistor region VI is gradually decreased, and the first transistor region I has the first layer work function layer 211 to the fifth layer work function layer 215, so that the first transistor region I has the maximum thickness of the work function structure, and the sixth transistor region VI does not have any work function layer, so that the surface of the etching stop layer 203 is exposed.
During each cycle, the existence of the barrier layer 204 on the etching stop layer 203 blocks the interdiffusion between each work function layer and the etching stop layer 203, thereby protecting the integrity of the etching stop layer 203. Therefore, in the process of patterning each work function layer and the barrier layer 204, the process of etching each work function layer and the barrier layer 204 has less influence on the etching stop layer 203 under the barrier layer 204, so that the thickness damage to the etching stop layer 203 is reduced, and the influence on the threshold voltage of the transistor device is reduced, and the device performance is ensured.
In this embodiment, the thickness of each work function layer ranges from 5 angstroms to 30 angstroms.
In this embodiment, the materials of each work function layer include titanium nitride, i.e., the materials of the work function structure include titanium nitride.
In other embodiments, the number of cycles is 1 to 10.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of transistor areas;
forming an etching stop layer on the substrate;
forming a barrier layer on the surface of the etching stop layer, wherein the barrier layer exposes the etching stop layer on any transistor area;
and performing a plurality of circulation processes until work function structures are respectively formed on each transistor region and the thicknesses of the work function structures are different, wherein each work function structure comprises a plurality of work function layers, and each circulation process comprises: forming a work function layer on the transistor areas, wherein the work function layer is positioned on the exposed surface of the etching stop layer; after forming the work function layer, patterning the barrier layer to expose the surface of the etch stop layer in any transistor region.
2. The method of claim 1, wherein the number of transistor regions is n+1, the number of cyclic processes is N, and N is a natural number greater than 1; the work function structure comprises a plurality of work function layers, and the maximum number of the work function layers is N.
3. The method of forming a semiconductor structure of claim 2, wherein N has a value in the range of 1 to 10.
4. The method of forming a semiconductor structure as claimed in claim 2, wherein an i-th work function layer is formed in the i-th cycle process, the i-th work function layer being located on the exposed surface of the etch stop layer and the i-1-th work function layer, the i-1-th work function layer being the work function layer formed in the i-1-th cycle process, the i having a value in a range of 1 < i.ltoreq.N.
5. The method of forming a semiconductor structure of claim 4, wherein a first work function layer exposing a portion of the etch stop layer is formed in a 1 st cycle process.
6. The method of forming a semiconductor structure of claim 5, wherein, in the ith cycle of processing, the method of patterning the barrier layer comprises: forming a patterned layer on the ith work function layer, wherein the patterned layer is internally provided with a pattern opening exposing any transistor area, and the pattern opening is positioned on part of the barrier layer; and etching the first work function layer to the ith work function layer and the barrier layer by taking the patterned layer as a mask until the surface of the etching stop layer is exposed.
7. The method of forming a semiconductor structure of claim 6, wherein the material of the barrier layer comprises amorphous silicon.
8. The method of claim 7, wherein the process of etching the first work function layer to the i-th work function layer is the same as the process of etching the barrier layer.
9. The method of forming a semiconductor structure of claim 8, wherein the process of etching the barrier layer comprises a wet etching process.
10. The method of forming a semiconductor structure of claim 9, wherein etching the barrier layer comprises: the etching liquid comprises ammonia water.
11. The method of forming a semiconductor structure of claim 6, wherein the material of the barrier layer comprises silicon nitride.
12. The method of claim 11, wherein the process of etching the first work function layer to the i-th work function layer is different from the process of etching the barrier layer.
13. The method of forming a semiconductor structure of claim 12, wherein etching the barrier layer comprises: the etching liquid comprises phosphoric acid; the process parameters for etching the first work function layer to the ith work function layer comprise: the etching liquid comprises ammonia water.
14. The method of forming a semiconductor structure of claim 6, wherein the method of forming the patterned layer comprises: forming an initial patterning layer and a photoetching pattern layer positioned on the initial patterning layer on the ith work function layer, wherein the photoetching pattern layer is provided with a photoetching pattern opening exposing any transistor area, and the photoetching pattern opening is positioned on part of the barrier layer; and etching the initial patterning layer by taking the photoetching pattern layer as a mask until the surface of the ith work function layer is exposed, so as to form the patterning layer.
15. The method of forming a semiconductor structure of claim 14, wherein the process of etching the initial patterned layer comprises a dry etching process.
16. The method of forming a semiconductor structure of claim 1, wherein the barrier layer has a thickness greater than 10 angstroms.
17. The method of forming a semiconductor structure of claim 4, wherein the i-th work function layer has a thickness in the range of 5 angstroms to 30 angstroms.
18. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the etch stop layer: and forming a gate dielectric layer on the substrate and an initial work function layer on the gate dielectric layer.
19. The method of forming a semiconductor structure of claim 18, wherein the material of the initial work function layer comprises titanium nitride.
20. The method of forming a semiconductor structure of claim 1, wherein the material of the etch stop layer comprises tantalum nitride; the material of the work function structure comprises titanium nitride.
CN202210745172.6A 2022-06-28 2022-06-28 Method for forming semiconductor structure Pending CN117352389A (en)

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