CN117174655A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a plurality of first transistor areas and at least one second transistor area; forming an etching stop layer on each first transistor area and each second transistor area, wherein the thickness of the etching stop layer on each second transistor area is larger than that of the etching stop layer on each first transistor area; and performing a plurality of cyclic deposition etching processes on the first transistor area and the second transistor area until work function structures are respectively formed on the first transistor areas and the second transistor areas, wherein the work function structures have different thicknesses and comprise a plurality of work function layers, each cyclic deposition etching process comprises a deposition step and a patterning step after the deposition step, and the number of times of the patterning steps performed on the second transistor area is more than that performed on the first transistor area. The method for forming the semiconductor structure enables the threshold voltage of the transistor to be more stable, and further improves the performance of the device.

Description

Method for forming semiconductor structure

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure.

Background

As semiconductor device sizes continue to decrease, finfet devices are widely used in integrated circuit devices.

In the fabrication process of fin field effect transistors, work function metals (Work Function Metal, WFM) are typically formed on high K dielectric layers, and by adjusting the thickness of the work function metal layer, the threshold voltage of the field effect transistor can be adjusted.

Currently, multiple etching processes are typically employed to achieve thickness adjustment of work function metal layers on different transistors. However, in the prior art, in the etching process for adjusting the thickness of the work function metal layer, the number of times of etching the work function metal layer on each transistor is different, so that the work function metal layer on a part of the transistors is easy to be excessively damaged, thereby affecting the stability of the threshold voltage of the field effect transistor and further affecting the performance of the device.

Disclosure of Invention

The invention solves the technical problem of providing a method for forming a semiconductor structure, which reduces the extra damage to the work function metal layer in the process of etching the work function metal layer, thereby stabilizing the threshold voltage of the field effect transistor and improving the performance of the device.

In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a plurality of first transistor areas and at least one second transistor area; forming an etching stop layer on each first transistor area and each second transistor area, wherein the thickness of the etching stop layer on each second transistor area is larger than that of the etching stop layer on each first transistor area; after forming the etching stop layer, performing a plurality of cyclic deposition etching processes on the first transistor area and the second transistor area until work function structures are respectively formed on the first transistor areas and the second transistor areas, wherein the work function structures have different thicknesses and comprise a plurality of work function layers, each cyclic deposition etching process comprises a deposition step and a patterning step after the deposition step, the number of patterning steps performed on the second transistor area is more than that performed on the first transistor area, and each cyclic deposition etching process comprises: depositing on each first transistor area and each second transistor area to form an initial work function layer; patterning the initial work function layer to expose the surface of any one of the first transistor regions, any one of the second transistor regions, or the etching stop layer of any one of the first transistor regions and at least one of the second transistor regions, so as to form a work function layer.

Optionally, the sum of the number of the first transistor areas and the number of the second transistor areas is n+1, the number of the cyclic deposition etching processes is N, and N is a natural number greater than or equal to 2; the work function structure comprises a plurality of work function layers, and the maximum number of layers of the work function layers is N.

Optionally, a first work function layer exposing a portion of the etch stop layer is formed in a 1 st cycle deposition etch process.

Optionally, in the deposition step of the ith cyclic deposition etching process, depositing and forming an ith initial work function layer, wherein the ith initial work function layer is positioned on the exposed surface of the etching stop layer and the surface of the i-1 th work function layer; in the patterning step of the ith cyclic deposition etching process, patterning the ith layer initial work function layer to form an ith layer work function layer; the i-1 th work function layer is a work function layer formed in the i-1 st cyclic deposition etching process, and the value range of i is more than 1 and less than or equal to N.

Optionally, in the ith cyclic deposition etching process, the method for patterning the ith initial work function layer includes: forming a patterned layer on the i-th layer initial work function layer, wherein the patterned layer is internally provided with a pattern opening exposing the i-th layer initial work function layer on any one of the first transistor area and any one of the second transistor area; and etching the first layer work function layer to the i layer initial work function layer by taking the patterned layer as a mask until the surface of the etching stop layer is exposed, wherein the i layer initial work function layer becomes the i layer work function layer.

Optionally, in the ith cyclic deposition etching process, the method for patterning the ith initial work function layer includes: forming a patterned layer on the i-th layer initial work function layer, wherein the patterned layer is internally provided with a pattern opening exposing the i-th layer initial work function layer on any one of the first transistor area and at least one of the second transistor areas; and etching the first layer work function layer to the i layer initial work function layer by taking the patterned layer as a mask until the surface of the etching stop layer is exposed, wherein the i layer initial work function layer becomes the i layer work function layer.

Optionally, the value range of N is 2-10.

Optionally, the process of etching the first layer work function layer to the i-th layer initial work function layer includes a wet etching process.

Optionally, the etching stop layer includes: a first etch stop layer on the second transistor region, and a second etch stop layer on the first and second transistor regions.

Optionally, the method for forming the etching stop layer includes: forming an initial first etch stop layer on the first transistor region and the second transistor region; removing the initial first etching stop layer on the first transistor area to form a first etching stop layer on the second transistor area; and forming a second etching stop layer on the first etching stop layer of the first transistor area and the second transistor area.

Optionally, the process of removing the initial first etch stop layer on the first transistor region includes a dry etching process.

Optionally, the difference between the thickness of the etching stop layer on the second transistor area and the thickness of the etching stop layer on the first transistor area is a first difference, the difference between the number of patterning steps performed on the second transistor area and the number of patterning steps performed on the first transistor area is a second difference, and the first difference and the second difference are positively correlated.

Optionally, the second difference is equal to 1; the first difference is in the range of 5 angstroms to 20 angstroms.

Optionally, the material of the etching stop layer comprises tantalum nitride; the material of the work function structure comprises titanium nitride.

Optionally, before forming the etching stop layer, the method for forming the semiconductor structure further includes: and forming a gate dielectric layer on the substrate and a bottom work function layer on the gate dielectric layer.

Optionally, the material of the bottom work function layer comprises titanium nitride.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the method for forming a semiconductor structure provided by the technical scheme of the invention, the number of patterning steps performed on each second transistor region is greater than that performed on each first transistor region, so that the thickness damage of the etching stop layer on the second transistor region is greater than that of the etching stop layer on the first transistor region. Because the thickness of the formed etching stop layer on the second transistor area is larger than that of the formed etching stop layer on the first transistor area, the thickness difference between the second transistor area and the etching stop layer on the first transistor area can compensate the extra thickness damage to the etching stop layer on the second transistor area, thereby compensating the thickness loss of the etching stop layer on the second transistor area, ensuring that the thickness of the etching stop layer is more uniform, improving the stability of the threshold voltage of the device and improving the performance of the device.

Drawings

Fig. 1 to 12 are schematic cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As described in the background, in the prior art, multiple etching processes are typically used to achieve thickness adjustment of work function metal layers on different transistors. However, in the etching process for adjusting the thickness of the work function metal layer, the number of times of etching the work function metal layer on each transistor is different, so that the work function metal layer on part of the transistors is easy to be excessively damaged, thereby affecting the stability of the threshold voltage of the field effect transistor and further affecting the performance of the device.

In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, which enables the thickness of an etching stop layer formed on a second transistor area to be larger than that of an etching stop layer formed on a first transistor area, wherein the thickness difference of the etching stop layer on the second transistor area and the etching stop layer on the first transistor area can compensate the extra thickness damage suffered by the etching stop layer on the second transistor area, thereby compensating the thickness loss of the etching stop layer on the second transistor area, enabling the thickness of the etching stop layer to be more uniform, improving the stability of the threshold voltage of a device and improving the performance of the device.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 to 12 are schematic cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 1 and 2, fig. 2 is an enlarged partial cross-sectional view of regions a, B, c, d, e and f in fig. 1, providing a substrate 201, wherein the substrate 201 includes a plurality of first transistor regions a and at least one second transistor region B.

In this embodiment, the substrate 201 includes a number of discrete fin structures (not shown). The material of the substrate 201 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like. Specifically, in this embodiment, the material of the substrate 201 is silicon.

And in the process of forming the work function structure subsequently, performing a plurality of cyclic deposition etching processes on the first transistor area A and the second transistor area B, wherein each cyclic deposition etching process comprises a deposition step and a patterning step after the deposition step, and the number of times of the patterning step performed on the second transistor area B is more than that performed on the first transistor area A.

In this embodiment, the transistor devices are disposed in the first transistor region a and the second transistor region B, and the required operating voltages of the transistor devices in the transistor regions are different. Work function structures with different thicknesses are formed on the first transistor areas A and the second transistor areas B, so that the work voltages required by the transistor devices on the transistor areas are respectively met.

Specifically, the number of the first transistor areas a is 4, which are respectively denoted as: a first sub-transistor region I having a PFET ultra-low voltage threshold device (pulsvt) therein; a second sub-transistor region II having a PFET low voltage threshold device (PLVT) therein; a third sub-transistor region III having a PFET standard voltage threshold device (PSVT) therein; and a fourth sub-transistor region IV having an NFET standard voltage threshold device (NSVT) therein. The number of the second transistor areas B is 2, and they are respectively recorded as: a fifth sub-transistor region V having an NFET low voltage threshold device (NLVT) therein; and a sixth sub-transistor region VI having an NFET ultra low voltage threshold device (NULVT) therein. The thicknesses of the power function structures required in the first to sixth sub-transistor areas I to VI decrease in order to meet different operating voltage requirements of the transistor devices in each sub-transistor area.

With continued reference to fig. 1 and 2, a gate dielectric layer (not shown) is formed on the substrate 201, and a bottom work function layer 202 is formed on the gate dielectric layer.

In this embodiment, the material of the bottom work function layer 202 comprises titanium nitride.

And forming an etching stop layer on each first transistor area A and each second transistor area B, wherein the thickness of the etching stop layer on each second transistor area B is larger than that of each first transistor area A.

In this embodiment, the etching stop layer includes: a first etch stop layer on the second transistor region B, and a second etch stop layer on the first and second transistor regions a and B.

In this embodiment, detailed steps of forming an etching stop layer are shown in fig. 2 to 3.

Referring to fig. 3, a first etching stop layer 203 is formed on the second transistor region B.

The first etching stop layer 203 is only located on the second transistor region B, so that after the second etching stop layer is formed later, the thickness of the overall etching stop layer on the second transistor region B is greater than that on the first transistor region a.

Specifically, the method for forming the first etching stop layer 203 includes: forming an initial first etch stop layer (not shown) on the first and second transistor areas a and B; the initial first etch stop layer on the first transistor region a is removed to form a first etch stop layer 203 on the second transistor region B.

In this embodiment, the process of removing the initial first etching stop layer on the first transistor region a includes a dry etching process.

Referring to fig. 4, a second etch stop layer 204 is formed on the first etch stop layer 203 of the first transistor region a and the second transistor region B.

Since each of the second transistor regions B has the first etching stop layer 203 and the second etching stop layer 204 thereon, and each of the first transistor regions a has only the second etching stop layer 204 thereon, the thickness of the overall etching stop layer 205 on the second transistor region B is greater than the thickness of the overall etching stop layer 205 on the first transistor region a.

In the subsequent process of performing the cyclical deposition etching process, the number of patterning steps performed on each second transistor region B is greater than that performed on each first transistor region a, and a thickness difference exists between each second transistor region B and the etching stop layer 205 on each first transistor region a, and the thickness difference can compensate for the extra thickness damage of the etching stop layer 205 on the second transistor region B in the patterning step, thereby compensating for the thickness loss of the etching stop layer 205 on the second transistor region B, improving the stability of the threshold voltage of the transistor device, and improving the device performance.

In this embodiment, the thickness of the first etching stop layer 203 is 5 to 20 angstroms; the thickness of the second etching stop layer 204 is 5 to 20 angstroms.

In this embodiment, the material of the etching stop layer 205 includes tantalum nitride.

After the etching stop layer 205 is formed, performing a plurality of cyclic deposition etching processes on the first transistor area a and the second transistor area B until work function structures are formed on the first transistor area a and the second transistor area B respectively, and the thickness of each work function structure is different, wherein each work function structure comprises a plurality of work function layers, each cyclic deposition etching process comprises a deposition step and a patterning step after the deposition step, the number of times of the patterning step performed on the second transistor area B is greater than that performed on the first transistor area a, and each cyclic deposition etching process comprises: depositing on each first transistor area A and each second transistor area B to form an initial work function layer; the initial work function layer is patterned to expose the surface of any one of the first transistor region a, any one of the second transistor region B, or the etch stop layer 205 of any one of the first transistor region a and at least one of the second transistor region B, to form a work function layer.

Specifically, the sum of the number of the first transistor areas a and the number of the second transistor areas B is n+1, the number of the cyclic deposition etching processes is N, and N is a natural number greater than or equal to 2; the work function structure comprises a plurality of work function layers, and the maximum number of layers of the work function layers is N.

Wherein a first work function layer exposing a portion of the etch stop layer 205 is formed in a 1 st cycle deposition etch process.

Thereafter, in a deposition step of the i-th cyclic deposition etching process, depositing and forming an i-th initial work function layer, wherein the i-th initial work function layer is positioned on the exposed surface of the etching stop layer 205 and the i-1-th work function layer; in the patterning step of the ith cyclic deposition etching process, patterning the ith layer initial work function layer to form an ith layer work function layer; the i-1 th work function layer is a work function layer formed in the i-1 st cyclic deposition etching process, and the value range of i is more than 1 and less than or equal to N.

In this embodiment, the number of times of the cyclical deposition etching process is 5. The work function structure is formed to comprise a maximum number of 5 work function layers.

Specifically, the process of forming the work function structure is shown in fig. 4 to 11.

First, a 1 st cycle deposition etch process is performed to form a first work function layer exposing a portion of the etch stop layer 205. Specifically, the process of performing the 1 st cycle deposition etching process is shown in fig. 4 and 5.

Referring to fig. 5, a first initial work function layer 221 is formed by depositing on the surface of the etch stop layer 205 on each of the first transistor region a and the second transistor region B.

In this embodiment, the material of the first initial work function layer 221 includes titanium nitride.

The thickness of the first initial work function layer 221 ranges from 5 a to 30 a. The formation process of the first initial work function layer 221 includes atomic layer deposition.

Referring to fig. 6, the first initial work function layer 221 is patterned to expose the surface of the etch stop layer 205 on the second sub-transistor region II, so as to form a first work function layer 211.

The patterning of the first initial work function layer 221 is performed by removing the first initial work function layer 221 on the second sub-transistor region II while maintaining the first initial work function layer 221 on the first sub-transistor region I, so that the thicknesses of the formed first work function layer 211 on the first sub-transistor region I and the second sub-transistor region II are different.

In this embodiment, the method for patterning the first initial work function layer 221 includes: forming a patterned layer (not shown) having a pattern opening therein exposing the first initial work function layer 221 on the second sub-transistor region II on the first initial work function layer 221; the first initial work function layer 221 is etched using the patterned layer as a mask until the surface of the etch stop layer 205 is exposed.

Specifically, the process of etching the first initial work function layer 221 includes a wet etching process. The parameters of the wet etching process include: the etching liquid comprises ammonia water.

Specifically, the method for forming the patterned layer includes: forming an initial patterning layer (not shown) having a photolithography pattern opening exposing the second sub-transistor region II, and a photolithography pattern layer (not shown) on the initial patterning layer on the first initial work function layer 221; and etching the initial patterning layer by using the photoetching pattern layer as a mask until the surface of the first initial work function layer 221 is exposed to form the patterning layer.

In this embodiment, the initial patterning layer includes an anti-reflection layer (not shown) and a low temperature oxide layer (not shown) on the anti-reflection layer.

Fig. 7 and 8 are schematic cross-sectional views of the process of performing the 2 nd cycle deposition etching.

Referring to fig. 7, a second initial work function layer 222 is formed on the surface of the first work function layer 211, and the second initial work function layer 222 is also located on the exposed surface of the etching stop layer 205.

In this embodiment, the second initial work function layer 222 is further located on the surface of the first work function layer 211 in the third sub-transistor area III, the fourth sub-transistor area IV, the fifth sub-transistor area V, and the sixth sub-transistor area VI.

In this embodiment, the material of the second initial work function layer 222 includes titanium nitride.

Referring to fig. 8, the first work function layer 211 and the second initial work function layer 222 are patterned to expose the surface of the etching stop layer 205 in the third sub-transistor region III, and the second initial work function layer 222 becomes the second work function layer 212.

Since the second work function layer 212 is located on the surface of the first work function layer 211 on the first sub-transistor area I and the surface of the etch stop layer 205 on the second sub-transistor area II. Therefore, the first sub-transistor area I has the first work function layer 211 and the second work function layer 212 thereon, and the second sub-transistor area II has only the second work function layer 212 thereon, so that the overall thickness of the work function layer on the first sub-transistor area I is greater than that on the second sub-transistor area II.

In this embodiment, the method for patterning the first work function layer 211 and the second initial work function layer 222 includes: forming a patterned layer (not shown) having a patterned opening (not shown) therein exposing the third sub-transistor region III on the second initial work function layer 222; the first work function layer 211, and the second initial work function layer 222 are etched using the patterned layer as a mask until the surface of the etch stop layer 205 is exposed.

Specifically, the process of etching the first work function layer 211 and the second initial work function layer 222 includes a wet etching process.

Fig. 9 and 10 are schematic cross-sectional views illustrating the process of performing the 3 rd cycle deposition etching process.

Referring to fig. 9, a third initial work function layer 223 is formed on the surface of the second work function layer 212, and the third initial work function layer 223 is further located on the exposed surface of the etching stop layer 205.

Referring to fig. 10, the first work function layer 211, the second work function layer 212 and the third initial work function layer 223 are patterned to expose the surfaces of the etching stop layer 205 in the fourth sub-transistor region IV, the fifth sub-transistor region V and the sixth sub-transistor region VI, and the third initial work function layer 223 becomes the third work function layer 213.

The method for patterning the first work function layer 211, the second work function layer 212 and the third initial work function layer 223 includes: forming a patterned layer on the third initial work function layer 223, wherein the patterned layer is provided with a pattern opening exposing the third initial work function layer 223 of the fourth sub-transistor area IV, the fifth sub-transistor area V and the sixth sub-transistor area VI; and etching the first layer work function layer 211 to the third layer initial work function layer 223 by taking the patterned layer as a mask until the surface of the etching stop layer 205 is exposed.

Due to the diffusion between the etching stop layer 205 and the work function layers, the etching stop layer 205 is damaged to a certain extent during the patterning process, so that the thickness of the etching stop layer 205 is reduced to a certain extent.

In the present cyclical deposition etching process, a first patterning step is performed on each second transistor region B. In the subsequent cyclical deposition etching process, a second patterning step is performed on each second transistor region B, so that the etching stop layer 205 on each second transistor region B is greatly damaged.

FIG. 11 is a schematic cross-sectional view of a process for performing a 4 th cyclical deposition etch process.

Referring to fig. 11, a fourth initial work function layer (not shown) is formed on the surface of the third work function layer 213, and the fourth initial work function layer is further located on the exposed surface of the etching stop layer 205; the fourth initial work function layer is patterned to expose the surface of the etch stop layer 205 in the fifth sub-transistor region V, which becomes the fourth work function layer 214.

In the present cyclical deposition etching process, a second patterning step is performed on the fifth sub-transistor region V, and the patterning step causes the second damage to the etching stop layer 205 on the fifth sub-transistor region V. However, the patterning step is performed only once on each first transistor area a, so that the etching stop layer 205 on each first transistor area a is damaged only once, and the thickness damage degree of the etching stop layer 205 on the fifth sub-transistor area V is greater than that of the etching stop layer 205 on each first transistor area a.

Since the thickness of the etching stop layer 205 on the fifth sub-transistor area V is greater than the thickness of the etching stop layer 205 on each of the first transistor areas a, the additional second damage to the etching stop layer 205 on the fifth sub-transistor area V is compensated for, thereby compensating for the thickness loss of the etching stop layer 205 on the fifth sub-transistor area V.

In this embodiment, the method for patterning the fourth initial work function layer is the same as the method for patterning the first initial work function layer 221 in fig. 5, and will not be described here.

FIG. 12 is a schematic cross-sectional view of a deposition etching process for the 5 th cycle.

Referring to fig. 12, a fifth initial work function layer (not shown) is formed on the surface of the fourth work function layer 214, and the fifth initial work function layer is further located on the exposed surface of the etching stop layer 205; the fourth work function layer 214 and the fifth initial work function layer are patterned to expose the surface of the etch stop layer 205 in the sixth sub-transistor region VI, the fifth initial work function layer becoming the fifth work function layer 215.

In the cyclical deposition etching process, a second patterning step is performed on the sixth sub-transistor region VI, so that the etching stop layer 205 on the sixth sub-transistor region VI is also damaged secondarily.

The first to fifth work function layers 211 to 215 together form a work function structure (not shown) on the etch stop layer 205, and the work function structures on the first and second transistor regions a and B have different thicknesses.

By performing the cyclic deposition etching process for 5 times, work function structures with different thicknesses are formed on the first to sixth sub-transistor areas I to VI respectively, so as to meet different working voltages required by the transistor devices on the first to sixth sub-transistor areas I to VI.

Specifically, the number of layers of the work function layers on the first to sixth sub-transistor regions I to VI is gradually decreased, and the first sub-transistor region I has the first to fifth work function layers 211 to 215 thereon, so that it has the greatest thickness of the work function structure, and the sixth sub-transistor region VI does not have any work function layer thereon, thereby exposing the surface of the etching stop layer 205.

Since the patterning process is performed twice on each of the second transistor regions B, i.e., the fifth and sixth sub-transistor regions V and VI, and only one patterning process is performed on each of the first transistor regions a in each of the cyclical deposition etching processes, the thickness damage of the etch stop layer 205 on each of the second transistor regions B is greater than the thickness damage of the etch stop layer 205 on each of the first transistor regions a. Because the thickness of the formed etching stop layer 205 on each second transistor area B is greater than that on each first transistor area a, the thickness difference between the second transistor area B and the etching stop layer 205 on the first transistor area a can compensate for the damage of the etching stop layer 205 on the second transistor area B due to the extra thickness, thereby compensating for the thickness loss of the etching stop layer 205 on the second transistor area B, making the thickness of the etching stop layer 205 more uniform, further improving the stability of the threshold voltage of the device, and improving the device performance.

The difference between the thickness of the etching stop layer 205 on the second transistor area B and the thickness of the etching stop layer 205 on the first transistor area a is a first difference, the difference between the number of patterning steps performed on the second transistor area B and the number of patterning steps performed on the first transistor area a is a second difference, and the first difference and the second difference are positively correlated.

Specifically, in this embodiment, the second difference is equal to 1; the first difference is in the range of 5 angstroms to 20 angstroms.

In other embodiments, the second difference is greater than 1. Each time the second difference increases by 1, the first difference increases by 5 to 20 angstroms, thereby effectively compensating for the additional thickness loss of the etch stop layer 205 on the second transistor region B.

In this embodiment, the method for patterning the fourth work function layer 214 and the fifth initial work function layer is the same as the method for patterning the first work function layer 211 and the second initial work function layer 222 in fig. 7, and will not be described here.

In this embodiment, the thickness of each work function layer is in the range of 5 to 30 angstroms.

In this embodiment, the material of each work function layer includes titanium nitride, that is, the material of the work function structure includes titanium nitride.

In other embodiments, the number of cyclical deposition etch processes is 2 to 10.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a plurality of first transistor areas and at least one second transistor area;

forming an etching stop layer on each first transistor area and each second transistor area, wherein the thickness of the etching stop layer on each second transistor area is larger than that of the etching stop layer on each first transistor area;

after forming the etching stop layer, performing a plurality of cyclic deposition etching processes on the first transistor area and the second transistor area until work function structures are respectively formed on the first transistor areas and the second transistor areas, wherein the work function structures have different thicknesses and comprise a plurality of work function layers, each cyclic deposition etching process comprises a deposition step and a patterning step after the deposition step, the number of patterning steps performed on the second transistor area is more than that performed on the first transistor area, and each cyclic deposition etching process comprises: depositing on each first transistor area and each second transistor area to form an initial work function layer; patterning the initial work function layer to expose the surface of any one of the first transistor regions, any one of the second transistor regions, or the etching stop layer of any one of the first transistor regions and at least one of the second transistor regions, so as to form a work function layer.

2. The method of claim 1, wherein the sum of the number of the first transistor regions and the number of the second transistor regions is n+1, the number of the cyclical deposition etching processes is N, and N is a natural number greater than or equal to 2; the work function structure comprises a plurality of work function layers, and the maximum number of layers of the work function layers is N.

3. The method of forming a semiconductor structure of claim 2, wherein the first work function layer exposing a portion of the etch stop layer is formed in a 1 st cyclical deposition etch process.

4. The method of forming a semiconductor structure of claim 3, wherein in the depositing step of the i-th cyclical deposition etching process, an i-th initial work function layer is deposited, the i-th initial work function layer being located on the exposed etch stop layer surface and the i-1-th work function layer surface; in the patterning step of the ith cyclic deposition etching process, patterning the ith layer initial work function layer to form an ith layer work function layer; the i-1 th work function layer is a work function layer formed in the i-1 st cyclic deposition etching process, and the value range of i is more than 1 and less than or equal to N.

5. The method of forming a semiconductor structure of claim 4, wherein in the ith cyclical deposition etch process, the method of patterning the ith initial work function layer comprises: forming a patterned layer on the i-th layer initial work function layer, wherein the patterned layer is internally provided with a pattern opening exposing the i-th layer initial work function layer on any one of the first transistor area and any one of the second transistor area; and etching the first layer work function layer to the i layer initial work function layer by taking the patterned layer as a mask until the surface of the etching stop layer is exposed, wherein the i layer initial work function layer becomes the i layer work function layer.

6. The method of forming a semiconductor structure of claim 4, wherein in the ith cyclical deposition etch process, the method of patterning the ith initial work function layer comprises: forming a patterned layer on the i-th layer initial work function layer, wherein the patterned layer is internally provided with a pattern opening exposing the i-th layer initial work function layer on any one of the first transistor area and at least one of the second transistor areas; and etching the first layer work function layer to the i layer initial work function layer by taking the patterned layer as a mask until the surface of the etching stop layer is exposed, wherein the i layer initial work function layer becomes the i layer work function layer.

7. The method of forming a semiconductor structure of claim 2, wherein N has a value in the range of 2 to 10.

8. The method of claim 5, wherein etching the first to i-th initial work function layers comprises a wet etching process.

9. The method of forming a semiconductor structure of claim 1, wherein the etch stop layer comprises: a first etch stop layer on the second transistor region, and a second etch stop layer on the first and second transistor regions.

10. The method of forming a semiconductor structure of claim 9, wherein the method of forming an etch stop layer comprises: forming an initial first etch stop layer on the first transistor region and the second transistor region; removing the initial first etching stop layer on the first transistor area to form a first etching stop layer on the second transistor area; and forming a second etching stop layer on the first etching stop layer of the first transistor area and the second transistor area.

11. The method of claim 10, wherein removing the initial first etch stop layer over the first transistor region comprises a dry etching process.

12. The method of claim 1, wherein a difference between the thickness of the etch stop layer on the second transistor region and the thickness of the etch stop layer on the first transistor region is a first difference, and a difference between the number of patterning steps performed on the second transistor region and the number of patterning steps performed on the first transistor region is a second difference, the first difference and the second difference being positively correlated.

13. The method of forming a semiconductor structure of claim 12, wherein the second difference is equal to 1; the first difference is in the range of 5 angstroms to 20 angstroms.

14. The method of forming a semiconductor structure of claim 1, wherein the material of the etch stop layer comprises tantalum nitride; the material of the work function structure comprises titanium nitride.

15. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the etch stop layer: and forming a gate dielectric layer on the substrate and a bottom work function layer on the gate dielectric layer.

16. The method of forming a semiconductor structure of claim 15, wherein the material of the bottom work function layer comprises titanium nitride.