CN117348799A - Method, system, storage medium and electronic equipment for automatically identifying EEPROM model - Google Patents
Method, system, storage medium and electronic equipment for automatically identifying EEPROM model Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
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- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention provides a method, a system, a storage medium and electronic equipment for automatically identifying EEPROM model, which comprises the following steps: setting a characteristic word of the EEPROM, writing the characteristic word into the head of the EEPROM, wherein the characteristic word comprises four bytes, the first three bytes are magic numbers, and the fourth byte is the model code of the EEPROM; setting the addressing mode of the EEPROM to be a single byte addressing mode or a double byte addressing mode, and sequentially reading I2C addresses; for each read I2C address, judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte. The method, the system, the storage medium and the electronic equipment for automatically identifying the EEPROM model can realize the automatic identification of the EEPROM model, and are quick and efficient.
Description
Technical Field
The invention belongs to the technical field of embedded application, and particularly relates to a method, a system, a storage medium and electronic equipment for automatically identifying EEPROM (electrically erasable programmable read-Only memory) models.
Background
EEPROM (Electrically Erasable Programmable read only memory) is a common nonvolatile memory chip, has the characteristics of wide working voltage (2.5V-5.5V), more erasing times (more than 10000 times), high writing speed (less than 10 ms), strong anti-interference capability, small volume, low cost and the like, and is widely applied to consumer electronic products.
In the prior art, common EEPROM types are AT24C01, AT24C02, AT24C04, … … and AT24C512, and the capacities are respectively 1 KBbit, 2 KBbit, 4 KBbit, … … and 512 KBbit. And the EEPROM adopts an I2C interface to perform data read-write operation. The time sequence of the read-write data can be divided into three types of single byte address addressing (AT 24C 01/02), compound address addressing (AT 24C 04/08/16) and double byte address addressing (AT 24C32 and above) according to different capacities.
In embedded software development, embedded products nominally support multiple types of EEPROM, and it is desirable that the embedded software automatically recognize what type and capacity is to ensure that the data read is correct and that the data not expected is not read due to looping.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method, a system, a storage medium and an electronic device for automatically identifying an EEPROM model, which can realize automatic identification of the EEPROM model, and is fast and efficient.
In a first aspect, the present invention provides a method of automatically identifying an EEPROM model, the method comprising the steps of: setting a characteristic word of the EEPROM, writing the characteristic word into the head of the EEPROM, wherein the characteristic word comprises four bytes, the first three bytes are magic numbers, and the fourth byte is the model code of the EEPROM; setting the addressing mode of the EEPROM as a single byte addressing mode, and sequentially reading I2C addresses; for each read I2C address, judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number; if yes, reading a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte; when the 2 nd, 1 st and 0 th bytes of all the I2C addresses in the single byte addressing mode are inconsistent with the magic number, setting the addressing mode of the EEPROM to be a double byte addressing mode, and sequentially reading the I2C addresses; for each read I2C address, judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte.
In one implementation of the first aspect, the magic number uses a fixed string.
In one implementation of the first aspect, the I2C addresses are read sequentially in ascending or descending order.
In an implementation manner of the first aspect, the model code is obtained by a model code of an EEPROM.
In a second aspect, the present invention provides a system for automatically identifying an EEPROM model, the system comprising a setup module, a first read module, a first identification module, a second read module, and a second identification module;
the setting module is used for setting a characteristic word of the EEPROM, writing the characteristic word into the head of the EEPROM, wherein the characteristic word comprises four bytes, the first three bytes are magic numbers, and the fourth byte is the model code of the EEPROM;
the first reading module is used for setting the addressing mode of the EEPROM into a single-byte addressing mode and sequentially reading the I2C addresses;
the first identification module is used for judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number or not for each read I2C address; if yes, reading a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte;
the second reading module is used for setting the addressing mode of the EEPROM to be a double-byte addressing mode and sequentially reading the I2C addresses when the 2 nd, 1 st and 0 th bytes of all the I2C addresses in the single-byte addressing mode are inconsistent with the magic number;
the second identification module is used for judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number or not for each read I2C address; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte.
In one implementation manner of the second aspect, the magic number uses a fixed character string.
In one implementation of the second aspect, the I2C addresses are read sequentially in ascending or descending order.
In one implementation manner of the second aspect, the model code is obtained by a model code of an EEPROM.
In a third aspect, the present invention provides an electronic device comprising: a processor and a memory.
The memory is used for storing a computer program;
the processor is used for executing the computer program stored in the memory so as to enable the electronic equipment to execute the method for automatically identifying the EEPROM model.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon a computer program, characterized in that the program when executed by an electronic device implements the above-described method of automatically identifying an EEPROM model.
As described above, the method, system, storage medium and electronic device for automatically identifying EEPROM model of the invention have the following beneficial effects:
(1) The automatic identification of the EEPROM model can be realized, and the speed and the efficiency are high;
(2) The EEPROM can be automatically judged to be single address addressing or double byte addressing, and model information is read after a correct addressing mode is determined, so that accurate information is provided for subsequent embedded development;
(3) The intelligent control system is free of manual operation, high in intelligent degree and high in practicability.
Drawings
FIG. 1 is a schematic view of an electronic device according to an embodiment of the invention;
FIG. 2 is a flow chart of a method for automatically identifying EEPROM types according to the present invention in one embodiment;
FIG. 3 is a schematic diagram of a method for automatically identifying EEPROM types according to the present invention in an embodiment;
FIG. 4 is a schematic diagram of a system for automatically identifying EEPROM types according to the present invention in one embodiment;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
The following embodiments of the present invention provide a method of automatically identifying an EEPROM model, which is applicable to an electronic device as shown in fig. 1. The electronic device in the present invention may include a mobile phone 11, a tablet computer 12, a notebook computer 13, a wearable device, a vehicle-mounted device, an augmented Reality (Augmented Reality, AR)/Virtual Reality (VR) device, an Ultra-Mobile Personal Computer (UMPC), a netbook, a personal digital assistant (Personal Digital Assistant, PDA) and the like with a wireless charging function, and the specific type of the electronic device is not limited in the embodiments of the present invention.
For example, the electronic device may be a Station (ST) in a wireless charging enabled WLAN, a wireless charging enabled cellular telephone, a cordless telephone, a Session initiation protocol (Session InitiationProtocol, SIP) telephone, a wireless local loop (WirelessLocal Loop, WLL) station, a personal digital assistant (Personal Digital Assistant, PDA) device, a wireless charging enabled handheld device, a computing device or other processing device, a computer, a laptop computer, a handheld communication device, a handheld computing device, and/or other devices for communicating over a wireless system, as well as next generation communication systems, such as a mobile terminal in a 5G network, a mobile terminal in a future evolved public land mobile network (PublicLand Mobile Network, PLMN), or a mobile terminal in a future evolved Non-terrestrial network (Non-terrestrial Network, NTN), etc.
For example, the electronic device may communicate with networks and other devices via wireless communications. The wireless communications may use any communication standard or protocol including, but not limited to, global system for mobile communications (GlobalSystem of Mobile communication, GSM), general Packet radio service (General Packet RadioService, GPRS), code division multiple access (Code Division Multiple Access, CDMA), wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA), long term evolution (Long Term Evolution, LTE)), email, short message service (Short Messaging Service, SMS), BT, GNSS, WLAN, NFC, FM, and/or IR techniques, among others. The GNSS may include a global satellite positioning system (Global Positioning System, GPS), a global navigation satellite system (Global Navigation Satellite System, GLONASS), a beidou satellite navigation system (BeiDou navigation Satellite System, BDS), a Quasi zenith satellite system (Quasi-Zenith Satellite System, QZSS) and/or a satellite based augmentation system (Satellite Based Augmentation Systems, SBAS).
The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention.
As shown in fig. 2, the method for automatically identifying an EEPROM model of the present invention includes steps S1 to S5.
Step S1, setting a characteristic word of the EEPROM, writing the characteristic word into the head of the EEPROM, wherein the characteristic word comprises four bytes, the first three bytes are magic numbers, and the fourth byte is the model code of the EEPROM.
Specifically, the feature words of the EEPROM are customized. In the present invention, the character word takes four bytes. Wherein the first three bytes are magic numbers and the last byte is the model code of the EEPROM. Preferably, the magic number may employ a fixed string, such as "JLE". When the magic number adopts three bytes, the judgment is relatively strong, and the erroneous judgment can be effectively avoided. The model code may be derived from a model code of an EEPROM. And the model and the capacity of the EEPROM can be obtained according to the model code of the EEPROM. For example, the model code may represent the following coding scheme:
0x0：24C01
0x1:24C02
0x2：24C04
0x3:24C08
…
0x9:24C512
wherein: the left side is the model code: the right is the model of the corresponding EEPROM.
It should be noted that the feature word needs to be written into the header of the EEPROM, that is, the 0-2 address of the EEPROM is the magic number, such as "JIE", and the 3 address is the model code, such as "0x0".
And S2, setting the addressing mode of the EEPROM to be a single byte addressing mode, and sequentially reading the I2C addresses.
Specifically, typically the I2C address ranges from 0x50 to 0x57. First, the I2C address is scanned by a single byte addressing mode, and the I2C address is read. Wherein each I2C address may be read sequentially in an ascending or descending order.
S3, judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number or not for each read I2C address; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte.
Specifically, for the read I2C address, if the 2 nd, 1 th, 0 th bytes of the I2C address are consistent with the magic number, the I2C address is indicated in the EEPROM location. Thus, the fourth byte of the characteristic word of the EEPROM, i.e. the capacity code, is read, so that the model of the EEPROM can be known from said capacity code. If not, reading the next I2C address until the model of the EEPROM is obtained or the model of the EEPROM is not obtained after all the I2C addresses are read. If the 2 nd, 1 st and 0 th bytes of the I2C address are inconsistent with the magic number, the EEPROM is not in a single byte addressing mode.
In an embodiment, the association relation between the model code and the model and the capacity of the EEPROM is stored in advance, and the model and the capacity of the EEPROM corresponding to the model code are determined according to the association relation.
And S4, when the 2 nd byte, the 1 st byte and the 0 th byte of all the I2C addresses in the single-byte addressing mode are inconsistent with the magic number, setting the addressing mode of the EEPROM to be a double-byte addressing mode, and sequentially reading the I2C addresses.
Specifically, when the 2 nd, 1 st, and 0 th bytes of all I2C addresses in the single byte addressing mode are inconsistent with the magic number, a double byte addressing mode is attempted. Thus, the I2C address is scanned by the double-byte addressing mode, reading the I2C address.
S5, judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number or not for each read I2C address; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte.
Specifically, for the read I2C address, if the 2 nd, 1 th, 0 th bytes of the I2C address are consistent with the magic number, the I2C address is indicated in the EEPROM location. Thus, the fourth byte of the characteristic word of the EEPROM, i.e. the model code, is read, so that the model and the capacity of the EEPROM can be known from said model code. If not, reading the next I2C address until the model of the EEPROM is obtained or the model of the EEPROM is not obtained after all the I2C addresses are read. And if the 2 nd byte, the 1 st byte and the 0 th byte of the I2C address are inconsistent with the magic number, indicating that the EEPROM does not adopt a double-byte addressing mode.
In the embodiment shown in fig. 3, for the single address addressing mode and the double address addressing mode, a mode of traversing and reading the I2C address (i2c_dev) is adopted to perform magic number matching judgment, and then automatic identification of EEPROM model is realized through model code during magic number matching.
The protection scope of the method for automatically identifying the EEPROM model according to the embodiment of the invention is not limited to the execution sequence of the steps listed in the embodiment, and all the schemes of step increase and decrease and step replacement in the prior art according to the principles of the invention are included in the protection scope of the invention.
The embodiment of the invention also provides a system for automatically identifying the EEPROM model, which can realize the method for automatically identifying the EEPROM model, but the realization device of the system for automatically identifying the EEPROM model, which is disclosed by the invention, comprises but is not limited to the structure of the system for automatically identifying the EEPROM model, and all the structural variations and substitutions of the prior art according to the principles of the invention are included in the protection scope of the invention.
As shown in fig. 4, in one embodiment, the system for automatically identifying an EEPROM model of the present invention includes a setting module 41, a first reading module 42, a first identifying module 43, a second reading module 44, and a second identifying module 45.
The setting module 41 is configured to set a feature word of the EEPROM, and write the feature word into a header of the EEPROM, where the feature word includes four bytes, the first three bytes are magic numbers, and the fourth byte is a model code of the EEPROM.
The first reading module 42 is configured to set the addressing mode of the EEPROM to a single-byte addressing mode, and sequentially read the I2C address.
The first identifying module 43 is connected to the setting module 41 and the first reading module 42, and is configured to determine, for each I2C address read, whether the 2 nd, 1 st, and 0 th bytes of the I2C address are consistent with the magic number; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte.
The second reading module 44 is connected to the first identifying module 43, and is configured to set the addressing mode of the EEPROM to be a double-byte addressing mode and sequentially read the I2C addresses when the 2 nd, 1 st, and 0 th bytes of all the I2C addresses in the single-byte addressing mode are inconsistent with the magic number.
The second identifying module 45 is connected to the second reading module 44 and the setting module 41, and is configured to determine, for each I2C address read, whether the 2 nd, 1 st, and 0 th bytes of the I2C address are consistent with the magic number; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte.
The structures and principles of the setting module 41, the first reading module 42, the first identifying module 43, the second reading module 44, and the second identifying module 45 are in one-to-one correspondence with the steps in the method for automatically identifying the EEPROM model, so that the description thereof is omitted herein.
In the several embodiments provided in the present invention, it should be understood that the disclosed system, apparatus, or method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules/units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or units may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.
The modules/units illustrated as separate components may or may not be physically separate, and components shown as modules/units may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules/units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention. For example, functional modules/units in various embodiments of the invention may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.
Those of ordinary skill would further appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The embodiment of the invention also provides a computer readable storage medium. Those of ordinary skill in the art will appreciate that all or part of the steps in the method implementing the above embodiments may be implemented by a program to instruct a processor, where the program may be stored in a computer readable storage medium, where the storage medium is a non-transitory (non-transitory) medium, such as a random access memory, a read only memory, a flash memory, a hard disk, a solid state disk, a magnetic tape (magnetic tape), a floppy disk (floppy disk), an optical disk (optical disk), and any combination thereof. The storage media may be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
The embodiment of the invention also provides electronic equipment. The electronic device includes a processor and a memory.
The memory is used for storing a computer program.
The memory includes: various media capable of storing program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.
The processor is connected with the memory and is used for executing the computer program stored in the memory so as to enable the electronic equipment to execute the method for automatically identifying the EEPROM model.
Preferably, the processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), etc.; but also digital signal processors (Digital Signal Processor, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field programmable gate arrays (Field Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
As shown in FIG. 5, the electronic device of the present invention is embodied in the form of a general purpose computing device. Components of an electronic device may include, but are not limited to: one or more processors or processing units 51, a memory 52, a bus 53 that connects the various system components, including the memory 52 and the processing unit 51.
Bus 53 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
Electronic devices typically include a variety of computer system readable media. Such media can be any available media that can be accessed by the electronic device and includes both volatile and nonvolatile media, removable and non-removable media.
Memory 52 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 521 and/or cache memory 522. The electronic device may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 523 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 5, commonly referred to as a "hard disk drive"). Although not shown in fig. 5, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be coupled to bus 53 through one or more data medium interfaces. Memory 52 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of embodiments of the invention.
A program/utility 524 having a set (at least one) of program modules 5241 may be stored in, for example, memory 52, such program modules 5241 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 5241 generally perform the functions and/or methods in the described embodiments of the invention.
The electronic device may also communicate with one or more external devices (e.g., keyboard, pointing device, display, etc.), with one or more devices that enable a user to interact with the electronic device, and/or with any device (e.g., network card, modem, etc.) that enables the electronic device to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 54. And, the electronic device may also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through the network adapter 55. As shown in fig. 5, the network adapter 55 communicates with other modules of the electronic device over the bus 53. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with an electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method for automatically identifying an EEPROM model, said method comprising the steps of:
setting a characteristic word of the EEPROM, writing the characteristic word into the head of the EEPROM, wherein the characteristic word comprises four bytes, the first three bytes are magic numbers, and the fourth byte is the model code of the EEPROM;
setting the addressing mode of the EEPROM as a single byte addressing mode, and sequentially reading I2C addresses;
for each read I2C address, judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number; if yes, reading a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte;
when the 2 nd, 1 st and 0 th bytes of all the I2C addresses in the single byte addressing mode are inconsistent with the magic number, setting the addressing mode of the EEPROM to be a double byte addressing mode, and sequentially reading the I2C addresses;
for each read I2C address, judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte.
2. The method for automatically identifying an EEPROM model of claim 1, wherein: the magic numbers adopt fixed character strings.
3. The method for automatically identifying an EEPROM model of claim 1, wherein: the I2C addresses are sequentially read in ascending or descending order.
4. The method for automatically identifying an EEPROM model of claim 1, wherein: the model code is obtained by the model code of the EEPROM.
5. A system for automatically identifying EEPROM models, which is characterized by comprising a setting module, a first reading module, a first identification module, a second reading module and a second identification module;
the setting module is used for setting a characteristic word of the EEPROM, writing the characteristic word into the head of the EEPROM, wherein the characteristic word comprises four bytes, the first three bytes are magic numbers, and the fourth byte is the model code of the EEPROM;
the first reading module is used for setting the addressing mode of the EEPROM into a single-byte addressing mode and sequentially reading the I2C addresses;
the first identification module is used for judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number or not for each read I2C address; if yes, reading a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte;
the second reading module is used for setting the addressing mode of the EEPROM to be a double-byte addressing mode and sequentially reading the I2C addresses when the 2 nd, 1 st and 0 th bytes of all the I2C addresses in the single-byte addressing mode are inconsistent with the magic number;
the second identification module is used for judging whether the 2 nd, 1 st and 0 th bytes of the I2C address are consistent with the magic number or not for each read I2C address; if yes, reading out a fourth byte of the characteristic word, and acquiring the model of the EEPROM according to the model code of the fourth byte.
6. The system for automatically identifying an EEPROM model of claim 5, wherein: the magic numbers adopt fixed character strings.
7. The system for automatically identifying an EEPROM model of claim 5, wherein: the I2C addresses are sequentially read in ascending or descending order.
8. The system for automatically identifying an EEPROM model of claim 5, wherein: the model code is obtained by the model code of the EEPROM.
9. An electronic device, the electronic device comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the computer program stored in the memory to cause the electronic device to perform the method of automatically identifying an EEPROM model of any one of claims 1 to 4.
10. A computer readable storage medium having stored thereon a computer program, characterized in that the program, when executed by an electronic device, implements the method of automatically identifying an EEPROM model as claimed in any one of claims 1 to 4.
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