CN117347715A

CN117347715A - Resistance detection circuit and portable resistance detection device

Info

Publication number: CN117347715A
Application number: CN202210754159.7A
Authority: CN
Inventors: 苑家玮; 王博; 许飞
Original assignee: Zhaoyi Innovation Technology Group Co ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2022-06-28
Filing date: 2022-06-28
Publication date: 2024-01-05

Abstract

The application discloses a resistance detection circuit and a portable resistance detection device. The resistance detection circuit includes: the output end of the controller is used for outputting a first voltage signal, and the input end of the controller is used for being coupled with a port of the device to be tested; the input end of the constant current source is coupled with the output end of the controller, and the output end of the constant current source is used for being coupled with the port of the device to be tested; the constant current source outputs a constant current signal to the port of the device to be tested according to the first voltage signal, and the controller obtains a second voltage signal of the port of the device to be tested and determines the resistance value of the port of the device to be tested according to the second voltage signal. By the mode, the measuring efficiency of the resistance value of the port of the device to be measured can be improved, and the detection flow is simplified.

Description

Resistance detection circuit and portable resistance detection device

Technical Field

The present disclosure relates to the field of resistor detection technology, and in particular, to a resistor detection circuit and a portable resistor detection device.

Background

With the continuous progress and improvement of photoetching machines and chip designs, the number of pins of the chip is increased. In general, the internal resistance of the pins of the chip is tested before shipment, and a user can know a typical value in a data manual, but the accurate internal resistance of the chip is measured when actually designing the circuit.

At present, the measuring method adopts a manual measuring mode, and the efficiency is low.

Disclosure of Invention

The application provides a resistance detection circuit and a portable resistance detection device, which can improve the measurement efficiency of the resistance value of the port of a device to be detected and simplify the detection flow.

In a first aspect, embodiments of the present application provide a resistance detection circuit, including: the output end of the controller is used for outputting a first voltage signal, and the input end of the controller is used for being coupled with a port of the device to be tested; the input end of the constant current source is coupled with the output end of the controller, and the output end of the constant current source is used for being coupled with the port of the device to be tested; the constant current source outputs a constant current signal to the port of the device to be tested according to the first voltage signal, and the controller obtains a second voltage signal of the port of the device to be tested and determines the resistance value of the port of the device to be tested according to the second voltage signal.

Wherein the constant current source includes: a first operational amplifier; the first end of the gain resistor is coupled with the output end of the first operational amplifier; the first operational amplifier and the gain resistor form a feedback circuit, and the voltage value of the first voltage signal and the resistance value of the gain resistor determine the current value of the current signal, wherein the current value of the current signal does not change along with whether the port of the device to be tested is connected or not.

Wherein the constant current source further comprises: the first end of the first resistor is coupled with the output end of the controller, and the second end of the first resistor is coupled with the non-inverting input end of the first operational amplifier; the first end of the second resistor is coupled with the non-inverting input end of the first operational amplifier; the first end of the third resistor is grounded, and the second end of the third resistor is coupled with the inverting input end of the first operational amplifier; the first end of the fourth resistor is coupled with the inverting input end of the first operational amplifier, and the second end of the fourth resistor is coupled with the output end of the first operational amplifier; the non-inverting input end of the second operational amplifier is coupled with the second end of the gain resistor, the inverting input end of the second operational amplifier is coupled with the output end of the second operational amplifier, and the output end of the second operational amplifier is coupled with the second end of the second resistorThe method comprises the steps of carrying out a first treatment on the surface of the The second end of the gain resistor is used as an output end of the constant current source, and the first resistor, the second resistor, the third resistor and the fourth resistor meet the following conditions:wherein R is ₁ A resistance value of the first resistor R ₂ The resistance value of the second resistor, R ₃ The resistance value of the third resistor, R ₄ The resistance value of the fourth resistor.

Wherein the constant current source further comprises: the first end of the capacitor is coupled with the first end of the fourth resistor, and the second end of the capacitor is coupled with the second end of the fourth resistor.

The resistance value of the gain resistor is configured to be adjustable to adjust the voltage value of the second voltage signal within a preset range.

Wherein the gain resistor comprises a plurality of resistors; the constant current source further comprises a digital switch, a plurality of input ends of the digital switch are coupled with a plurality of general input and output ends of the controller, each of a plurality of output ends of the digital switch is coupled with one of a plurality of resistors, and the digital switch is configured to control whether the plurality of resistors are connected or not according to a control signal output by the controller from the plurality of general input and output ends, so that the connection mode of the plurality of resistors is changed to change the resistance value of the gain resistor.

The controller responds to the obtained voltage value of the second voltage signal within a set proportion range of a preset maximum voltage value, and determines the resistance value of the port of the device to be tested according to the second voltage signal; or the controller responds to the obtained second voltage signal in a set proportion range that the voltage value of the second voltage signal is not the preset maximum voltage value, and adjusts the resistance value of the gain resistor.

The controller responds to the voltage value of the second voltage signal or the set proportion range of which the voltage division value is lower than a preset maximum voltage value, and reduces the resistance value of the gain resistor; the controller is used for adjusting the resistance value of the gain resistor in response to the voltage value of the second voltage signal or the set proportion range of the voltage division value of the second voltage signal higher than the preset maximum voltage value.

Wherein the method comprises the steps ofThe constant current source further includes: the first end of the first resistor is coupled with the output end of the controller, and the second end of the first resistor is coupled with the non-inverting input end of the first operational amplifier; the first end of the second resistor is coupled with the non-inverting input end of the first operational amplifier, and the second end of the second resistor is coupled with the second end of the gain resistor; the first end of the third resistor is grounded, and the second end of the third resistor is coupled with the inverting input end of the first operational amplifier; the first end of the fourth resistor is coupled with the inverting input end of the first operational amplifier, and the second end of the fourth resistor is coupled with the output end of the first operational amplifier; the first end of the gain resistor is used as an output end of the constant current source, and the gain resistor, the first resistor, the second resistor, the third resistor and the fourth resistor meet the following conditions:

Wherein R is _gain R is the resistance value of the gain resistor ₁ A resistance value of the first resistor R ₂ The resistance value of the second resistor, R ₃ The resistance value of the third resistor, R ₄ The resistance value of the fourth resistor.

The controller calculates the resistance value of the port of the device to be tested based on the following formula:or (b)

Wherein R is _{Upper part} The resistance of the port of the device to be tested is represented as a pull-up resistance, R _{Lower part(s)} The resistance of the port of the device to be tested is represented as pull-down resistance, V ₁ Is the voltage value of the first voltage signal, V ₂ Is the voltage value of the second voltage signal, V _DD For the supply voltage of the device to be tested, R _gain Is the resistance value of the gain resistor, wherein V _1/ R _gain Is the current value of the current signal.

The controller further comprises a digital-to-analog conversion module and an analog-to-digital conversion module, wherein the controller controls the digital-to-analog conversion module to output a first voltage signal from the output end, and the controller obtains a second voltage signal or a partial pressure value of the second voltage signal from the input end through the analog-to-digital conversion module.

The resistor detection circuit further comprises a first voltage follower, wherein the input end of the first voltage follower is coupled with the output end of the controller to receive a first voltage signal, the output end of the first voltage follower is coupled with the input end of the constant current source, and the controller further obtains a third voltage signal of the output end of the first voltage follower and adjusts the first voltage signal output by the controller according to whether the third voltage signal reaches an expected value or not.

Wherein, resistance detection circuit still includes: the input end of the second voltage follower is coupled with the port of the device to be tested; the first end of the first resistor is coupled with the output end of the second voltage follower, and the second end of the first resistor is coupled with the input end of the controller; the first end of the second resistor is coupled with the second end of the first resistor, and the second end of the second resistor is grounded, wherein the voltage signal of the input end of the controller is a second voltage signal or a voltage division value of the second voltage signal.

In a second aspect, embodiments of the present application provide a portable resistance detection device including a resistance detection circuit as provided in the first aspect above.

The beneficial effects of this application are: in distinction from the prior art, the present application provides a resistance detection circuit, the resistance detection circuit includes: the output end of the controller is used for outputting a first voltage signal, and the input end of the controller is used for being coupled with a port of the device to be tested; the input end of the constant current source is coupled with the output end of the controller, and the output end of the constant current source is used for being coupled with the port of the device to be tested; the constant current source outputs a constant current signal to the port of the device to be tested according to the first voltage signal, and the controller obtains a second voltage signal of the port of the device to be tested and determines the resistance value of the port of the device to be tested according to the second voltage signal. By the mode, the constant current source is utilized to output a constant current signal to the port of the device to be tested so as to detect the second voltage signal of the port, and then the resistance value of the port, such as the resistance value of the pull-up resistor or the pull-down resistor of the port of the device to be tested, is determined by utilizing the second voltage signal, so that the measurement efficiency of the resistance value of the port of the device to be tested can be improved, and the detection flow is simplified. In a further embodiment, the current value of the current signal output by the constant current source is not changed due to the port access of the device to be tested; in a further embodiment, the controller can adjust the second voltage signal of the port of the device to be measured within a preset range by adjusting the gain resistor of the constant current source, so as to realize automatic matching of the resistance value of the port of the device to be measured and the preset voltage range of the controller, thereby further improving the measurement efficiency and simplifying the detection flow.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Wherein:

FIG. 1 is a schematic diagram of an embodiment of a resistance detection circuit provided herein;

FIG. 2 is a schematic diagram of another embodiment of a resistance detection circuit provided herein;

FIG. 3 is a schematic diagram of another embodiment of a resistance detection circuit provided herein;

FIG. 4 is a schematic diagram of another embodiment of a resistance detection circuit provided herein;

FIG. 5 is a schematic diagram of an embodiment of a gain resistor provided herein;

FIG. 6 is a schematic diagram of another embodiment of a gain resistor provided herein;

FIG. 7 is a schematic diagram of another embodiment of a resistance detection circuit provided herein;

FIG. 8 is a schematic diagram of another embodiment of a resistance detection circuit provided herein;

FIG. 9 is a schematic diagram of another embodiment of a resistance detection circuit provided herein;

FIG. 10 is a schematic diagram of another embodiment of a resistance detection circuit provided herein;

FIG. 11 is a schematic diagram illustrating a structure of an embodiment of a portable resistor detection device according to the present disclosure;

fig. 12 is a schematic view of an application scenario of the portable resistance detection device provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not limiting. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a resistance detection circuit provided in the present application. The resistance detection circuit 100 includes: a controller 10 and a constant current source 20.

The output end of the controller 10 is used for outputting a first voltage signal, and the input end of the controller 10 is used for being coupled with the port of the device under test 200.

The device under test 200 may have a plurality of ports, each of which may implement a different input or inputs. Thus, upon determining the destination port, then the input of the controller 10 is coupled to the destination port. In some embodiments, the ports of the device under test 200 are pins. The input of the controller 10 may be coupled to the pin. The device under test 200 may be a correspondingly sized chip.

The input end of the constant current source 20 is coupled to the output end of the controller 10, and the output end of the constant current source 20 is used for coupling to the port of the device under test 200.

The constant current source 20 outputs a constant current signal to the port of the device under test 200 according to the first voltage signal, and the controller 10 obtains a second voltage signal of the port of the device under test 200 and determines the resistance value of the port of the device under test 200 according to the second voltage signal.

The output terminal of the constant current source 20 and the input terminal of the controller 10 are both coupled to the same port (also referred to as a port to be measured) of the device under test 200, wherein the pull-up or pull-down resistor of the port to be measured is the resistance value to be measured. In some embodiments, the input terminal of the controller 10 is not directly electrically connected to the port to be tested, and may be electrically connected to the port to be tested via a voltage dividing resistor and/or a voltage follower to obtain the second voltage signal of the port to be tested.

In an application scenario, after the device under test 200 is manufactured, a data table corresponding to the device under test 200 is generated. In the data table, it can be determined whether each port of the device under test 200 is correspondingly connected to a pull-up resistor or a pull-down resistor. At this time, a corresponding calculation formula may be determined according to the pull-up resistor or the pull-down resistor corresponding to each port, and the second voltage signal is input to the calculation formula to determine the resistance value of the port of the device under test 200.

In this embodiment, the resistance detection circuit 100 uses the constant current source 20 to output a constant current signal to the port of the device under test 200 to detect the second voltage signal of the port, and further uses the obtained second voltage signal to determine the resistance value of the port under test, such as the resistance value of the pull-up resistor or the pull-down resistor of the port of the device under test 200, so as to improve the measurement efficiency of the resistance value of the port of the device under test 200 and simplify the detection flow.

Referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of a resistance detection circuit provided in the present application. The resistance detection circuit 100 includes: a controller 10 and a constant current source 20.

Wherein the constant current source 20 includes: first operational amplifier opa1 and gain resistor R _gain 。

Wherein the gain resistor R _gain The first end of the first operational amplifier opal is coupled with the output end of the first operational amplifier opal; wherein, the first operational amplifier opal and the gain resistor R _gain Form a feedback circuit, the voltage value of the first voltage signal and a gain resistor R _gain The resistance value of the current signal is determined, wherein the current value of the current signal does not change with whether the port of the device under test 200 is connected or not. In one embodiment, the first operational amplifier opal is a unity gain. In a further embodiment, the controller 10 may further adjust the gain resistance R _gain To adjust the second voltage signal of the port of the device under test 200 within the preset range, so as to realize the automatic matching of the resistance value of the port of the device under test 200 and the measurable voltage range of the controller 10.

Wherein, the output end of the controller 10 is connected with the non-inverting input end of the first operational amplifier opal, and the output end of the first operational amplifier opal is connected with the gain resistor R _gain The negative phase input end of the first operational amplifier opal is connected with a gain resistor R _gain Thereby forming a feedback circuit.

In some embodiments, the controller 10 may calculate the resistance value of the port of the device under test 200 using the following equation:

wherein R is _{Upper part} The resistance of the port of the device to be tested is represented as a pull-up resistance, V ₁ Is the voltage value of the first voltage signal, V ₂ Is the voltage value of the second voltage signal, V _DD R is the supply voltage of the device under test 200 _gain Is a gain resistor R _gain Wherein V is ₁ /R _gain Is the current value of the current signal, which is not due to R _{Upper part} Access is varied. Alternatively, the controller 10 may calculate the resistance value of the port of the device under test 200 using the following formula:

wherein R is _{Lower part(s)} The resistance of the port of the device to be tested is represented as pull-down resistance, V ₁ Is the voltage value of the first voltage signal, V ₂ Is the voltage value of the second voltage signal, R _gain Is a gain resistor R _gain Wherein V is ₁ /R _gain Is the current value of the current signal, which is not due to R _{Lower part(s)} Access is varied.

In the present embodiment, the resistance detection circuit 100 uses the first operational amplifier opa1 of the constant current source 20 and the gain resistor R _gain And outputting a constant current signal to the port of the device under test 200 to detect a second voltage signal of the port, and determining the resistance value of the port by using the second voltage signal, such as the resistance value of a pull-up resistor or a pull-down resistor of the port of the device under test 200, wherein the current signal output by the constant current source 20 does not change with the connection of the pull-up resistor or the pull-down resistor of the port of the device under test 200, so that the measurement efficiency of the resistance value of the port of the device under test 200 can be improved, and the detection flow is simplified.

In a further embodiment, the controller 10 further comprises a digital-to-analog conversion module D/A and an analog-to-digital conversion module A/D, wherein the controller 10 controls the digital-to-analog conversion module D/A to output the first voltage signal (the analog voltage signal output according to the expected value) from the output terminal, and the controller 10 obtains the voltage value V of the second voltage signal from the input terminal via the analog-to-digital conversion module A/D ₂ Or a second voltage signal V ₂ Is a partial pressure value of (a). The controller 10 can automatically adjust the gain resistor R _gain To adjust the second voltage signal V of the port of the device under test 200 ₂ Or the voltage division value is in the preset voltage range of the A/D conversion module of the controller 10, so as to realize the automatic operation of the resistance value of the port of the device 200 to be tested and the preset voltage range of the A/D conversion module of the controller 10Matching.

Referring to fig. 3, fig. 3 is a schematic structural diagram of another embodiment of a resistance detection circuit provided in the present application. The resistance detection circuit 100 includes: a controller 10 and a constant current source 20.

Wherein the constant current source 20 includes: first operational amplifier opa1, gain resistor R _gain A first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a second operational amplifier opa2.

The first end of the first resistor R1 is coupled to the output end of the controller 10, and the second end of the first resistor R1 is coupled to the non-inverting input end of the first operational amplifier opal.

The first end of the second resistor R2 is coupled to the non-inverting input terminal of the first operational amplifier opal.

The first end of the third resistor R3 is grounded, and the second end of the third resistor R3 is coupled to the inverting input end of the first operational amplifier opal.

The first end of the fourth resistor R4 is coupled to the inverting input terminal of the first operational amplifier opal, and the second end of the fourth resistor R4 is coupled to the output terminal of the first operational amplifier opal.

The non-inverting input terminal of the second operational amplifier opa2 is coupled to the second terminal of the gain resistor, the inverting input terminal of the second operational amplifier opa2 is coupled to the output terminal of the second operational amplifier opa2, and the output terminal of the second operational amplifier opa2 is coupled to the second terminal of the second resistor R2.

Wherein the gain resistor R _gain The second terminal of the constant current source 20, and the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 satisfy:wherein R is ₁ A resistance value of the first resistor R1, R ₂ A resistance value of the second resistor R2, R ₃ A resistance value of the third resistor R3, R ₄ The resistance value of the fourth resistor R4.

In some embodiments, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first operational amplifier opa1 and the second operational amplifier opa2 form a negative feedback path, wherein the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 all select a resistor with 0.1% precision.

The first operational amplifier opa1 and the second operational amplifier opa2 are both unit gains, and function to generate a constant current signal that does not change due to whether the port to be tested of the device under test 200 is connected or not. In some embodiments, a constant current

In the above manner, the controller 10 acquires the second voltage signal of the port of the device under test 200, and determines the resistance value of the port of the device under test 200 according to the second voltage signal.

In the present embodiment, the resistor detection circuit 100 forms a negative feedback path by using the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first operational amplifier opa1 and the second operational amplifier opa2 of the constant current source 20, outputs a constant current signal to the port of the device under test 200, and the controller 10 only needs to detect the voltage value V of the second voltage signal of the port under test ₂ By the second voltage signal V ₂ And the constant current signalThe resistance value of the port to be tested, such as the resistance value of the pull-up resistor or the pull-down resistor of the port of the device to be tested 200, can be determined, the measurement efficiency of the resistance value of the port of the device to be tested 200 can be improved, and the detection flow is simplified.

Referring to fig. 4, fig. 4 is a schematic structural diagram of another embodiment of a resistance detection circuit provided in the present application. The resistance detection circuit 100 includes: a controller 10 and a constant current source 20.

Wherein the constant current source 20 includes: first operational amplifier opal, gain resistor R _gain The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the second operational amplifier opa2 and the capacitor C1.

The first end of the capacitor C1 is coupled to the first end of the fourth resistor R4, and the second end of the capacitor C1 is coupled to the second end of the fourth resistor R4. The capacitor C1 is used to provide high frequency compensation of the first operational amplifier opal.

In some embodiments, the gain resistor R _gain Is configured to be adjustable to adjust the voltage value of the second voltage signal within a preset range.

Wherein the gain resistor R _gain Comprises a plurality of resistors; the constant current source 20 further includes a digital switch (not shown in fig. 4), an input terminal of the digital switch is coupled to a plurality of general purpose input output terminals (GPIO 0 to GPIO n) of the controller 10, each of a plurality of output terminals of the digital switch is coupled to one of a plurality of resistors, and the digital switch is configured to control whether the plurality of resistors are connected or not according to a control signal output from the plurality of general purpose input output terminals (GPIO 0 to GPIO n) of the controller 10, thereby changing a connection manner of the plurality of resistors to change a resistance value of the gain resistor.

In an application scenario, as shown in fig. 5, a point a in fig. 5 is connected to the output end of the first operational amplifier opal, and a point B is connected to the port of the device under test 200. Gain resistor R _gain May include a first gain resistor R _{gain_1} A second gain resistor R _{gain_2} Third gain resistor R _{gain_3} Fourth gain resistor R _{gain_4} And an nth gain resistor R _{gain_n} . First gain resistor R _{gain_1} A first end of (a) is connected with the point A, a first gain resistor R _{gain_1} A second end of the switch K1 is connected with a first end of the switch K1, a second end of the switch K1 is connected with a point B, and a second gain resistor R _{gain_2} A first end of the resistor is connected with the point A, a second gain resistor R _{gain_2} A second end of the switch K2 is connected with a first end of the switch K2, a second end of the switch K2 is connected with a point B, and a third gain resistor R _{gain_3} A first end of (a) is connected with the point A, a third gain resistor R _{gain_3} A second end of the switch K3 is connected with a first end of the switch K3, a second end of the switch K3 is connected with a point B, and a fourth gain resistor R _{gain_4} A first end of the resistor is connected with the point A, a fourth gain resistor R _{gain_4} A second end of the switch K4 is connected with a first end of the switch K4, a second end of the switch K4 is connected with a point B, and an nth gain resistor R _{gain_n} Is connected with the point A at the first end of the circuit, and the nth gain resistor R _{gain_n} The second end of the switch Kn is connected with the first end of the switch Kn, and the second end of the switch Kn is connected with the point B.

In one embodiment, the switches K1, K2, K3, K4 and Kn are located inside the digital switch 50 independent from the outside of the controller 10, and are controlled by control signals output from a plurality of general purpose input/output terminals (GPIO 0 to GPIO n) by the controller 10.

The digital switch 50 is configured to control on/off of at least one switch in the controller 10 according to control signals output from multiple general purpose input/output terminals (GPIO 0-GPIO) to change the connection mode of multiple resistors to change the gain resistor R _gain Is a resistance value of (a).

As shown in fig. 5, the digital switch 50 controls the digital switches K1, K2, K3, K4 and Kn inside to be turned on, so that the first gain resistor R _{gain_1} A second gain resistor R _{gain_2} Third gain resistor R _{gain_3} Fourth gain resistor R _{gain_4} And an nth gain resistor R _{gain_n} In parallel, the total resistance value can be expressed as:

wherein R is _{Total (S)} Represents the total resistance value after parallel connection, R _{gain_1} Representing the first gain resistance R _{gain_1} Resistance value R of (2) _{gain_2} Representing a second gain resistance R _{gain_2} Resistance value R of (2) _{gain_3} Representing a third gain resistance R _{gain_3} Resistance value R of (2) _{gain_4} Represents the fourth gain resistance R _{gain_4} Resistance value R of (2) _{gain_n} Represents the nth gain resistor R _{gain_n} Is a resistance value of (a).

The digital switch 50 can control the conduction of at least one of the digital switches K1, K2, K3, K4 and Kn according to the control signals outputted from the controller 10 at the general purpose input/output terminals (GPIO 0-GPIO) to change the gain resistor R _gain Is a resistance value of (a). The controller 10 can output corresponding control signals at general purpose input/output terminals (GPIO 0-GPIO) to change the gain resistance R according to a control algorithm described in detail in FIG. 12 _gain To adjust the voltage value of the second voltage signal V2 within a preset range, or to adjust the voltage value of the second voltage signal V2 or the voltage division value thereof within a preset proportion range of a preset maximum voltage value, wherein the preset maximum voltage value is determined by the maximum range of the analog-to-digital conversion module a/D of the controller 10.

In another application scenario, as shown in fig. 6, a point a in fig. 6 is connected to the output end of the first operational amplifier opal, and a point B is connected to the port of the device under test 200. Gain resistor R _gain May include a first gain resistor R _{gain_1} A second gain resistor R _{gain_2} Third gain resistor R _{gain_3} And a fourth gain resistor R _{gain_4} . First gain resistor R _{gain_1} Is connected to the point a. First gain resistor R _{gain_1} A second end of (2) is connected with a second gain resistor R _{gain_2} Is provided. Second gain resistor R _{gain_2} A second end of (a) is connected with a third gain resistor R _{gain_3} Is provided. Third gain resistor R _{gain_3} A second end of the capacitor is connected with a fourth gain resistor R _{gain_4} Is provided. Fourth gain resistor R _{gain_4} The second end of the n-th gain resistor Rgain_n is connected with the first end of the n-th gain resistor Rgain_n, and the second end of the n-th gain resistor Rgain_n is connected with the point B.

Switch K1 and first gain resistor R _{gain_1} In parallel, a switch K2 and a second gain resistor R _{gain_2} In parallel, a switch K3 and a third gain resistor R _{gain_3} Parallel connection, switch K4 and fourth gain resistor R _{gain_4} In parallel, the switch Kn is connected in parallel with the nth gain resistor rgain_n.

The digital switch 50 is configured to make at least one switch inside the controller 10 on or off according to control signals output by a plurality of general purpose input/output terminals (GPIO 0-GPIO) to change the connection mode of a plurality of resistors to change the gain resistor R _gain Is a resistance value of (a). The controller 10 may be based onThe control algorithm described in detail later with reference to FIG. 12 outputs corresponding control signals at general purpose input/output terminals (GPIO 0-GPIO) to change the gain resistance R _gain To adjust the voltage value of the second voltage signal V2 within a preset range, or to adjust the voltage value of the second voltage signal V2 or the voltage division value thereof within a preset proportion range of a preset maximum voltage value, wherein the preset maximum voltage value is determined by the maximum range of the analog-to-digital conversion module a/D of the controller 10.

As shown in fig. 6, the digital switch 50 controls the digital switches K1, K2, K3 and K4 inside thereof to be turned off, and the first gain resistor R _{gain_1} A second gain resistor R _{gain_2} Third gain resistor R _{gain_3} And a fourth gain resistor R _{gain_4} In series, the total resistance value can be expressed as:

R _{total (S)} ＝R _{gain_1} +R _{gain_2} +R _{gain_3} +R _{gain_4} +R _{gain_n} ；

Wherein R is _{Total (S)} Represents the total resistance value after parallel connection, R _{gain_1} Representing the first gain resistance R _{gain_1} Resistance value R of (2) _{gain_2} Representing a second gain resistance R _{gain_2} Resistance value R of (2) _{gain_3} Representing a third gain resistance R _{gain_3} Resistance value R of (2) _{gain_4} Represents the fourth gain resistance R _{gain_4} Rgain_n represents the resistance of the n-th gain resistor Rgain_n.

In an application scenario, the controller 10 determines the resistance value of the port of the device under test 200 according to the second voltage signal in response to the acquired voltage value or the partial voltage value of the second voltage signal V2 being within a set proportion range of a preset maximum voltage value.

If the voltage value of the second voltage signal V2 or the partial voltage value thereof is within the set proportion range of the preset maximum voltage value, it is indicated that the second voltage signal V2 or the partial voltage value thereof is normally collected, and the resistor value can be calculated, wherein the preset maximum voltage value is determined by the maximum range of the analog-to-digital conversion module a/D of the controller 10, for example, the analog-to-digital conversion module a/D of the controller 10 is a 12-bit (bit) ADC, the maximum range thereof is 4096, and the digital value range corresponding to the set proportion range can be the intermediate range 2200-2600, so that the measurement of the second voltage signal V2 is more accurate.

In an application scenario, the controller 10 adjusts the gain resistor R in response to the obtained voltage value or the partial voltage value of the second voltage signal not being within a set proportion range of the preset maximum voltage value _gain Is a resistance value of (a).

If the voltage value of the second voltage signal is not within the set proportion range of the preset maximum voltage value, indicating that the second voltage signal V2 or the partial voltage value thereof is abnormally collected, adjusting the gain resistor R _gain Is a resistance value of (a).

E.g. gain resistor R _gain As shown in fig. 5 or 6, the controller 10 can output corresponding control signals at general purpose input/output terminals (GPIO 0-GPIO on) according to a control algorithm to control the digital switch 50 to change the gain resistor R _gain Is a resistance value of (a). Further, the gain resistor R is adjusted _gain After the resistance value of the second voltage signal V2 or the voltage division value thereof is collected again through the a/D module of the controller 10, and whether the obtained voltage value of the second voltage signal V2 is within a preset range is determined (for example, according to whether the obtained voltage value of the second voltage signal V2 or the voltage division value thereof collected by the a/D module of the controller 10 is within a set proportion range of a preset maximum voltage value, the preset maximum voltage value is determined by the full scale of the a/D module of the controller 10). When the voltage value of the second voltage signal V2 or the voltage division value thereof is within the set proportion range of the preset maximum voltage value, the controller 10 determines the resistance value of the port of the device under test 200 according to the second voltage signal V2.

In some embodiments, the gain resistor R _gain The controller 10 sets down the gain resistor R in response to the voltage value of the second voltage signal V2 or the set proportion range of the divided voltage value thereof being lower than the preset maximum voltage value by default as the maximum resistance value _gain Resistance value of (2); the controller 10 increases the gain resistor R in response to the voltage value of the second voltage signal V2 or the set proportion range of the divided voltage value thereof being higher than the preset maximum voltage value _gain Is a resistance value of (a).

It can be understood that by adjusting down the gain resistor R according to the relation between the current and the resistor _gain Resistance of (2)The value can increase the constant current signal output by the constant current source 20, and after the constant current signal output by the constant current source 20 is increased, the voltage value or the partial voltage value of the collected second voltage signal V2 is increased, so that the voltage value or the partial voltage value falls into the set proportion range of the preset maximum voltage value; by raising the gain resistance R _gain The resistance value of the second voltage signal V2 is reduced, so that the constant current signal output by the constant current source 20 can be reduced, and the collected voltage value or the partial voltage value thereof of the second voltage signal V2 is reduced after the constant current signal output by the constant current source 20 is smaller, so that the voltage value or the partial voltage value thereof falls within the set proportion range of the preset maximum voltage value.

In this embodiment, the resistor detection circuit 100 forms a negative feedback path by using the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first operational amplifier opa1 and the second operational amplifier opa2 of the constant current source 20, and outputs a constant current signal to the port of the device under test 200, and the current value of the current signal output by the constant current source 20 is not changed due to the access of the port of the device under test 200, and the second voltage signal V2 of the port is detected, so that the resistor value of the port, such as the resistance value of the pull-up resistor or the pull-down resistor of the port of the device under test 200, is determined by using the voltage signal V2, so that the measurement efficiency of the resistor value of the port of the device under test 200 can be improved, and the detection flow is simplified.

Further, an adjustable gain resistor R is utilized _gain The constant current source 20 is enabled to output an adjustable constant current signal, specifically, the controller 10 can control the digital switch 50 with its general purpose input/output ports GPIO0 to GPIO n to adjust the gain resistor R _gain Thereby adjusting the constant current signal V output by the constant current source 20 ₁ /R _gain And further, the second voltage signal V2 of the port of the device under test 200 is adjusted to be within the preset range, so that the automatic matching of the resistance value of the port of the device under test 200 and the preset voltage range of the controller 10 is realized, more detection scenes can be adapted, the measurement efficiency of the resistance value of the port of the device under test 200 is improved, and the detection flow is simplified.

Referring to fig. 7, fig. 7 is a schematic structural diagram of another embodiment of a resistance detection circuit provided in the present application. The resistance detection circuit 100 includes: a controller 10 and a constant current source 20.

Wherein the constant current source 20 includes: first operational amplifier opal, gain resistor R _gain A first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4.

The first end of the second resistor R2 is coupled to the non-inverting input end of the first operational amplifier opal, and the second end of the second resistor R2 is coupled to the gain resistor R _gain Is provided.

Wherein, unlike the embodiment of FIG. 4, the gain resistor R _gain The first terminal of the constant current source 20, and the gain resistance, the first resistance R1, the second resistance R2, the third resistance R3, and the fourth resistance R4 satisfy: the method comprises the steps of carrying out a first treatment on the surface of the Wherein R is _gain Is a gain resistor R _gain The resistance value of the first resistor R1, the resistance value of the second resistor R2, the resistance value of the third resistor R3, and the resistance value of the fourth resistor R4.

The constant current source 20 outputs a constant current signal to the port of the device under test 200 according to the first voltage signal V1, and the controller 10 obtains a second voltage signal V2 of the port of the device under test 200, and determines the resistance value of the port of the device under test 200 according to the second voltage signal V2.

In the present embodiment, the resistance detection circuit 100 uses the first operational amplifier opal of the constant current source 20 and the gain resistor R _gain The first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 form a path, and a constant current signal is output to the port of the device under test 200 to detect the voltage signal of the port, and the resistance value of the port is determined by using the voltage signal, such as to be tested The resistance value of the pull-up resistor or the pull-down resistor of the port of the device 200 can be measured, so that the measurement efficiency of the resistance value of the port of the device 200 to be measured can be improved, and the detection flow is simplified.

Further, an adjustable gain resistor R is utilized _gain The constant current source 20 is enabled to output an adjustable constant current signal, specifically, the controller 10 can control the digital switch 50 with its general purpose input/output ports GPIO0 to GPIO n to adjust the gain resistor R _gain Thereby adjusting the constant current signal V output by the constant current source 20 ₁ /R _gain Further, the second voltage signal V2 of the port of the device under test 200 is adjusted within the preset range, so as to automatically match the resistance value of the port of the device under test 200 with the preset voltage range of the controller 10, unlike the embodiment of fig. 4, in which the embodiment of fig. 7 adjusts the gain resistor R _gain In this case, it is also necessary to ensure that r4/r3= (r2+r) is satisfied at the same time _gain ) R1, the resistance of resistor R2 therefore also needs to be adjusted synchronously to accommodate the gain resistor R _gain Is a variation of (c).

Referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of a resistance detection circuit provided in the present application. The resistance detection circuit 100 includes: a controller 10, a constant current source 20 and a first voltage follower 30.

The controller 10 and the constant current source 20 may refer to any of the above embodiments, and will not be described herein.

The input end of the first voltage follower 30 is coupled to the output end of the controller 10 to receive the first voltage signal V1, the output end of the first voltage follower 30 is coupled to the input end of the constant current source 20, and the controller 10 further obtains a third voltage signal V3 at the output end of the first voltage follower 30 and adjusts the first voltage signal V1 according to whether the third voltage signal V3 reaches a desired value.

The first voltage follower 30 may be an operational amplifier, and an output end of the controller 10 is connected to a positive input end of the operational amplifier, and an output end of the operational amplifier is coupled to an input end of the constant current source 20 and a negative input end of the controller 10 and the operational amplifier.

It will be appreciated that the first voltage signal V1 output by the controller 10 needs to be adjusted, because the output of the controller 10 has a certain error, the a/D module of the controller 10 is used to collect the value of the third voltage signal V3 output by the operational amplifier (i.e. the first voltage follower 30), and the value of the first voltage signal V1 is transmitted to the controller 10 to perform a closed-loop control. For example, the controller 10 theoretically outputs a first voltage signal V1 of 2V, the a/D module of the actual controller 10 collects a third voltage signal V3 of 1.95V at the output end of the first voltage follower 30, and the controller 10 performs closed-loop adjustment to make the first voltage signal V1 output by the controller 10 be 2V. It should be noted that the a/D module of the controller 10 collects the third voltage signal V3 and the second voltage signal V2 or the divided voltage value thereof through different ADC channels.

Further, in the present embodiment, the first voltage follower 30 can make the first voltage signal V1 output by the controller 10 perform closed-loop adjustment, so as to improve the stability of the output first voltage signal V1.

Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a resistance detection circuit provided in the present application. The resistance detection circuit 100 includes: a controller 10, a constant current source 20, a second voltage follower 40, a fifth resistor R5 and a sixth resistor R6.

Wherein the input terminal of the second voltage follower 40 is coupled to the port of the device under test 200.

The first end of the fifth resistor R5 is coupled to the output end of the second voltage follower 40, and the second end of the fifth resistor R5 is coupled to the input end of the controller 10.

The first end of the sixth resistor R6 is coupled to the second end of the fifth resistor R5, and the second end of the sixth resistor R6 is grounded.

The voltage signal at the input end of the controller 10 is the second voltage signal V2 or the divided voltage value of the second voltage signal V2. In some embodiments, the second voltage signal V2 of the port of the device under test 200 is collected by the analog-to-digital conversion module a/D of the controller 10 via the second voltage follower 40 (or directly without the second voltage follower 40); in other embodiments, the second voltage signal V2 at the port of the device under test 200 is collected by the analog-to-digital conversion module a/D of the controller 10 through the voltage divider value of the fifth resistor R5 and the sixth resistor R6 after passing through the second voltage follower 40 (or without passing through the second voltage follower 40).

wherein R is _{Upper part} To pull up the resistor, V ₁ Is the voltage value of the first voltage signal, V ₂ Is the voltage value of the second voltage signal, V _DD R is the supply voltage of the device under test 200 _gain Is a gain resistor R _gain Is a resistance value of (a). R is R ₅ A resistance value of the fifth resistor R5, R ₆ The resistance value of the sixth resistor R6.

Alternatively, the controller 10 may calculate the resistance value of the port of the device under test 200 using the following formula:

wherein R is _{Lower part(s)} Is a pull-down resistor.

In the present embodiment, further, the input impedance is made smaller by the second voltage follower 40, the driving capability is increased, and further, the voltage dividing operation is performed by the fifth resistor R5 and the sixth resistor R6.

Referring to fig. 10, fig. 10 is a schematic structural diagram of another embodiment of a resistance detection circuit provided in the present application. The resistance detection circuit 100 includes: the controller 10, the constant current source 20, the third operational amplifier opa3, the fourth operational amplifier opa4, the fifth resistor R5, and the sixth resistor R6.

Wherein the constant current source 20 includes: first operational amplifier opal, gain resistor R _gain A first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, A second operational amplifier opa2 and a capacitor C1.

The non-inverting input terminal of the third operational amplifier opa3 is connected to the controller 10, and is configured to receive the first voltage signal input by the controller 10.

The negative phase input terminal of the third operational amplifier opa3 is connected to the output terminal of the third operational amplifier opa 3.

The output end of the third operational amplifier opa3 is connected to the controller 10 for feeding back the voltage signal to the control end.

The first end of the first resistor R1 is coupled to the output end of the third operational amplifier opa3, and the second end of the first resistor R1 is coupled to the non-inverting input end of the first operational amplifier opa.

The first end of the capacitor C1 is coupled to the first end of the fourth resistor R4, and the second end of the capacitor C1 is coupled to the second end of the fourth resistor R4.

The non-inverting input of the fourth operational amplifier opa4 is coupled to the port of the device under test 200.

The first end of the fifth resistor R5 is coupled to the output end of the fourth operational amplifier opa4, and the second end of the fifth resistor R5 is coupled to the input end of the controller 10.

The fourth operational amplifier opa4 has a function of voltage follower to reduce input impedance and increase driving capability.

The third operational amplifier opa3 forms a negative feedback path of the operational amplifier, which can adjust the output of the controller 10, so that the constant current source 20 works more stably.

A first operational amplifier opal and a gain resistor R in the constant current source 20 _gain The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the second operational amplifier opa2 form a negative feedback path, wherein the resistors are all 0.1% accurate, and the R1/r2=r3/R4, and the capacitor C1 provides high-frequency compensation for the operational amplifier.

In addition, the second terminal of the fifth resistor R5 is coupled to the input terminal of the controller 10, and can provide the divided value of the second voltage signal V2 to the controller 10. And the magnitude of the gain resistor can be adjusted through the second voltage signal, so that automatic gear shifting measurement is realized.

It will be appreciated that in the controller 10 there is typically an analog to digital converter and a digital to analog converter. When the controller 10 outputs the first voltage signal, the digital signal of the controller 10 is converted into an analog signal by the digital-to-analog converter and output as the first voltage signal.

When the second voltage signal is input to the controller 10, the second voltage signal belonging to the analog signal is converted into a digital signal input by an analog-to-digital converter.

For example, an analog-to-digital converter of 12 bits, a full scale of 4096, and a value of 2200 to 2600 for the second voltage signal is considered to be an "intermediate value".

The fifth resistor R5 and the sixth resistor R6 are analog-to-digital converter input protection circuits. The voltage operating range of the analog-to-digital converter module inside the controller 10 is typically 0-3.3V. Therefore, voltage division can be performed using the fifth resistor R5 and the sixth resistor R6.

The resistance values of the fifth resistor R5 and the sixth resistor R6 may be equal. Namely, the pull-up resistor is calculated by:wherein V is ₃ The voltage of the fifth resistor R5 is shown.

The pull-down resistance calculation formula:

in this embodiment, the resistance detection circuit 100 uses the constant current source 20 to output a constant current signal to the port of the device under test 200 to detect the voltage signal of the port, and further uses the voltage signal to determine the resistance value of the port, such as the resistance value of the pull-up resistor or the pull-down resistor of the port of the device under test 200, so as to improve the measurement efficiency of the resistance value of the port of the device under test 200 and simplify the detection flow. Wherein the current value of the current signal output by the constant current source 20 is not changed due to the port access of the device under test 200; the controller 10 can adjust the gain resistance R of the constant current source 20 by adjusting _gain The second voltage signal V2 of the port of the device to be tested is adjusted to be within the preset range, so that the automatic matching of the resistance value of the port of the device to be tested and the preset voltage range of the controller 10 (for example, the full-scale intermediate value range of the analog-to-digital conversion module a/D of the controller 10) is realized, the measurement efficiency is further improved, and the detection flow is simplified.

Referring to fig. 11, fig. 11 is a schematic structural diagram of an embodiment of a portable resistor detection device provided in the present application. The portable resistance detection apparatus 1000 includes a resistance detection circuit 100.

The resistance detection circuit 100 may be the resistance detection circuit 100 in any of the above embodiments.

In other embodiments, the portable resistance detection device 1000 further includes a display screen (not shown). The resistance value of the port of the device under test 200 may be displayed by a display screen.

In one scenario, referring to fig. 12, first, the portable resistor detection device 1000 is powered on, then a program in the portable resistor detection device 1000 is initialized, and after the initialization is completed, the controller 10 of the resistor detection circuit 100 in the portable resistor detection device 1000 controls the digital switch 50 to configure the maximum gain resistor R _gain . Then detecting the port to be tested of the device to be tested, and reading the second voltage signal V ₂ Judging the second voltage signal V ₂ Whether the value of (c) is an intermediate value. If yes, calculating the resistance of the port to be testedAnd performing a reset operation after the calculation is completed. If not, the controller 10 outputs corresponding control signals at general purpose input/output terminals (GPIO 0-GPIO) to change the gain resistance R _gain And then detecting the port to be detected again, and adjusting the voltage value of the second voltage signal V2 within a preset range or adjusting the voltage value of the second voltage signal V2 or the partial voltage value thereof within a set proportion range of a preset maximum voltage value in the cycle.

After the voltage value of the second voltage signal V2 is adjusted within the preset range, the accurate second voltage signal V2 can be read. And then obtaining the resistance value of the pull-up or pull-down resistor of the port to be tested according to the second voltage signal V2.

Since there is also a range of numerical readings within the controller, readings beyond the range are inaccurate. For example, the maximum value is read, and it is not known at this time, because the limitation of the hardware itself can only read the maximum value corresponding to the hardware, or the value of the voltage signal.

Therefore, the intermediate value is set to determine the value of the voltage signal so as to improve the detection accuracy.

In summary, the resistor detection circuit and the portable resistor detection device provided by the application can automatically match and measure the numerical value of the internal pull-up resistor or the internal pull-down resistor of the device to be detected, thereby improving the working efficiency and simplifying the test flow.

In the several embodiments provided in the present application, it should be understood that the disclosed methods and apparatuses may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed.

The integrated units of the other embodiments described above may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as stand alone products. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.

Claims

1. A resistance detection circuit, the resistance detection circuit comprising:

the output end of the controller is used for outputting a first voltage signal, and the input end of the controller is used for being coupled with a port of a device to be tested;

the input end of the constant current source is coupled with the output end of the controller, and the output end of the constant current source is used for being coupled with the port of the device to be tested;

the constant current source outputs a constant current signal to the port of the device to be tested according to the first voltage signal, and the controller obtains a second voltage signal of the port of the device to be tested and determines the resistance value of the port of the device to be tested according to the second voltage signal.

2. The circuit for detecting resistance according to claim 1, wherein,

the constant current source includes:

a first operational amplifier;

A gain resistor, wherein a first end of the gain resistor is coupled with the output end of the first operational amplifier;

the first operational amplifier and the gain resistor form a feedback circuit, and the voltage value of the first voltage signal and the resistance value of the gain resistor determine the current value of the current signal, wherein the current value of the current signal does not change along with whether the port of the device to be tested is connected or not.

3. The resistance detection circuit according to claim 2, wherein,

the constant current source further includes:

a first resistor, a first end of which is coupled with the output end of the controller, and a second end of which is coupled with the non-inverting input end of the first operational amplifier;

a second resistor, wherein a first end of the second resistor is coupled with a non-inverting input end of the first operational amplifier;

a third resistor, a first end of which is grounded, and a second end of which is coupled to the inverting input end of the first operational amplifier;

a fourth resistor, wherein a first end of the fourth resistor is coupled to the inverting input end of the first operational amplifier, and a second end of the fourth resistor is coupled to the output end of the first operational amplifier;

The non-inverting input end of the second operational amplifier is coupled with the second end of the gain resistor, the inverting input end of the second operational amplifier is coupled with the output end of the second operational amplifier, and the output end of the second operational amplifier is coupled with the second end of the second resistor;

the second end of the gain resistor is used as an output end of the constant current source, and the first resistor, the second resistor, the third resistor and the fourth resistor meet the following conditions:

wherein R is ₁ A resistance value of the first resistor R ₂ The resistance value of the second resistor, R ₃ The resistance value of the third resistor, R ₄ The resistance value of the fourth resistor.

4. A resistance detection circuit according to claim 3, wherein,

the constant current source further includes:

and the first end of the capacitor is coupled with the first end of the fourth resistor, and the second end of the capacitor is coupled with the second end of the fourth resistor.

5. The resistance detection circuit according to claim 2, wherein,

6. The resistance detection circuit according to claim 5, wherein,

The gain resistor comprises a plurality of resistors;

the constant current source further comprises a digital switch, a plurality of input ends of the digital switch are coupled with a plurality of general input and output ends of the controller, each of a plurality of output ends of the digital switch is coupled with one of the plurality of resistors, and the digital switch is configured to control whether the plurality of resistors are connected or not according to a control signal output by the controller from the plurality of general input and output ends, so that the connection mode of the plurality of resistors is changed to change the resistance value of the gain resistor.

7. The resistance detection circuit according to claim 5, wherein,

the controller responds to the obtained voltage value of the second voltage signal within a set proportion range of a preset maximum voltage value, and determines the resistance value of the port of the device to be tested according to the second voltage signal; or (b)

And the controller responds to the obtained voltage value of the second voltage signal which is not in the set proportion range of the preset maximum voltage value, and adjusts the resistance value of the gain resistor.

8. The resistance detection circuit according to claim 5, wherein,

the resistance value of the gain resistor defaults to the maximum resistance value, and the controller responds to the voltage value of the second voltage signal or the set proportion range that the partial voltage value of the second voltage signal is lower than the preset maximum voltage value, so that the resistance value of the gain resistor is reduced; the controller responds to the voltage value of the second voltage signal or the set proportion range of which the voltage division value is higher than the preset maximum voltage value, and the resistance value of the gain resistor is adjusted to be high.

9. The resistance detection circuit according to claim 2, wherein,

the constant current source further includes:

a second resistor, wherein a first end of the second resistor is coupled to the non-inverting input end of the first operational amplifier, and a second end of the second resistor is coupled to the second end of the gain resistor;

wherein the first end of the gain resistor is used as the output end of the constant current source, and the gain resistor, the first resistor, the second resistor, the third resistor and the fourth resistor satisfy the following conditions:

10. The resistance detection circuit according to claim 2, wherein,

the controller calculates the resistance value of the port of the device under test based on the following formula:

or (b)

Wherein R is _{Upper part} The resistance of the port of the device to be tested is represented as a pull-up resistance, R _{Lower part(s)} The resistance of the port of the device to be tested is represented as pull-down resistance, V ₁ V is the voltage value of the first voltage signal ₂ V is the voltage value of the second voltage signal _DD R is the power supply voltage of the device to be tested _gain Is the resistance value of the gain resistor, wherein V _1/ R _gain Is the current value of the current signal.

11. The circuit for detecting resistance according to claim 1, wherein,

the controller further comprises a digital-to-analog conversion module and an analog-to-digital conversion module, wherein the controller controls the digital-to-analog conversion module to output the first voltage signal from the output end, and the controller obtains the second voltage signal or the partial pressure value of the second voltage signal from the input end through the analog-to-digital conversion module.

12. The circuit for detecting resistance according to claim 1, wherein,

The resistance detection circuit further comprises a first voltage follower, wherein the input end of the first voltage follower is coupled with the output end of the controller to receive the first voltage signal, the output end of the first voltage follower is coupled with the input end of the constant current source, and the controller further obtains a third voltage signal of the output end of the first voltage follower and adjusts the first voltage signal output by the controller according to whether the third voltage signal reaches a desired value or not.

13. The circuit for detecting resistance according to claim 1, wherein,

the resistance detection circuit further includes:

the input end of the second voltage follower is coupled with the port of the device to be tested;

a fifth resistor, a first end of which is coupled to the output end of the second voltage follower, and a second end of which is coupled to the input end of the controller;

a sixth resistor, a first end of the sixth resistor is coupled to a second end of the fifth resistor, a second end of the sixth resistor is grounded,

the voltage signal of the input end of the controller is the second voltage signal or the divided voltage value of the second voltage signal.

14. A portable resistance detection apparatus, characterized in that it comprises a resistance detection circuit according to any one of claims 1-13.