CN1173408C - Nitride read-only memory structure and mfg. method threrof - Google Patents
Nitride read-only memory structure and mfg. method threrof Download PDFInfo
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- CN1173408C CN1173408C CNB011361999A CN01136199A CN1173408C CN 1173408 C CN1173408 C CN 1173408C CN B011361999 A CNB011361999 A CN B011361999A CN 01136199 A CN01136199 A CN 01136199A CN 1173408 C CN1173408 C CN 1173408C
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- layer
- grid dielectric
- substrate
- oxide layer
- nitride
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- 238000000059 patterning Methods 0.000 claims description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 4
- XQMTUIZTZJXUFM-UHFFFAOYSA-N tetraethoxy silicate Chemical compound CCOO[Si](OOCC)(OOCC)OOCC XQMTUIZTZJXUFM-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 125000003963 dichloro group Chemical group Cl* 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000001272 nitrous oxide Substances 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 239000002131 composite material Substances 0.000 abstract 5
- 230000010354 integration Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000035755 proliferation Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 239000000428 dust Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229940090044 injection Drugs 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 210000001161 mammalian embryo Anatomy 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Semiconductor Memories (AREA)
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Abstract
The present invention relates to the structure of a nitride read-only memory and a manufacturing method thereof. The structure at least comprises a composite grid dielectric layer on a substrate, a silicon oxide layer on the surface of the composite grid dielectric layer, bit line oxide layers positioned on both sides of the composite grid dielectric layer and in the substrate, source/drain electrodes positioned under the bit line oxide layer and in the substrate, and a grid electrode crossing the composite grid dielectric layer and positioned on the bit line oxide layers, wherein the composite grid dielectric layer is composed of a bottom oxide layer, a silicon nitride layer and a top oxide layer, and the silicon oxide layer is made by deposition through a chemical vapor deposition technique. The present invention can reduce heat budget and reduce the transverse diffusion of the source/drain electrodes to increase the integration level of an integrated circuit.
Description
Technical field
The present invention relates to a kind of structure and manufacture method thereof of semiconductor subassembly, particularly about a kind of nitride ROM (nitride read only memory; NROM) structure and manufacture method thereof.
Background technology
Along with the lifting of integrated circuit technique and popularizing of information products application, make semiconductor subassembly become more and more important.Wherein memory is played the part of critical role in the application of information products, and the flash memory that particularly has superior data preservation characteristics becomes the main flow in non-volatility memorizer market gradually.Yet because the semiconductor subassembly live width dwindles day by day, based on the power saving design consider, the data signal bits standard falls progressively and the problems such as interference of outside noise, cause to write or when erasing data-signal, be not easy accurately to control the signal level of flash memory.In other words, can't in flash memory crystal cell, write the electronics or the electronics of erasing effectively.
The structure of typical nitride ROM is for to have bottom oxide, silicon nitride layer, top oxide layer and the formed stack architecture of conductor layer in regular turn in substrate, and a source/drain is respectively arranged in this stack architecture substrate on two sides, as the usefulness of bit line.In nitride ROM, silicon nitride layer is played the part of the floating grid (floating gate) of conventional flash memory, is used for storing the electric charge of representative " 0 " or " 1 ".Conductor layer is then played the part of the control gate (control gate) of conventional flash memory, as the usefulness of word line.
At United States Patent (USP) the 5th, in 966, No. 603, for the time and the bit line capacitance of the store charge that prolongs silicon nitride layer, form bit line oxidation layer (bit line oxide) on the surface of bit line (that is source/drain) with thermal oxidation method, and the part that comes out of the periphery of simultaneous oxidation silicon nitride layer.But this kind manufacture causes the serious horizontal proliferation of source/drain, makes the limit of the downsizing of assembly be subjected to suitable restriction.
Summary of the invention
In order to overcome the deficiencies in the prior art, main purpose of the present invention provides a kind of structure of nitride ROM, to increase the retention time of its stored data.
Another object of the present invention provides a kind of manufacture method of nitride ROM, to reduce the heat budget of its manufacture process.
Another purpose of the present invention provides a kind of manufacture method of nitride ROM, with the horizontal proliferation of limits source/drain electrode.
According to above-mentioned purpose of the present invention, a kind of structure of nitride ROM is proposed, source/drain that this structure comprises the silicon oxide layer, the bit line oxidation layer that is positioned at the both sides substrate of the multiple layer of grid dielectric that are arranged in the multiple layer of suprabasil grid dielectric, are arranged in grid dielectric clad surface at least, be positioned at the below substrate of bit line oxidation layer and the grid that crosses on the multiple layer of grid dielectric and the bit line oxidation layer.Wherein the multiple layer of grid dielectric is made up of bottom oxide, silicon nitride layer and top oxide layer, and silicon oxide layer is deposited by chemical vapour deposition technique to form.
And the manufacture method of above-mentioned nitride ROM structure is included at least and forms bottom oxide, silicon nitride layer and top oxide layer in the substrate in regular turn, and patterning top oxide layer, silicon nitride layer and bottom oxide are to form the multiple layer of grid dielectric then.Be mask then with the multiple layer of grid dielectric, inject ion in substrate to form the both sides substrate of source/drain in the multiple layer of grid dielectric.With chemical vapour deposition technique conformal silicon oxide layer of deposition on the multiple layer of grid dielectric and source/drain, carry out again thermal oxidation method with oxidation not by the surface of multiple layer of this substrate that is covered of grid dielectric to form a plurality of bit line oxidation layers.Form to cross over the grid on the multiple layer of grid dielectric and the source/drain then.
According to a preferred embodiment of the present invention, the silicon oxide layer of the multiple layer of above-mentioned covering gate dielectric is preferably high temperature oxide layer (high-temperature-oxide; HTO).
As mentioned above, the surface coverage of layer is answered the grid dielectric with the silicon oxide layer that chemical vapour deposition technique was deposited in utilization of the present invention.So when forming the grid that crosses the multiple layer of grid dielectric, grid can directly not contact with the silicon nitride layer of the multiple layer of grid dielectric, causes the flow of charge that stores in silicon nitride layer to come out.So can increase the time of the multiple layer of grid dielectric storage data, guarantee the stability of storage data.In addition, because the formation method of the silicon oxide layer of the multiple layer of covering gate dielectric is a chemical vapour deposition technique, thus can reduce heat budget, and reduce the horizontal proliferation of source/drain, to increase the integrated level of integrated circuit.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Figure 1A-1E is the manufacturing process profile according to a kind of nitride ROM of a preferred embodiment of the present invention.
Symbol description among the figure
100 substrates
110,115 bottom oxides
120,125 silicon nitride layers
130,135 top oxide layers
140 source/drains
150 silicon oxide layers
160 bit line oxidation layers
170 grids
Embodiment
Please refer to Figure 1A-1E, it illustrates the manufacturing process profile according to a kind of nitride ROM of a preferred embodiment of the present invention.
In Figure 1A, in substrate 100, form bottom oxide 110, silicon nitride layer 120 and top oxide layer 130 in regular turn.Wherein bottom oxide 110 is preferably and uses thermal oxidation method to form, and silicon nitride layer 120 is preferably and uses Low Pressure Chemical Vapor Deposition to form.And then carry out thermal oxidation method the top layer of silicon nitride layer 120 is oxidized to top oxide layer 130, so the embryo deposit thickness of silicon nitride layer 120 must be thicker, the part that was depleted because of oxidation afterwards with compensation.And the thickness of the silicon nitride layer 120 after bottom oxide 110 and 130 formation of top oxide layer, preferable 50-90 dust and the 40-70 dust of being about respectively.
In Figure 1B, carry out photoetching process and come patterning top oxide layer 130, silicon nitride layer 120 and bottom oxide 110 to form the multiple layer of grid dielectric, the multiple layer of grid dielectric is made up of with top oxide layer 135 bottom oxide 115, silicon nitride layer 125.Be mask with the multiple layer of grid dielectric then, ion carried out in the substrate 100 that exposes inject to form the usefulness of source/drain 140 as bit line.
In Fig. 1 C, with conformal (conformal) silicon oxide layer 150 of chemical vapour deposition technique deposition one deck.Silicon oxide layer 150 is preferably high temperature oxide layer, and its formation method for example for using Low Pressure Chemical Vapor Deposition to deposit, can be used tetraethoxy silicate (tetraethoxysilicate; TEOS)/oxygen or dichloro silicomethane (SiH
2Cl
2)/nitrous oxide (N
2O) under 600-750 degree Celsius, deposit.Silicon oxide layer 150 and top oxide layer 135 thickness altogether are example to cooperate the above-mentioned end silicon oxide layer 110 and the thickness (asking for an interview the explanation of Figure 1A) of silicon nitride layer 120, the preferable 70-100 dust that is about.
In Fig. 1 D, carry out thermal oxidation method with substrate 100 surfaces that oxidation is not covered by the multiple layer of grid dielectric, form bit line oxidation layer 160.Because the oxidized silicon layer 150 of the periphery of silicon nitride layer 125 covers, so the periphery that this step of thermal oxidation does not need to spend the extra time to guarantee silicon nitride layer 125 is gone out one deck silicon oxide layer by thermal oxidation, therefore can limit the horizontal proliferation (lateral diffusion) of source/drain 140.
In Fig. 1 E, form conductor layer, carry out lithography step again so that its patterning is formed grid 170.The trend of the trend of grid 170 and source/drain 140 (that is bit line) is mutually perpendicular.The material of conductor layer for example can be polysilicon or multi-crystal silicification metal (polycide), and its formation method for example can be chemical vapour deposition technique.
By the invention described above preferred embodiment as can be known, utilization of the present invention is got up the surface coverage of the multiple layer of grid dielectric with the formed silicon oxide layer of chemical vapour deposition technique.So when forming the grid that crosses the multiple layer of grid dielectric, grid can directly not contact with the silicon nitride layer of the multiple layer of grid dielectric, causes the flow of charge that stores in silicon nitride layer to come out.So can increase the time of the multiple layer of grid dielectric storage data, guarantee the stability of storage data.In addition because the formation method of the silicon oxide layer of the multiple layer of covering gate dielectric is a chemical vapour deposition technique, so can reduce heat budget and reduce the integrated level of the horizontal proliferation of source/drain with the increase integrated circuit.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, thus protection scope of the present invention when with claims and in conjunction with specification and accompanying drawing the person of being defined be as the criterion.
Claims (9)
1. the structure of a nitride ROM, this structure comprises at least:
The multiple layer of one grid dielectric is positioned in the substrate, and the multiple layer of this grid dielectric is made up of a bottom oxide, a silicon nitride layer and a top oxide layer;
Conformal one silica layer is positioned at the surface of the multiple layer of this grid dielectric;
Two bit line oxidation layers are arranged in this substrate of both sides of the multiple layer of this grid dielectric;
Two source/drains lay respectively in this substrate of both sides of those bit line oxidation layer belows; And
One grid is crossed on the multiple layer of this grid dielectric and this two bit line oxidations layer.
2. the structure of nitride ROM according to claim 1, it is characterized in that: this silicon oxide layer is with the formed silicon oxide layer of chemical vapour deposition technique.
3. the structure of nitride ROM according to claim 1, it is characterized in that: this silicon oxide layer comprises a high temperature oxide layer.
4. the manufacture method of a nitride ROM, this method comprises at least:
Form a bottom oxide in a substrate;
Form a silicon nitride layer on this silicon oxide layer;
Form a top oxide layer on this silicon nitride layer;
This top oxide layer of patterning, this silicon nitride layer and this bottom oxide are to form the multiple layer of a grid dielectric;
With the multiple layer of this grid dielectric is mask, injects ion in this substrate, to form two source/drains in this substrate of both sides of the multiple layer of this grid dielectric;
Deposit conformal one silica layer on the multiple layer of this grid dielectric and this source/drain;
Carry out thermal oxidation method and do not answered layer surface of this substrate that is covered to form a plurality of bit line oxidation layers by this grid dielectric with oxidation;
Form a conductive layer in this substrate; And
This conductive layer of patterning is crossed on the multiple layer of this grid dielectric and this source/drain to form a grid.
5. the manufacture method of nitride ROM according to claim 4, it is characterized in that: the method that forms this silicon oxide layer comprises chemical vapour deposition technique.
6. the manufacture method of nitride ROM according to claim 5, it is characterized in that: the used reacting gas of this chemical vapour deposition technique comprises tetraethoxy silicate and oxygen.
7. the manufacture method of nitride ROM according to claim 5, it is characterized in that: the used reacting gas of this chemical vapour deposition technique comprises dichloro silicomethane and nitrous oxide.
8. the manufacture method of nitride ROM according to claim 4, it is characterized in that: this conductive layer comprises with the formed polysilicon layer of chemical vapour deposition technique.
9. the manufacture method of nitride ROM according to claim 4, it is characterized in that: this conductive layer comprises with the formed multi-crystal silicification metal of chemical vapour deposition technique.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011361999A CN1173408C (en) | 2001-11-21 | 2001-11-21 | Nitride read-only memory structure and mfg. method threrof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011361999A CN1173408C (en) | 2001-11-21 | 2001-11-21 | Nitride read-only memory structure and mfg. method threrof |
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| Publication Number | Publication Date |
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| CN1420567A CN1420567A (en) | 2003-05-28 |
| CN1173408C true CN1173408C (en) | 2004-10-27 |
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Granted publication date: 20041027 Termination date: 20191121 |