CN117337425A

CN117337425A - Storage device, method and electronic equipment

Info

Publication number: CN117337425A
Application number: CN202180098434.8A
Authority: CN
Inventors: 郭林; 秦军杰; 杨庭坚
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-07-08
Filing date: 2021-07-08
Publication date: 2024-01-02
Also published as: WO2023279334A1

Abstract

The application relates to a storage device, a method and an electronic device, wherein the storage device comprises a controller and a first memory, the first memory comprises a plurality of magnetic disks, the controller comprises a second memory for caching data, and the controller is configured to: generating a virtual address corresponding to the first address information according to the first address information of the first data to be operated and the category of the target disk; generating an operation instruction according to the virtual address; sending an operation instruction to a target disk so that the target disk generates an address reading instruction aiming at the virtual address; and under the condition that an address reading instruction sent by the target disk is received, performing data interaction with the target disk according to the first address information corresponding to the virtual address. The embodiment of the application can simplify the address management in the storage device through address virtualization, thereby improving the processing efficiency.

Description

Storage device, method and electronic equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a storage device, a method, and an electronic apparatus.

Background

A disk array (redundant array of independent disks, RAID) is a large capacity disk set made up of multiple individual disks that provides better storage performance than a single hard disk. Disk arrays are typically managed by array cards (which may also be referred to as RAID cards, disk array cards, etc.).

The data management protocols supported by different disks in a disk array may differ, as may the address description schemes supported by different data management protocols. In the case where the disks in the disk array support multiple address description schemes, there may be mixed complex address management inside the array card, which affects the processing efficiency of the disk array, such as input/output (I/O) efficiency.

Disclosure of Invention

In view of this, a storage device, a method and an electronic apparatus are provided.

In a first aspect, embodiments of the present application provide a storage device including a controller and a first memory, the first memory including a plurality of disks, the controller including a second memory for caching data, the controller configured to: generating a virtual address corresponding to first address information according to the first address information of first data to be operated and the category of a target disk, wherein the first address information is used for indicating the physical address of the first data in the second memory, the target disk is at least one of the plurality of disks, and the virtual address comprises an identifier of the first address information; generating an operation instruction according to the virtual address; sending the operation instruction to the target disk so as to enable the target disk to generate an address reading instruction aiming at the virtual address; and under the condition that the address reading instruction sent by the target disk is received, carrying out data interaction with the target disk according to the first address information corresponding to the virtual address.

The storage device of the embodiment of the invention comprises a controller and a first memory, wherein the controller can generate a virtual address corresponding to first address information according to the first address information of first data to be operated (part of data or all data in second data) and the category of a target disk, then generate and send an operation instruction to the target disk in the first memory according to the virtual address, the target disk generates and sends an address reading instruction for the virtual address under the condition that the operation instruction sent by the controller is received, and the controller performs data interaction with the target disk under the condition that the address reading instruction sent by the target disk is received, so that the address information of the data to be operated (namely the physical address of the data to be operated in the second memory) can be virtualized according to the first address information corresponding to the virtual address, the corresponding virtual address is obtained, and the virtual address is used in the instruction (or command) interaction process of the controller and the target disk, so that the address information in the storage device is virtualized and normalized, and the address management in the storage device is simplified, and the processing efficiency of the storage device is improved.

In a first possible implementation manner of the storage device according to the first aspect, the controller is connected to a host, and the controller is further configured to: under the condition that a data writing instruction for second data sent by the host is received, according to second address information of the second data in the data writing instruction, caching the second data into the second memory, wherein the data writing instruction is used for instructing the controller to write the second data into the first memory; and determining first address information of first data to be operated according to third address information of the second data in the second memory, wherein the first data are part of or all of the second data.

In the embodiment of the application, when receiving the data writing instruction for the second data sent by the host, the controller of the storage device caches the second data into the second memory according to the second address information of the second data in the data writing instruction, and determines the first address information of the first data to be operated (part of the data or all the data in the second data) according to the third address information of the second data in the second memory, so that the second data is cached through the second memory of the controller during data writing, the spatial distribution of the second data can be recombined in the second memory, the dispersity of the second data can be reduced, the address information can be managed in a unified address description mode inside the controller, and the complexity of address management inside the controller can be reduced.

In a second possible implementation form of the storage device according to the first possible implementation form of the first aspect, the controller is further configured to: under the condition that a data reading instruction for third data sent by the host is received, according to the length of the third data, a buffer space is allocated for the third data in the second memory, the data reading instruction is used for instructing the controller to read the third data from the first memory, and the buffer space is used for buffering the third data in the controller; and determining first address information of first data to be operated according to fourth address information of the cache space, wherein the first data is part of or all of the third data.

In the embodiment of the application, the controller of the storage device can apply for a buffer space in the second memory for the third data to be read according to the length of the third data under the condition that a data reading instruction for the third data sent by the host is received, and determine the first address information of the first data to be operated (part of the data or all the data in the third data) according to the fourth address information of the buffer space, so that the buffer space can be allocated in the controller for the third data to be read in advance, the controller can uniformly manage the address information of the data which is read from the first memory and is buffered in the second memory, and the complexity of address management in the controller is reduced.

In a third possible implementation manner of the storage device according to the second possible implementation manner of the first aspect, an address description manner of the second address information is any one of a physical area page PRP, a scatter aggregation table SGL, and a scatter aggregation element SGE, an address description manner of the first address information, the third address information, and the fourth address information is PRP, and a class of the target disk is any one of a PRP class, an SGL class, and an SGE class.

In the embodiment of the present application, the first address information, the third address information and the fourth address information inside the controller adopt a unified address description manner PRP, and the address description manner of the second address information from the host is any one of PRP, SGL, SGE, and the class of the target disk is any one of PRP class, SGL class and SGE class. In this way, the controller of the storage device not only can receive address information with different address description modes from the host and interact with different types of target disks, but also can manage the address information inside the storage device in a unified address description mode (PRP), so that the controller of the storage device can realize unified management of the internal address information without influencing external interaction.

In a fourth possible implementation manner of the storage device according to the first possible implementation manner of the first aspect, the determining the first address information of the first data according to the third address information of the second data in the second memory includes: and when the first data is part of the second data, determining the first address information of the first data according to third address information, the length of the first data and a starting position offset, wherein the starting position offset is used for indicating the offset of the starting position of the first data relative to the starting position of the second data.

In the embodiment of the present application, in the case where the first data to be operated is part of the second data, the first data to be processed needs to be split from the second data. The first address information of the first data may be determined according to third address information of the second data in the second memory, a length of the first data, a start position offset, and the like. By the method, the first address information of the first data can be rapidly and accurately determined under the condition that the first data is part of the second data, so that the second data can be written in blocks or downloaded.

In a fifth possible implementation manner of the storage device according to the first possible implementation manner of the first aspect, the determining, according to third address information of the second data in the second memory, first address information of the first data includes: and when the first data is all data in the second data, determining third address information of the second data as first address information of the first data.

In the embodiment of the application, when the first data to be operated is all data in the second data, that is, when the second data is written in the whole or is downloaded, the third address information of the second data in the second memory can be directly determined as the first address information of the first data, so that the method and the device are simple and quick, and the processing efficiency can be improved.

In a sixth possible implementation form of the storage device according to any of the first possible implementation forms of the first aspect to the fifth possible implementation form of the first aspect, the controller is further configured to: and determining that the first data is all data in the second data under the condition that the length of the first data is the same as that of the second data and the initial position offset of the first data is equal to 0.

In the embodiment of the application, whether the first data is all data or part of data in the second data is judged through the length of the data and the initial position offset, and under the condition that the length of the first data is the same as the length of the second data and the initial position offset of the first data is equal to 0, the first data is determined to be all data in the second data, so that the processing efficiency can be improved simply, quickly and accurately.

In a seventh possible implementation form of the storage device according to any of the first possible implementation form of the first aspect to the sixth possible implementation form of the first aspect, the controller is further configured to: and determining that the first data is part of the second data when the length of the first data is different from the length of the second data or the initial position deviation of the first data is not equal to 0.

In the embodiment of the application, whether the first data is all data or part of data in the second data is judged through the length and the initial position offset of the data, and the first data is determined to be part of the data in the second data under the condition that the length of the first data is different from the length of the second data or the initial position offset of the first data is not equal to 0, so that the processing efficiency can be improved.

In an eighth possible implementation manner of the storage device according to the first aspect or any one of the first possible implementation manners of the first aspect to the seventh possible implementation manner of the first aspect, the performing data interaction with the target disk according to the first address information corresponding to the virtual address includes: under the condition that the address description mode of the first address information is not matched with the category of the target disk, converting the first address information according to the category of the target disk to obtain target address information; and carrying out data interaction with the target disk according to the target address information.

In the embodiment of the application, when the address description mode of the first address information corresponding to the virtual address is not matched with the type of the target magnetic disk, the controller converts the first address information according to the type of the target magnetic disk to obtain the target address information, and performs data interaction with the target magnetic disk according to the target address information, so that the controller and the target magnetic disk can perform data interaction under the condition that the target address information is matched with the type of the target magnetic disk.

In a ninth possible implementation manner of the storage device according to the first aspect or any one of the first possible implementation manners of the first aspect to the seventh possible implementation manner of the first aspect, the performing data interaction with the target disk according to the first address information corresponding to the virtual address includes: and under the condition that the address description mode of the first address information is matched with the category of the target disk, carrying out data interaction with the target disk by taking the first address information as target address information.

In the embodiment of the application, when the address description mode of the first address information corresponding to the virtual address is matched with the type of the target disk, the first address information is directly used as the target address information to perform data interaction with the target disk, and address conversion is not needed, so that the processing efficiency can be improved.

In a second aspect, embodiments of the present application provide a storage method applied to a controller in a storage device, the storage device further including a first memory including a plurality of disks, the controller including a second memory for caching data, the method including: generating a virtual address corresponding to first address information according to the first address information of first data to be operated and the category of a target disk, wherein the first address information is used for indicating the physical address of the first data in the second memory, the target disk is at least one of the plurality of disks, and the virtual address comprises an identifier of the first address information; generating an operation instruction according to the virtual address; sending the operation instruction to the target disk so as to enable the target disk to generate an address reading instruction aiming at the virtual address; and under the condition that the address reading instruction sent by the target disk is received, carrying out data interaction with the target disk according to the first address information corresponding to the virtual address.

According to the embodiment of the application, the virtual address corresponding to the first address information can be generated according to the first address information of the first data to be operated (part of the data or all the data in the second data) and the category of the target disk, then the operation instruction is generated and sent to the target disk in the first memory according to the virtual address, the address reading instruction aiming at the virtual address is generated and sent to the controller when the operation instruction sent by the controller is received by the target disk, and the controller performs data interaction with the target disk according to the first address information corresponding to the virtual address when the address reading instruction sent by the target disk is received by the controller, so that the address information of the data to be operated (namely the physical address of the data to be operated in the second memory) can be virtualized to obtain the corresponding virtual address, and the virtual address is used in the instruction (or command) interaction process of the controller and the target disk, so that the address information management virtualization and normalization inside the storage device are simplified, and the processing efficiency of the storage device is improved.

In a first possible implementation manner of the storage method according to the second aspect, the controller is connected to a host, and the method further includes: under the condition that a data writing instruction for second data sent by the host is received, according to second address information of the second data in the data writing instruction, caching the second data into the second memory, wherein the data writing instruction is used for instructing the controller to write the second data into the first memory; and determining first address information of first data to be operated according to third address information of the second data in the second memory, wherein the first data are part of or all of the second data.

In the embodiment of the application, under the condition that the data writing instruction sent by the host computer and aiming at the second data is received, the second data can be cached to the second memory according to the second address information of the second data in the data writing instruction, and the first address information of the first data (part of the data or all the data in the second data) to be operated is determined according to the third address information of the second data in the second memory, so that the second data is cached through the second memory of the controller during data writing, the spatial distribution of the second data can be recombined in the second memory, the dispersity of the second data is reduced, the address information can be managed in a unified address description mode in the controller, and the complexity of address management in the controller is reduced.

In a second possible implementation manner of the storing method according to the first possible implementation manner of the second aspect, the method further includes: under the condition that a data reading instruction for third data sent by the host is received, according to the length of the third data, a buffer space is allocated for the third data in the second memory, the data reading instruction is used for instructing the controller to read the third data from the first memory, and the buffer space is used for buffering the third data in the controller; and determining first address information of first data to be operated according to fourth address information of the cache space, wherein the first data is part of or all of the third data.

In the embodiment of the application, under the condition that the data reading instruction sent by the host for the third data is received, a buffer space can be applied for the third data to be read in the second memory according to the length of the third data, and the first address information of the first data to be operated (part of the data or all the data in the third data) is determined according to the fourth address information of the buffer space, so that the buffer space can be allocated in advance to the third data to be read in the controller, the controller can uniformly manage the address information of the data which is read from the first memory and is buffered in the second memory, and the complexity of address management in the controller is reduced.

According to a second possible implementation manner of the second aspect, in a third possible implementation manner of the storage method, an address description manner of the second address information is any one of a physical area page PRP, a scatter aggregation table SGL, and a scatter aggregation element SGE, an address description manner of the first address information, the third address information, and the fourth address information is PRP, and a class of the target disk is any one of a PRP class, an SGL class, and an SGE class.

In a fourth possible implementation manner of the storing method according to the first possible implementation manner of the second aspect, the determining the first address information of the first data according to the third address information of the second data in the second memory includes: and when the first data is part of the second data, determining the first address information of the first data according to third address information, the length of the first data and a starting position offset, wherein the starting position offset is used for indicating the offset of the starting position of the first data relative to the starting position of the second data.

In a fifth possible implementation manner of the storing method according to the first possible implementation manner of the second aspect, the determining the first address information of the first data according to the third address information of the second data in the second memory includes: and when the first data is all data in the second data, determining third address information of the second data as first address information of the first data.

In a sixth possible implementation manner of the storage method according to any one of the first possible implementation manner to the fifth possible implementation manner of the second aspect, the method further includes: and determining that the first data is all data in the second data under the condition that the length of the first data is the same as that of the second data and the initial position offset of the first data is equal to 0.

In a seventh possible implementation manner of the storage method according to any one of the first possible implementation manner to the sixth possible implementation manner of the second aspect, the method further includes: and determining that the first data is part of the second data when the length of the first data is different from the length of the second data or the initial position deviation of the first data is not equal to 0.

In an eighth possible implementation manner of the storage method according to the second aspect or any one of the first possible implementation manner to the seventh possible implementation manner of the second aspect, the performing data interaction with the target disk according to the first address information corresponding to the virtual address includes: under the condition that the address description mode of the first address information is not matched with the category of the target disk, converting the first address information according to the category of the target disk to obtain target address information; and carrying out data interaction with the target disk according to the target address information.

In the embodiment of the application, under the condition that the address description mode of the first address information corresponding to the virtual address is not matched with the type of the target disk, the controller converts the first address information according to the type of the target disk to obtain the target address information, and performs data interaction with the target disk according to the target address information, so that the controller and the target disk can perform data interaction under the condition that the target address information is matched with the type of the target disk.

In a ninth possible implementation manner of the storage method according to the second aspect or any one of the first possible implementation manner to the seventh possible implementation manner of the second aspect, the performing data interaction with the target disk according to the first address information corresponding to the virtual address includes: and under the condition that the address description mode of the first address information is matched with the category of the target disk, carrying out data interaction with the target disk by taking the first address information as target address information.

In a third aspect, embodiments of the present application provide an electronic device, including a processor, and a storage device connected to the processor, where the storage device is one or more of the foregoing first aspect or one or more possible implementations of the first aspect.

In this embodiment of the present invention, a controller of a storage device may generate a virtual address corresponding to the first address information according to the first address information of the first data to be operated (which is part of the second data or all of the second data) and a class of a target disk, and then generate and send an operation instruction to the target disk in the first memory according to the virtual address, where the target disk generates and sends an address reading instruction for the virtual address when receiving the operation instruction sent by the controller, and the controller performs data interaction with the target disk according to the first address information corresponding to the virtual address when receiving the address reading instruction sent by the target disk, thereby performing virtualization on the address information of the data to be operated (i.e. a physical address of the data to be operated in the second memory) to obtain a corresponding virtual address, and use the virtual address in an instruction (or command) interaction process between the controller and the target disk, so that the address information in the storage device is virtualized and normalized, and further address management in the storage device is simplified, and processing efficiency of the storage device is improved. .

These and other aspects of the application will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present application and together with the description, serve to explain the principles of the present application.

Fig. 1 shows a schematic diagram of an application scenario of a storage device according to an embodiment of the present application.

Fig. 2 shows a block diagram of a memory device according to an embodiment of the present application.

Fig. 3 shows a schematic diagram of a data writing process of a memory device according to an embodiment of the present application.

FIG. 4 illustrates a schematic diagram of a controller buffering data according to an embodiment of the present application.

FIG. 5 illustrates a schematic diagram of a controller buffering data according to an embodiment of the present application.

FIG. 6 illustrates a schematic diagram of a virtual address space according to an embodiment of the present application.

FIG. 7 illustrates a schematic diagram of virtual addresses according to an embodiment of the present application.

Fig. 8 shows a schematic diagram of a data reading process of a memory device according to an embodiment of the present application.

Fig. 9 shows a flow chart of a storage method according to an embodiment of the present application.

Detailed Description

Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present application. It will be understood by those skilled in the art that the present application may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits have not been described in detail as not to unnecessarily obscure the present application.

In the related art, the interaction of traffic data between a host and a disk array is typically performed through a RAID card (i.e., an array card). The process by which a RAID card interacts traffic data of a host with individual disks (also referred to as platters) in a disk array may be considered the back-end of the RAID card.

The data management of the back-end of a RAID card is typically associated with the data management protocols supported by the individual disks in the disk array. The data management protocol may be used to indicate a data interaction flow, an address description manner, etc. between the RAID card and the magnetic disk. Common data management protocols include non-volatile memory host controller interface Specification (non-volatile memory express, NVMe), serial attached Small computer System interface (serial attached small computer system interface, SAS), and the like. The address description mode supported by NVMe comprises a physical area page (physical region page, PRP), a scatter/gather list (SGL); the SAS supported address description includes a scatter/gather element (SGE) and the like.

In the case that the address description mode is PRP, address information used in the interaction process of the RAID card and the disk is represented by a PRP descriptor. Each PRP descriptor corresponds to a physical page (page) of a fixed size (e.g., 4 KB), and the PRP descriptor may be used to indicate a starting address of the physical page, an intra-page offset, etc., typically 8B in size.

And under the condition that the address description mode is SGL, the address information used in the interaction process of the RAID card and the disk is represented by SGL. The SGL includes at least one SGL segment that includes at least one SGL descriptor that may be used to indicate a starting address, a space size, etc. of a contiguous segment of physical space, typically 16B in size. The address description of the SGL supports chaining (i.e., multi-level linked list).

In the case that the address description mode is SGE, address information used in the interaction process of the RAID card and the disk is represented by an SGE descriptor. The SGE descriptor may be used to indicate the starting address of a contiguous piece of physical space, the size of the space, etc., which is typically 24B in size. Multiple SGE descriptors may be linked by pointers or the like to form a linked list. The address description mode of the SGE also supports chaining (i.e., multi-level linked list).

In the case where the disks in the disk array support multiple address description schemes, there are correspondingly multiple hybrid complex address management within the RAID card. For example, assume that the disk array includes 5 disks, where 1 disk supports an address description manner is PRP,3 disks support an address description manner is SGL, and the remaining 1 disk supports an address description manner is SGE, and accordingly, there are three kinds of mixed complex address management corresponding to PRP, SGL, SGE inside the RAID card. The complex address management mixed in the RAID card affects the processing efficiency of the RAID card, and further affects the processing efficiency of the disk array, for example, I/O efficiency.

In order to solve the technical problems, the application provides a storage device. The storage device of the embodiment of the application comprises a controller and a first memory, wherein the first memory comprises a plurality of magnetic disks, and the controller comprises a second memory for caching data. The controller of the storage device can cache the data to be operated through the second memory, can virtualize address information of the data to be operated (namely, the physical address of the data to be operated in the second memory) to obtain a corresponding virtual address, and uses the virtual address in the interaction process of the controller and the instruction (or command) of the first memory, so that the internal address management of the storage device is virtualized and normalized, the internal address management of the storage device is simplified, and the processing efficiency of the storage device is improved.

Fig. 1 shows a schematic diagram of an application scenario of a storage device according to an embodiment of the present application. As shown in fig. 1, the storage device 200 includes a controller 210 and a first memory 220, and the controller 210 is connected to the host 100. The host 100 may perform data operations, such as data writing, data reading, etc., on the storage device 200.

In some embodiments, host 100 may be any form of electronic device, such as a server, desktop computer, mainframe computer, and any other type of computing device. In this embodiment, the storage device 200 is located outside the host 100.

In some embodiments, host 100 may be a processor in an electronic device. The processor may include one or more processing units, such as: the processors may include application processors (application processor, AP), modem processors, graphics processors (graphics processing unit, GPU), image signal processors (image signal processor, ISP), controllers, video codecs, digital signal processors (digital signal processor, DSP), baseband processors, and/or neural network processors (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors. In this embodiment, the storage device 200 may be located inside the electronic device to which the processor belongs, or may be located outside the electronic device to which the processor belongs, which is not limited in this application.

In some embodiments, the storage device 200 may be a disk array, the controller 210 in the storage device 200 may be an array card (i.e., a RAID card) in the disk array, and the first memory 220 may be a storage medium in the disk array, including a plurality of disks or platters.

The controller 210 may be implemented by a central processing unit (central processing unit, CPU), an integrated circuit, or any other module capable of performing data processing, which is not limited in this application.

When the host 100 interacts with the storage device 200, the host 100 may send a data write instruction or a data read instruction to the controller 210 in the storage device 200; after receiving the data writing command or the data reading command sent by the host 100, the controller 210 may perform the related processing. For example, in case of receiving a data writing instruction transmitted from the host 100, the controller 210 may write data indicated by the data writing instruction into the first memory 210 of the storage device 200; in case of receiving a data read instruction transmitted from the host 100, the controller 210 may read data indicated by the data read instruction from the first memory 220 of the storage device 200 and transmit the read data to the host 100.

Fig. 2 shows a block diagram of a memory device according to an embodiment of the present application. As shown in fig. 2, the storage device 200 includes a controller 210 and a first memory 220 connected to the controller 210. The controller 210 includes a second memory 211, and the second memory 211 may be regarded as a cache/memory of the controller 210 for caching data; the first memory 220 includes a plurality of disks 221.

In one possible implementation, the classification of each disk in the first memory 220 may be determined according to the address description used during interaction of the disk 221 with the controller 210. For example, in the case where the address description manner used in the interaction of the disk 221 with the controller 210 is PRP, the class of the disk 221 may be determined as the PRP class; in the case where the address description manner used in the interaction of the disk 221 with the controller 210 is SGL, the class of the disk 221 may be determined as the SGL class; in the case where the address description manner used in the interaction of the disk 221 with the controller is SGE, the class of the disk 221 may be determined as the SGE class.

The processing procedure of the controller of the storage device will be exemplarily described below taking the data writing procedure and the data reading procedure of the storage device as examples, respectively.

Fig. 3 shows a schematic diagram of a data writing process of a memory device according to an embodiment of the present application. The data in the host that needs to be written to the storage device may be considered as second data. When writing the second data, the host may send a data writing instruction for the second data to the storage device, for instructing the controller of the storage device to write the second data to the first memory.

As shown in fig. 3, in the case of receiving a data write instruction for the second data sent by the host, the controller of the storage device may perform the following processing:

step S310, when a data writing instruction for second data sent by the host is received, according to second address information of the second data in the data writing instruction, caching the second data to the second memory.

The data writing instruction sent by the host to the controller may include second address information of second data that instructs the controller to write into the first memory, where the second address information may include at least one of a start address, a base address, an address offset, a data length, an address description mode, and the like of the second data. The address description mode of the second address information may be PRP or SGL, that is, the address description mode used in the interaction process of the host and the controller may be PRP or SGL. In some embodiments, the second address information may also be represented by SGE, or other address description, which is not limited in this application.

The controller may buffer the second data to the second memory according to second address information of the second data in the data writing instruction when receiving the data writing instruction for the second data sent by the host. That is, in the case of receiving a data write instruction for the second data sent by the host, the controller may first cache the second data, i.e., store the second data in the second memory (i.e., the local cache of the controller).

In one possible implementation, the address description mode supported inside the controller is PRP. After the second data is cached in the second memory, the address description mode is converted into PRP. For example, in the data writing instruction sent to the controller by the host, the address description mode of the second address information of the second data is SGL, and because the address description mode supported in the controller is PRP, after the controller caches the second data through the second memory, the address description mode of the second data is converted into PRP. It should be noted that, the address description manner supported in the controller may be SGL or other address description manners, which is not limited in this application.

FIG. 4 illustrates a schematic diagram of a controller buffering data according to an embodiment of the present application. As shown in FIG. 4, the cache 410 is located in the host and includes three cache areas 411, 412, and 413, each of which is 4KB in size. The cache 420 is located in the second memory of the controller and includes three cache areas 421, 422, and 423, each of which has a size of 4KB. The address description mode supported inside the controller is PRP.

The Data1 stored in the buffer 410 has a length of 7KB, and includes a Data block A1 (length of 2 KB), a Data block A2 (length of 4 KB), and a Data block A3 (length of 1 KB).

When the host needs to write the Data1 into the storage device, a Data writing instruction may be sent to the controller in the storage device, where the second address information of the Data1 in the Data writing instruction is represented by a PRP descriptor, as shown in table 1 below:

TABLE 1

PRP1	Offset！＝0
PRP2	Offset＝0
PRP3	Offset＝0

As shown in table 1, the second address information of the Data1 in the Data write instruction is represented by PRP descriptors PRP1, PRP2, and PRP3, and Offset represents an address Offset.

When receiving a Data write command for the Data1 transmitted from the host, the controller may read the Data1 from the cache 410 of the host according to the second address information of the Data1 shown in table 1, and store the read Data1 in the cache 420 of the controller.

As shown in fig. 4, the Data1 in the buffer 420 includes two Data blocks: the data block A1 'and the data block A2' are stored in the buffer areas 421 and 422, respectively. The address information of the Data1 in the buffer 420 may be represented by a PRP descriptor as shown in the following table 2:

TABLE 2

PRP4	Offset＝LBA Offset1
PRP5	Offset＝0

As shown in table 2, address information of the Data1 in the buffer 420 is represented by PRP descriptors PRP4, PRP 5. Where Offset represents the address Offset, LBA Offset1 represents the logical block address (logical block address, LBA) Offset of data block A1' in the cache area 421.

FIG. 5 illustrates a schematic diagram of a controller buffering data according to an embodiment of the present application. As shown in FIG. 5, cache 510 is located in the host, and includes three cache regions 511, 512, and 513, each of 4KB in size. The cache 520 is located in the second memory of the controller and includes three cache areas 521, 522, and 523, each of which has a size of 4KB. The address description mode supported inside the controller is PRP.

The Data2 stored in the buffer 510 has a length of 7KB, and includes a Data block B1 (3 KB in length), a Data block B2 (2.5 KB in length), and a Data block B3 (1.5 KB in length).

When the host needs to write the Data2 into the storage device, a Data writing instruction may be sent to the controller in the storage device, where the second address information of the Data2 in the Data writing instruction is represented by SGL as shown in table 3 below:

TABLE 3 Table 3

As shown in table 3, the second address information of the Data2 in the Data write instruction is represented by SGL1, SGL2, and SGL3, where Offset represents an address Offset, and Length represents a Data block Length.

When receiving a Data write command for the Data2 transmitted from the host, the controller may read the Data2 from the cache 510 of the host according to the second address information of the Data2 shown in table 3, and store the read Data2 in the cache 520 of the controller.

As shown in fig. 5, the Data2 in the buffer 520 includes two Data blocks: the data block B1 'and the data block B2' are stored in the buffer areas 521 and 522, respectively. The address information of the Data2 in the buffer 520 may be represented by PRP descriptors, as shown in table 4 below:

TABLE 4 Table 4

PRP6	Offset＝LBA Offset2
PRP7	Offset＝0

As shown in table 4, address information of the Data2 in the buffer 520 is represented by PRP descriptors PRP6, PRP 7. Where Offset represents the address Offset, LBA Offset2 represents the logical block address (logical block address, LBA) Offset of the data block B1' in the cache area 521.

In the above description, only fig. 4 and 5 are taken as examples, and the caching process of the second Data (Data 1 and Data 2) in the controller is described as an example, where the address description mode, the size of the second Data, the storage location, the address description mode, and the like supported in the controller are all examples. In practical applications, those skilled in the art may set the address description mode, the size of the second data, the storage location, the address description mode, etc. supported in the controller according to practical situations, which is not limited in this application.

Step S320, determining first address information of the first data to be operated according to the third address information of the second data in the second memory.

The first data is part of or all of the second data. The scenario where the first data is all of the second data may be: the controller writes the second data as a whole, i.e. the controller writes the second data to the second memory by a write operation (also called a write-down operation). The scenario where the first data is part of the second data may be: the controller splits the second data into a plurality of data blocks, and writes the data blocks respectively, namely the controller writes the second data into the second memory through a plurality of write operations.

In the data writing process, the controller may determine the first data to be operated according to a preset data operation rule (for example, a data blocking rule) of the storage device, and the like. The controller can preset a data blocking flag bit to indicate whether the second data is blocked, and then determine that the first data is part of or all of the second data according to the data blocking flag bit. The controller can also determine that the first data is part of or all of the second data in real time through judging the length, the initial position offset and the like of the data in the data writing process.

In one possible implementation, the controller may determine whether the first data is all or part of the second data according to the length of the data. For example, whether the length of the first data is the same as the length of the second data may be determined, and when the length of the first data is the same as the length of the second data, the first data may be regarded as all data in the second data; in the case where the length of the first data is smaller than the length of the second data, the first data may be regarded as part of the data in the second data.

In one possible implementation manner, the controller may also determine whether the first data is all or part of the second data according to the length of the data and the initial position offset of the data. The initial position offset is used for indicating the offset of the initial position of the first data relative to the initial position of the second data.

For example, it may be determined whether the length of the first data is the same as the length of the second data, and if the lengths are the same, it is determined whether the initial position shift of the first data is equal to 0, and if the initial position shift of the first data is equal to 0, the first data is considered to be all of the second data. Alternatively, it may be determined whether the initial position shift of the first data is equal to 0, and if the initial position shift of the first data is equal to 0, it is determined whether the length of the first data is the same as the length of the second data, and if the lengths of the first data and the second data are the same, the first data is considered to be all data in the second data.

That is, in the case where the length of the first data is the same as the length of the second data and the initial position deviation of the first data is equal to 0, the first data is determined to be all of the second data. When the length of the first data is different from the length of the second data or the initial position shift of the first data is not equal to 0, the first data may be regarded as part of the second data.

And the first data is judged to be all data or part data in the second data through the length of the data and the initial position deviation, so that the method is simple, quick and high in accuracy, and the processing efficiency can be improved.

After determining the first data to be operated, the controller may determine the first address information of the first data according to the third address information of the second data in the second memory. Wherein the third address information is operable to indicate a physical address of the second data in the second memory. The first address information may be used to indicate a physical address of the first data to be operated on in the second memory.

In the case that the first data to be operated is all data in the second data, namely, in the case of overall writing or downloading of the second data, the third address information of the second data in the second memory can be directly determined as the first address information of the first data, so that the method is simple and quick, and the processing efficiency can be improved.

In the case where the first data to be operated is part of the second data, the first data to be processed needs to be split from the second data. The first address information of the first data may be determined according to third address information of the second data in the second memory, a length of the first data, a start position offset, and the like. By the method, the first address information of the first data can be rapidly and accurately determined under the condition that the first data is part of the second data, so that the second data can be written in blocks or downloaded.

In one possible implementation, the first address information may be represented as a physical address of the first data, similar to the third address information. In the case that the first data to be operated is part of the second data, the first address information may also be represented as a conversion relationship between the physical address of the first data and the third address information by means of a conversion table, a data information table (data information table, DIT), or the like. The controller can acquire the physical address of the first data through real-time analysis of the conversion table or the data information table.

In one possible implementation manner, the address description manner of the third address information is an address description manner supported inside the controller, and the address description manner of the first address information is the same as the address description manner of the third address information. For example, assuming that the address description manner supported inside the controller is PRP, the address description manner of the third address information and the address description manner of the first address information are PRP.

Under the condition that a controller of the storage device receives a data writing instruction sent by a host for second data, the second data is cached to a second memory according to second address information of the second data in the data writing instruction, and first address information of first data (part of the data or all the data in the second data) to be operated is determined according to third address information of the second data in the second memory, so that when the data is written, the second data is cached through the second memory of the controller, the spatial distribution of the second data can be recombined in the second memory, the dispersity of the second data is reduced, the address information can be managed in a unified address description mode inside the controller, and the complexity of address management inside the controller is reduced.

In one possible implementation, the controller may preset an address storage space for storing address information, the address storage space being a real physical storage space. The controller may store third address information of the second data in the second memory to the address storage space. The controller may also store the first address information of the first data in the address storage space after determining the first address information of the first data to be operated. The size of the storage area occupied by each piece of address information in the address storage space may be a preset fixed size (for example, 64B, 128B, etc.), or may be set according to practical situations, which is not limited in this application. The address storage space may be located in the second memory of the controller, or may be located in another position of the controller, and a specific position of the address storage space may be set by a person skilled in the art according to actual situations, which is not limited in this application.

In one possible implementation, the first storage space may be managed in a similar manner as the memory management unit (memory management unit, MMU). For example, a corresponding address lookup table (address look up table, ALT) may be created in the address storage space for the first address information of the first data and the first address information of the first data may be stored in the address lookup table ALT. The size of the address lookup table ALT may be a predetermined size, for example 64B, 128B, etc. Alternatively, in the case where one level of ALT is not sufficient, multiple levels of ALT may be set according to the length of the first data, for example: three-level ALT comprising level 1 ALT, level 2 ALT and level 3 ALT.

It should be noted that, those skilled in the art may determine the number of levels of multi-level ALT in combination with practical situations such as addressing efficiency, cache consumption, etc., which is not limited in this application.

In one possible implementation, the controller may assign an identifier (key) as its unique identification to each piece of address information stored in the address storage space. That is, in the address storage space, a storage area storing the first address information (i.e., the address lookup table ALT) is associated with the first address information by the identifier key. For example, the start address of address lookup table ALT, which may store the first address information, is associated with a key of the first address information.

In the case that the address lookup table ALT is multi-level, the starting address of the level 1 ALT is used as an index entry to be associated with the key of the first address information, and the corresponding table entry is directly accessed by calculating the offset of each level ALT, so that the link is not required to be carried out according to a data management protocol (for example, NVMe), and the addressing efficiency can be improved.

The address storage space for storing the address information is preset in the cache (namely the second memory) of the controller, corresponding storage areas are allocated to each address information in the address storage space according to the preset size, and then each address information is stored in the corresponding storage area in the address storage space, so that the addressing efficiency can be improved, the occupied cache resources can be reduced, and the cache utilization rate can be improved.

Step S330, according to the first address information of the first data to be operated and the category of the target disk, generating a virtual address corresponding to the first address information.

The target disk is at least one of a plurality of disks of the first memory, and can be used for storing first data to be written (i.e. as a destination when the data is written) or first data to be read (i.e. as a data source when the data is read).

When data is written, the controller can select at least one disk from a plurality of disks of the first memory as a target disk according to an address description mode, an available storage space and the like. For example, in the case where the controller caches the second data, the target disk may be determined according to the address description manner supported inside the controller: assuming that the address description mode supported in the controller is PRP, selecting a disk with the type of PRP, SGL or SGE as a target disk; assuming that the address description mode supported inside the controller is SGL, a disk with a class of SGL or SGE may be selected as the target disk. In addition, when determining the target disk, other information such as available storage space of the disk can be considered. The selection mode of the target disk can be set by a person skilled in the art according to practical situations, and the application is not limited.

The virtual address corresponding to the first address information can be generated according to the first address information of the first data to be operated and the category of the target disk. The virtual address corresponding to the first address information may include an identifier of the first address information. For example, a virtual address corresponding to the first address information may be generated based on the identifier key0 of the first address information of the first data, the type of the target disk, and other information required by the data management protocol (for example, a base address, an address offset, etc. in the first address description information), and the virtual address and the first address information are associated by the identifier key 0.

In one possible implementation, the virtual address is located in a preset virtual address space. The virtual address corresponding to the first address information may include a base address (base_address) of a preset virtual address space, a class (disk_information) of the target disk, an identifier key of the first address information, and an address offset of the first address information. The virtual address may also include other relevant information, which may be set by those skilled in the art according to the actual situation, and this application is not limited thereto.

The virtual address occupies a certain address space (i.e., an address segment) in a preset virtual address interval, but the address space does not correspond to a real physical storage space in the controller, i.e., the second memory of the controller cannot be accessed by using the virtual address. The controller can operate the virtual address and convert the virtual address into corresponding first address information through operation so as to access data.

FIG. 6 illustrates a schematic diagram of a virtual address space according to an embodiment of the present application. As shown in fig. 6, the preset virtual address space includes 4 sub-areas, and the address space corresponding to 4 virtual addresses:

the sub-region 1 corresponds to the first address information identified as key1, namely, the address space occupied by the virtual address corresponding to the first address information identified as key1 in the virtual address space is sub-region 1;

The sub-region 2 corresponds to the first address information identified as key2, namely, the address space occupied by the virtual address corresponding to the first address information identified as key2 in the virtual address space is the sub-region 2;

the sub-region 3 corresponds to the first address information identified as key3, that is, the address space occupied by the virtual address corresponding to the first address information identified as key3 in the virtual address space is the sub-region 3;

the sub-region 4 corresponds to the first address information identified as key4, i.e. the address space occupied by the virtual address corresponding to the first address information identified as key4 in the virtual address space is sub-region 4.

It should be noted that, fig. 6 only illustrates a virtual address space including 4 sub-areas as an example, and those skilled in the art should understand that the number of sub-areas included in the virtual address space and the size of each sub-area may be set according to the actual situation, which is not limited in this application.

In one possible implementation, a virtual address space S may be preset, where a virtual address of a target disk with a type of PRP may occupy the address space of the virtual address space S, and a virtual address of a target disk with a type of SGL or SGE may also occupy the address space of the virtual address space S.

In one possible implementation, different virtual address spaces may also be preset according to the class of the target disk. For example, two virtual address spaces S1 and S2 may be preset, and a virtual address of a target disk with a type PRP may occupy an address space in the virtual address space S1, and a virtual address of a target disk with a type SGL or SGE may occupy an address space in the virtual address space S2.

FIG. 7 illustrates a schematic diagram of virtual addresses according to an embodiment of the present application. As shown in fig. 7, the virtual address 700 includes a base address (base_address) of the virtual address space, a class (disk_information) of the target disk, an identifier (key) of first address information corresponding to the virtual address 700, and an address offset (entry_offset) in the first address information corresponding to the virtual address 700.

The virtual address 700 has a length of 48 bits, a length of base_address of 12 bits, a length of disk_information of 2 bits, a length of key of 16 bits, and a length of entry_offset of 18 bits.

Step S340, generating an operation instruction according to the virtual address.

The controller may generate an operation instruction according to a virtual address corresponding to the first address information and a data management protocol between the controller and the target disk, the operation instruction including the virtual address. When the command sent to the controller by the host is a data writing command, that is, in the data writing process, the operation command generated by the controller is a data writing command sent to the target disk.

By the method, the address description mode in the operation instruction meets the data management protocol requirement, and the first address information of the first data in the operation instruction is replaced by the corresponding virtual address, so that address virtualization in the interaction process of the controller and the target disk is realized.

And step S350, the operation instruction is sent to the target disk, so that the target disk generates an address reading instruction aiming at the virtual address.

After the controller generates the operation instruction, the operation instruction may be sent to the target disk. When receiving an operation instruction sent by a controller, a target disk in the first memory can generate an address reading instruction aiming at a virtual address in the operation instruction according to the operation instruction and a data management protocol between the controller and the target disk, and send the address reading instruction to the controller.

Step S360, when the address reading instruction sent by the target disk is received, performing data interaction with the target disk according to the first address information corresponding to the virtual address.

In one possible implementation manner, the controller may determine a class of the target disk from the virtual address in the address reading instruction when receiving the address reading instruction sent by the target disk, determine first address information corresponding to the virtual address (i.e., a physical address corresponding to the virtual address) through the key, and determine whether an address description manner of the first address information corresponding to the virtual address matches the class of the target disk.

For example, if the address description mode of the first address information corresponding to the virtual address is PRP and the class of the target disk is PRP class, the address description mode of the first address information corresponding to the virtual address is considered to match the class of the target disk; if the address description mode of the first address information corresponding to the virtual address is PRP and the class of the target disk is SGL class or SGE class, the address description mode of the first address information corresponding to the virtual address is not matched with the class of the target disk.

And under the condition that the address description mode of the first address information corresponding to the virtual address is matched with the category of the target disk, the first address information can be used as target address information to perform data interaction with the target disk. For example, assuming that a data management protocol between the controller and the target disk is NVMe, when the controller performs data interaction with the target disk by using the first address information as target address information, the controller may send the first address information to the target disk; under the condition that the target disk receives the first address information sent by the controller, the first data can be read from the second memory of the controller according to the first address information, and the read first data is written into the local (namely the target disk).

Under the condition that the address description mode of the first address information corresponding to the virtual address is matched with the category of the target disk, the first address information is directly used as the target address information to conduct data interaction with the target disk, address conversion is not needed, and therefore processing efficiency can be improved.

If the address description mode of the first address information corresponding to the virtual address does not match the class of the target disk, the controller may convert the first address information according to the class of the target disk to obtain the target address information, for example, assuming that the class of the target disk is SGL class and the address description mode of the first address information corresponding to the virtual address is PRP, the controller may convert the first address information to convert the address description mode thereof from PRP to SGL, so that the address description mode of the converted address information matches the class of the target disk and regards the converted address information as the target address information; and then, carrying out data interaction with the target disk according to the target address information.

Under the condition that the address description mode of the first address information corresponding to the virtual address is not matched with the category of the target disk, the controller converts the first address information according to the category of the target disk to obtain target address information, and performs data interaction with the target disk according to the target address information, so that the controller and the target disk can perform data interaction under the condition that the target address information is matched with the category of the target disk.

According to the storage device, when receiving the data writing instruction sent by the host for the second data, the controller can buffer the second data through the second memory, and can also virtualize the address information of the data to be operated by the controller (namely, the physical address of the data to be operated in the second memory) to obtain the corresponding virtual address, and then generate and send the operation instruction to the target disk according to the virtual address.

Step S340 and step S350 in the embodiment shown in fig. 3 are the instruction interaction process between the controller of the storage device and the target disk. In the prior art, the addresses used in the instruction interaction process between the controller and the target disk are all physical addresses of the data to be operated, that is, in the prior art, the physical addresses of the data to be operated in the second memory are used in step S340 and step S350, and there is complicated address management. In the storage device of the embodiment of the present application, in step S340 and step S350 (i.e., in the instruction interaction between the controller and the target disk), the virtual address generated according to the first address information (physical address) of the data to be operated is used, so that the address information in the storage device is virtualized and normalized, thereby improving the processing efficiency of the storage device.

Fig. 8 shows a schematic diagram of a data reading process of a memory device according to an embodiment of the present application. The data that the host needs to read from the first memory of the storage device can be considered as third data. When the third data is read, the host may send a data read instruction for the third data to the storage device for instructing the controller of the storage device to read the third data from the first memory.

As shown in fig. 8, in the case of receiving a data read instruction for third data transmitted by the host, the controller of the storage device may perform the following processing:

step S810, when a data reading instruction for third data sent by the host is received, allocating a buffer space for the third data in the second memory according to the length of the third data.

The data read command sent by the host to the controller may include information such as a storage address, a length, etc. of the third data stored in the first memory, which the host instructs the controller to read. The controller may determine a length of the third data from the data read instruction when receiving the data read instruction for the third data sent by the host, and allocate a buffer space for the third data in the second memory according to the length of the third data.

The buffer space is used for buffering the third data in the controller, that is, after the controller reads the third data from the first memory, the controller can store the third data in the buffer space and then send the third data in the buffer space to the host, so that the host can read the third data.

Step S820, determining the first address information of the first data to be operated according to the fourth address information of the buffer space.

Wherein the first data is part of or all of the third data. The scenario where the first data is all data in the third data may be: the controller reads the third data as a whole, i.e. the controller reads the third data from the first memory by one read operation. The scenario where the first data is part of the data in the third data may be: the controller splits the third data into a plurality of data blocks, and reads each data block respectively, namely the controller reads the third data from the first memory and completes the reading operation for a plurality of times.

In the data reading process, the controller may determine the first data to be operated according to a preset data operation rule (for example, a data blocking rule) of the storage device, and the like. The controller may preset a data block flag bit to indicate whether the third data is blocked, and further determine that the first data is part of or all of the third data according to the data block flag bit.

The controller can also determine that the first data is part of or all of the third data in real time through judging the length, the initial position offset and the like of the data in the data reading process. It should be noted that the determination process is similar to the determination process in step S320 in the embodiment shown in fig. 3, and will not be described here again.

After determining the first data to be operated, the controller may determine the first address information of the first data to be operated according to the fourth address information of the cache space. Wherein the first address information may be used to indicate a physical address of the first data to be operated on in the second memory. In the data reading process, the first address information may be regarded as address information of a buffer space allocated in the second memory in advance for the first data to be read.

In the case where the first data to be operated is all of the third data, the fourth address information (physical address) of the cache space may be directly determined as the first address information of the first data.

When the first data to be operated is part of the third data, the buffer space needs to be divided, and a buffer area corresponding to the first data is determined. The buffer area corresponding to the first data can be determined from the buffer space according to the fourth address information of the buffer space, the length of the first data, the initial position offset and the like, and the address information of the buffer area is determined as the first address information of the first data.

In one possible implementation, the first address information may be represented as a physical address of the cache space/cache region, similar to the fourth address information. In the case that the first data to be operated is part of the third data, the first address information may be represented as a conversion relationship between the cache area corresponding to the first data and the fourth address information by means of a conversion table, a data information table (data information table, DIT), or the like. The controller may obtain the physical address of the buffer area corresponding to the first data by real-time parsing of the conversion table or the data information table.

In one possible implementation manner, the address description manner of the fourth address information is an address description manner supported inside the controller, and the address description manner of the first address information is the same as the address description manner of the fourth address information. For example, assuming that the address description manner supported inside the controller is PRP, the address description manner of the fourth address information and the address description manner of the first address information are PRP.

When receiving a data reading instruction for third data sent by a host, a controller of the storage device can allocate a buffer space for the third data in a second memory according to the length of the third data, and determine first address information of first data to be operated (part of data or all data in the third data) according to fourth address information of the buffer space, so that when the data is read, the read third data can be buffered through the second memory of the controller, address information can be managed in a unified address description mode in the controller, and complexity of address management in the controller is reduced.

In the data reading process, the fourth address information and the first address information are also stored in an address storage space preset by the controller and used for storing the address information, and are associated through an identifier key. The specific manner is similar to the embodiment shown in fig. 3, and will not be described again here.

Step S830, according to the first address information of the first data to be operated and the class of the target disk, generating a virtual address corresponding to the first address information.

Wherein the target disk is at least one of a plurality of disks of the first memory. When data is read, the target disk is a disk storing first data to be read in the first memory. The virtual address corresponding to the first address information includes an identifier of the first address information.

The virtual address corresponding to the first address information can be generated according to the first address information of the first data to be operated and the category of the target disk. The specific manner is similar to the embodiment shown in fig. 3, and will not be described again here.

Step S840, generating an operation instruction according to the virtual address.

The controller may generate an operation instruction according to a virtual address corresponding to the first address information and a data management protocol between the controller and the target disk, the operation instruction including the virtual address. In the case that the command sent to the controller by the host is a data reading command, that is, in the data reading process, the operation command generated by the controller is a data reading command sent to the target disk.

Step S850, sending the operation instruction to the target disk, so that the target disk generates an address reading instruction for the virtual address.

Step S860, when the address reading instruction sent by the target disk is received, performing data interaction with the target disk according to the first address information corresponding to the virtual address.

And under the condition that the address description mode of the first address information corresponding to the virtual address is matched with the category of the target disk, the first address information can be used as target address information to perform data interaction with the target disk. For example, assuming that a data management protocol between the controller and the target disk is NVMe, when the controller performs data interaction with the target disk by using the first address information as target address information, the controller may send the first address information to the target disk; the target disk may read the first data locally when receiving the first address information sent by the controller, and write the read first data into a cache space (located in the second memory of the controller) indicated by the first address information.

In the storage device of the embodiment of the present application, when receiving a data reading instruction for third data sent by a host, the controller may apply for a cache space in the second memory for the third data to be read in advance, and determine, according to fourth address information of the cache space, first address information of first data to be operated (which is part of or all of data in the third data); the virtual address corresponding to the first address information can be generated according to the first address information of the first data to be operated and the category of the target disk, then an operation instruction is generated and sent to the target disk according to the virtual address, the target disk generates and sends an address reading instruction aiming at the virtual address under the condition that the operation instruction sent by the controller is received, and the controller performs data interaction with the target disk according to the first address information corresponding to the virtual address under the condition that the address reading instruction sent by the target disk is received, so that the address information of the data to be operated (namely, the physical address of the data to be operated in the second memory) can be virtualized to obtain the corresponding virtual address, and the virtual address is used in the process of the instruction (or command) interaction between the controller and the target disk, so that the address information in the storage device is virtualized and normalized, the address management in the storage device is simplified, and the processing efficiency of the storage device is improved.

Step S840 and step S850 in the embodiment shown in fig. 8 are the instruction interaction process between the controller of the storage device and the target disk. In the prior art, the addresses used in the instruction interaction process between the controller and the target disk are all physical addresses of the data to be operated, that is, in the prior art, the physical addresses of the data to be operated in the second memory are used in step 840 and step S850, and there is complicated address management. In the storage device of the embodiment of the present application, in step S840 and step S850 (i.e., in the instruction interaction between the controller and the target disk), the virtual address generated according to the first address information (physical address) of the data to be operated is used, so that the address information in the storage device is virtualized and normalized, thereby improving the processing efficiency of the storage device.

According to the storage device, the data of the operation can be cached through the second memory in the controller, and the virtual address is used in the instruction interaction process of the controller and the target disk, so that the address information in the storage device is virtualized and normalized. In the process of the instruction interaction between the controller and the target disk of the first memory, under the condition that the types of the target disk are different, virtual addresses in operation instructions sent to the target disk by the controller also show different rules.

Fig. 9 shows a flow chart of a storage method according to an embodiment of the present application. The storage method is applied to a controller in a storage device, the storage device further comprises a first memory, the first memory comprises a plurality of magnetic disks, and the controller comprises a second memory for caching data.

As shown in fig. 9, the storage method includes:

step S910, generating a virtual address corresponding to first address information according to the first address information of the first data to be operated and a class of a target disk, where the first address information is used to indicate a physical address of the first data in the second memory, the target disk is at least one of the plurality of disks, and the virtual address includes an identifier of the first address information;

step S920, generating an operation instruction according to the virtual address;

step S930, sending the operation instruction to the target disk, so that the target disk generates an address reading instruction for the virtual address;

step S940, when the address reading instruction sent by the target disk is received, performing data interaction with the target disk according to the first address information corresponding to the virtual address.

In one possible implementation, the controller is connected to a host, and the method may further include: under the condition that a data writing instruction for second data sent by the host is received, according to second address information of the second data in the data writing instruction, caching the second data into the second memory, wherein the data writing instruction is used for instructing the controller to write the second data into the first memory; and determining first address information of first data to be operated according to third address information of the second data in the second memory, wherein the first data are part of or all of the second data. .

In one possible implementation, the method may further include: under the condition that a data reading instruction for third data sent by the host is received, according to the length of the third data, a buffer space is allocated for the third data in the second memory, the data reading instruction is used for instructing the controller to read the third data from the first memory, and the buffer space is used for buffering the third data in the controller; and determining first address information of first data to be operated according to fourth address information of the cache space, wherein the first data is part of or all of the third data.

In one possible implementation manner, the address description manner of the second address information is any one of a physical area page PRP, a scatter aggregation table SGL, and a scatter aggregation element SGE, the address description manner of the first address information, the third address information, and the fourth address information is PRP, and the class of the target disk is any one of a PRP class, an SGL class, and an SGE class.

In one possible implementation manner, the determining the first address information of the first data according to the third address information of the second data in the second memory may include: and when the first data is part of the second data, determining the first address information of the first data according to third address information, the length of the first data and a starting position offset, wherein the starting position offset is used for indicating the offset of the starting position of the first data relative to the starting position of the second data.

In one possible implementation manner, the determining the first address information of the first data according to the third address information of the second data in the second memory may include: and when the first data is all data in the second data, determining third address information of the second data as first address information of the first data.

In one possible implementation, the method may further include: and determining that the first data is all data in the second data under the condition that the length of the first data is the same as that of the second data and the initial position offset of the first data is equal to 0.

In one possible implementation, the method may further include: and determining that the first data is part of the second data when the length of the first data is different from the length of the second data or the initial position deviation of the first data is not equal to 0.

In one possible implementation manner, the step S940 may include: under the condition that the address description mode of the first address information is not matched with the category of the target disk, converting the first address information according to the category of the target disk to obtain target address information; and carrying out data interaction with the target disk according to the target address information.

In one possible implementation manner, the step S940 may include: and under the condition that the address description mode of the first address information is matched with the category of the target disk, carrying out data interaction with the target disk by taking the first address information as target address information.

The embodiment of the application also provides electronic equipment, which comprises: the device comprises a processor and a storage device connected with the processor, wherein the storage device is any one of the storage devices.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and electronic devices according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by hardware (e.g., circuits or ASICs (Application Specific Integrated Circuit, application specific integrated circuits)) which perform the corresponding functions or acts, or combinations of hardware and software, such as firmware, etc.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The embodiments of the present application have been described above, the foregoing description is exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

A storage device is characterized by comprising a controller and a first memory, wherein the first memory comprises a plurality of magnetic disks, the controller comprises a second memory for caching data,

the controller is configured to:

generating a virtual address corresponding to first address information according to the first address information of first data to be operated and the category of a target disk, wherein the first address information is used for indicating the physical address of the first data in the second memory, the target disk is at least one of the plurality of disks, and the virtual address comprises an identifier of the first address information;

generating an operation instruction according to the virtual address;

sending the operation instruction to the target disk so as to enable the target disk to generate an address reading instruction aiming at the virtual address;

and under the condition that the address reading instruction sent by the target disk is received, carrying out data interaction with the target disk according to the first address information corresponding to the virtual address.
The storage device of claim 1, wherein the controller is coupled to a host,

The controller is further configured to:

under the condition that a data writing instruction for second data sent by the host is received, according to second address information of the second data in the data writing instruction, caching the second data into the second memory, wherein the data writing instruction is used for instructing the controller to write the second data into the first memory;

and determining first address information of first data to be operated according to third address information of the second data in the second memory, wherein the first data are part of or all of the second data.
The storage device of claim 2, wherein the controller is further configured to:

under the condition that a data reading instruction for third data sent by the host is received, according to the length of the third data, a buffer space is allocated for the third data in the second memory, the data reading instruction is used for instructing the controller to read the third data from the first memory, and the buffer space is used for buffering the third data in the controller;

and determining first address information of first data to be operated according to fourth address information of the cache space, wherein the first data is part of or all of the third data.
The storage device according to claim 3, wherein the address description manner of the second address information is any one of a physical area page PRP, a scatter gather table SGL, and a scatter gather element SGE, the address description manner of the first address information, the third address information, and the fourth address information is PRP, and the class of the target disk is any one of a PRP class, an SGL class, and an SGE class.
The storage device of claim 2, wherein the determining the first address information of the first data based on the third address information of the second data in the second memory comprises:

and when the first data is part of the second data, determining the first address information of the first data according to third address information, the length of the first data and a starting position offset, wherein the starting position offset is used for indicating the offset of the starting position of the first data relative to the starting position of the second data.
The storage device of claim 2, wherein the determining the first address information of the first data based on the third address information of the second data in the second memory comprises:

And when the first data is all data in the second data, determining third address information of the second data as first address information of the first data.
The storage device of any of claims 2-6, wherein the controller is further configured to:

and determining that the first data is all data in the second data under the condition that the length of the first data is the same as that of the second data and the initial position offset of the first data is equal to 0.
The storage device of any of claims 2-7, wherein the controller is further configured to:

and determining that the first data is part of the second data when the length of the first data is different from the length of the second data or the initial position deviation of the first data is not equal to 0.
The storage device according to any one of claims 1 to 8, wherein the performing data interaction with the target disk according to the first address information corresponding to the virtual address includes:

under the condition that the address description mode of the first address information is not matched with the category of the target disk, converting the first address information according to the category of the target disk to obtain target address information;

And carrying out data interaction with the target disk according to the target address information.
The storage device according to any one of claims 1 to 8, wherein the performing data interaction with the target disk according to the first address information corresponding to the virtual address includes:

and under the condition that the address description mode of the first address information is matched with the category of the target disk, carrying out data interaction with the target disk by taking the first address information as target address information.
A storage method, characterized in that the method is applied to a controller in a storage device, the storage device further comprising a first memory, the first memory comprising a plurality of disks, the controller comprising a second memory for caching data,

the method comprises the following steps:

generating a virtual address corresponding to first address information according to the first address information of first data to be operated and the category of a target disk, wherein the first address information is used for indicating the physical address of the first data in the second memory, the target disk is at least one of the plurality of disks, and the virtual address comprises an identifier of the first address information;

Generating an operation instruction according to the virtual address;

sending the operation instruction to the target disk so as to enable the target disk to generate an address reading instruction aiming at the virtual address;

and under the condition that the address reading instruction sent by the target disk is received, carrying out data interaction with the target disk according to the first address information corresponding to the virtual address.
The storage method of claim 11, wherein the controller is coupled to a host,

the method further comprises the steps of:

under the condition that a data writing instruction for second data sent by the host is received, according to second address information of the second data in the data writing instruction, caching the second data into the second memory, wherein the data writing instruction is used for instructing the controller to write the second data into the first memory;

and determining first address information of first data to be operated according to third address information of the second data in the second memory, wherein the first data are part of or all of the second data.
The storage method of claim 12, wherein the method further comprises:

Under the condition that a data reading instruction for third data sent by the host is received, according to the length of the third data, a buffer space is allocated for the third data in the second memory, the data reading instruction is used for instructing the controller to read the third data from the first memory, and the buffer space is used for buffering the third data in the controller;

and determining first address information of first data to be operated according to fourth address information of the cache space, wherein the first data is part of or all of the third data.
The storage method according to claim 13, wherein the address description manner of the second address information is any one of a physical area page PRP, a scatter gather table SGL, and a scatter gather element SGE, the address description manner of the first address information, the third address information, and the fourth address information is PRP, and the class of the target disk is any one of a PRP class, an SGL class, and an SGE class.
The storage method according to claim 12, wherein the determining the first address information of the first data based on the third address information of the second data in the second memory includes:

And when the first data is part of the second data, determining the first address information of the first data according to third address information, the length of the first data and a starting position offset, wherein the starting position offset is used for indicating the offset of the starting position of the first data relative to the starting position of the second data.
The storage method according to claim 12, wherein the determining the first address information of the first data based on the third address information of the second data in the second memory includes:

and when the first data is all data in the second data, determining third address information of the second data as first address information of the first data.
The storage method according to any one of claims 12-16, wherein the method further comprises:

and determining that the first data is all data in the second data under the condition that the length of the first data is the same as that of the second data and the initial position offset of the first data is equal to 0.
The storage method according to any one of claims 12-17, wherein the method further comprises:

And determining that the first data is part of the second data when the length of the first data is different from the length of the second data or the initial position deviation of the first data is not equal to 0.
The storage method according to any one of claims 11 to 18, wherein the performing data interaction with the target disk according to the first address information corresponding to the virtual address includes:

under the condition that the address description mode of the first address information is not matched with the category of the target disk, converting the first address information according to the category of the target disk to obtain target address information;

and carrying out data interaction with the target disk according to the target address information.
The storage method according to any one of claims 11 to 18, wherein the performing data interaction with the target disk according to the first address information corresponding to the virtual address includes:

and under the condition that the address description mode of the first address information is matched with the category of the target disk, carrying out data interaction with the target disk by taking the first address information as target address information.
An electronic device, comprising:

a processor;

a storage device coupled to the processor, the storage device being as claimed in any one of claims 1 to 10.