CN117337036A - Method for preparing memory array with contact enhancement top cover - Google Patents

Abstract

The present disclosure provides a method of fabricating a dynamic random access memory array with a contact enhanced cap. The method comprises the following steps: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated active regions formed by a surface region of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active regions; recessing a first set of active regions of the plurality of active regions from a top surface while covering a top surface of a second set of active regions of the plurality of active regions; and integrally forming a plurality of contact enhancement sidewall spacers and a plurality of contact enhancement caps, wherein the contact enhancement sidewall spacers transversely surround the tops of the active regions, and the contact enhancement caps cover the upper surfaces of the active regions.

Description

Method for fabricating memory array with contact enhanced top cover

This application is a division of Chinese invention patent application No. 202210723522.9, titled "Memory array with contact enhanced top cover and preparation method thereof" submitted on June 23, 2022. Application No. 202210723522.9 claims that 2021 Priority and benefits of U.S. Formal Application No. 17/528,505 and U.S. Formal Application No. 17/528,617 filed on November 17. The contents of these U.S. Formal Applications are incorporated herein by reference in their entirety.

Technical field

The present disclosure provides a memory array and a manufacturing method thereof, and particularly relates to a dynamic random access memory (DRAM) array with a contact-enhanced top cover and a manufacturing method thereof.

Background technique

As electronic products have continued to improve in recent decades, the need for storage capabilities has also increased. In order to increase the storage capacity of a memory element (eg, a DRAM element), more memory cells are arranged in the memory element, and the size of each memory cell in the memory element becomes smaller. The memory cells are respectively fabricated on an active area, which may be part of the semiconductor substrate. Active area scaling is an option to reduce the size of each memory cell.

Each DRAM cell may include a storage capacitor disposed on the active area and connected to the active area through a capacitive contact. A reduction in the active area may result in a reduction in the landing area for capacitor contact. Therefore, the contact resistance between the capacitor contacts and the active region may increase due to semiconductor lithography process overlay issues. In other words, pursuing high storage density by minimizing the active area may harm the performance of DRAM elements. There is a need in the art for a method of increasing the landing area for capacitor contacts without expanding the layout pattern of the active area.

The above "prior art" description only provides background art and does not admit that the above "prior art" description discloses the subject matter of the present disclosure. It does not establish prior art of the present disclosure, and the above "prior art" description Any description of shall not form any part of this disclosure.

Contents of the invention

In an embodiment of the present disclosure, a method for manufacturing a memory array is provided, including: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated cells formed by a surface area of the semiconductor substrate. Active region; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active regions; moving a first group of active regions of the active regions from a top surface recess, while covering a top surface of a second group of active areas of the plurality of active areas; and integrating to form a plurality of contact-enhancing sidewall spacers and a plurality of contact-enhancing top covers, the contact-enhancing sidewall gaps The sub-surface laterally surrounds the tops of the active areas, and the contact enhancement top covers cover the upper surfaces of the active areas.

The technical features and advantages of the disclosure have been summarized rather broadly above so that a better understanding can be obtained from the detailed description of the disclosure that follows. Other technical features and advantages that are the subject of the claims of the present disclosure will be described below. It should be understood by those skilled in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those skilled in the technical field to which this disclosure belongs should also understand that such equivalent constructions cannot depart from the concept and scope of the disclosure as defined by the claims.

Description of drawings

The disclosure content of the present disclosure can be more fully understood by referring to the embodiments and claims in conjunction with the accompanying drawings. The same reference numerals in the drawings refer to the same components.

FIG. 1A is a circuit diagram illustrating a memory cell in a memory array according to some embodiments of the present disclosure.

FIG. 1B is a structural diagram illustrating a memory array including a plurality of memory cells according to some embodiments of the present disclosure.

Figure 2A is a plan view illustrating a partial layout of a memory array according to some embodiments of the present disclosure.

2B is a cross-sectional view illustrating an edge portion of two adjacent active areas and a portion of an isolation structure extending between the adjacent active areas, according to some embodiments of the present disclosure.

Figure 3 is a flow chart illustrating a method of preparing the structure shown in Figure 2B according to some embodiments of the present disclosure.

4A to 4K are plan views illustrating structures at an intermediate stage of the preparation method shown in FIG. 3 according to some embodiments of the present disclosure.

5A to 5K are cross-sectional views illustrating structures at an intermediate stage of the preparation method shown in FIG. 3 according to some embodiments of the present disclosure.

6 is a cross-sectional view illustrating an edge portion of two adjacent active regions and a portion of an isolation structure extending between these adjacent active regions, according to some other embodiments of the present disclosure.

Explanation of reference symbols:

10: Memory array

100: storage cell

200: Semiconductor substrate

202: Isolation Structure

204: Contact Enhanced Top Cover

204-1: Contact Enhanced Top Cover

204-2: Contact Enhanced Top Cover

206: Self-assembled monolayer (SAM)

206-1: Self-assembled single layer

206-2: Self-assembled single layer

300: First insulation layer

302: Second insulation layer

304: Mask layer

304a: striped pattern

304b: Island pattern

306: Mask layer

604: Contact Enhanced Cover

604-1: Contact Enhanced Capping

604-2: Contact Enhanced Capping

604a: Contact enhancement layer

604b: Contact enhanced top cover

AA: active area

AA': initial active area

A-A': line

AA1: Active area

AA2: Active area

AT: access transistor

B-B': line

BL: bit line

CC: capacitor contact

CC1: Capacitor contact

CC2: Capacitor contact

D1: direction

D2: direction

H1: height

H2: height

H202: height

H204-1: Height

H204-2: Height

H604-1: height

H604-2: Height

S11: Steps

S13: Steps

S15: Steps

S17: Steps

S19: Steps

S21: Steps

S23: Steps

S25: Steps

S27: Steps

S29: Steps

S31: Steps

S33: Steps

SC: storage capacitor

SW1: side wall

SW2: side wall

TR: trench

TR': initial trench

TS1: Top surface

TS2: Top surface

TS202: Top surface

WL: word line

Detailed ways

The following disclosure provides many different embodiments or examples of implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the dimensions of components are not limited to the disclosed ranges or values, but may depend on process conditions and/or desired properties of the components. In addition, in the following description, forming the first feature "over" or "on" the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which the first feature and the second feature are formed in direct contact. Embodiments may be made in which additional features may be formed between features and second features such that the first feature and the second feature may not be in direct contact. For the sake of simplicity and clarity, some features may be drawn arbitrarily at different scales. In the figures, some layers/features may be omitted for simplicity.

In addition, for ease of explanation, "beneath", "below", "lower", "above", "upper", etc. may be used herein. Spatially relative terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The elements may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted equally accordingly.

FIG. 1A is a circuit diagram illustrating a memory cell 100 in a memory array according to some embodiments of the present disclosure. Referring to FIG. 1A, the memory array may be a dynamic random access memory (DRAM) array structure. Each memory cell 100 in the memory array may include an access transistor AT and a storage capacitor SC. The access transistor AT may be a field effect transistor (FET). One end of storage capacitor SC is coupled to the source/or drain terminal of access transistor AT, while the other end of storage capacitor SC may be coupled to a reference voltage (eg, ground voltage as described in FIG. 1A ). When access transistor AT turns on, storage capacitor SC can be accessed. On the other hand, when the access transistor AT is in an offstate, the storage capacitor SC cannot be accessed.

During a write operation, access transistor AT is turned on by establishing word line WL coupled to a gate terminal of access transistor AT, and applying force to bit line BL (coupled to a gate terminal of access transistor AT) The voltage on the storage capacitor SC (coupled with the other source/or drain terminal of the access transistor AT) may be transferred to the storage capacitor SC (coupled with the other source/or drain terminal of the access transistor AT). Therefore, the storage capacitor SC can be charged or discharged, and the logic state "1" or the logic state "0" can be stored in the storage capacitor SC. During a read operation, the access transistor AT is also turned on, and the pre-charged bit line BL can be pulled high or low depending on the charge state of the storage capacitor SC. By comparing the voltage of the bit line BL and the precharge voltage, the charge state of the storage capacitor SC can be sensed, and the logic state of the memory cell 100 can be identified.

FIG. 1B is a structural diagram illustrating a memory array 10 including a plurality of memory cells 100 according to some embodiments of the present disclosure. Referring to FIG. 1B , memory array 10 has rows and columns. The memory cells 100 in each column may be arranged along a first direction, and the memory cells 100 in each row may be arranged along a second direction intersecting the first direction. A plurality of bit lines BL may be respectively coupled to a column of memory cells 100 . On the other hand, multiple word lines WL may be coupled to one row of memory cells 100 respectively. In some embodiments, during a write operation, word line WL coupled to selected memory cell 100 is asserted, and the selected bit line WL is asserted by providing a voltage to a bit line coupled to selected memory cell 100 . The storage capacitor SC in the memory cell 100 is programmed. In addition, during the read operation, all bit lines BL are precharged, and the word line WL coupled to the selected memory cell 100 is established, and then each through the storage capacitor coupled to the established word line WL. SC to pull high or low the precharged bit line BL. By detecting the voltage change of the bit line BL coupled to the selected memory cell 100, the logic state of the selected memory cell 100 can be identified. By pulling the precharge bit line BL high and/or low, the stored charge in the storage capacitor SC of the memory cell 100 coupled to the established word line WL is changed. In order to restore the logic state of these memory cells 100, a write operation may be performed after the read operation to program the previous logic state into these memory cells 100. This write operation may also be called a refresh operation.

Figure 2A is a plan view illustrating a partial layout of memory array 10 for some embodiments of the present disclosure.

Referring to FIGS. 1B and 2A , memory array 10 may be built on semiconductor substrate 200 . The semiconductor substrate 200 may be, for example, a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. The semiconductor substrate 200 has surface portions laterally separated from each other, called active areas AA. The isolation structure 202 extending in the semiconductor substrate 200 may laterally surround each active area AA to physically and electrically isolate the active areas AA from each other. In other words, active area AA is defined by isolation structure 202 .

According to some embodiments, the active areas AA may be arranged in an array with multiple rows and columns. Word lines WL may be formed in the semiconductor substrate 200, and each word line laterally penetrates one row of the active area AA. On the other hand, the bit lines BL may be formed on the semiconductor substrate 200 and each intersect one column of the active areas AA.

The access transistor AT in each memory cell 100 of the memory array 10 is defined near the intersection of the active area AA and the penetrating word line WL and the intersecting bit line BL. The word line WL serves as the gate terminal of the access transistor AT, and the portions of the active area AA located on opposite sides of the word line WL may serve as the source/drain terminal of the access transistor AT. Bit line BL is coupled to one of the source/drain terminals. Additionally, the other source/drain terminal may be coupled with one of the storage capacitors SC formed over the semiconductor substrate 200 . It should be understood that depicting storage capacitor SC as a separate pattern represents the separate bottom electrode of storage capacitor SC. Although not shown, the storage capacitors SC may actually have a common top electrode.

In some embodiments, the word line WL extends along a first direction. In addition, the bit line BL may extend along a second direction that is substantially perpendicular to the first direction. Optionally, each bit line BL may form a curve along its extending direction (eg, the second direction). Furthermore, the active areas AA may each extend along a third direction intersecting the first direction and the second direction.

In some embodiments, each active area AA is shared by two access transistors AT having a common source/or drain terminal. In these embodiments, each active area AA is penetrated by two word lines WL and intersects one of the bit lines BL. Furthermore, each active area AA may overlap with two storage capacitors SC. The bit line BL overlaps and is electrically connected to a part of the active area AA spanning between the two word lines WL. This part of the active area AA can be used as the common source of the two access transistors AT/ or drain terminal. Other parts of the active area AA located on opposite sides of the two word lines WL can serve as separate source/drain terminals of the two access transistors AT, and can overlap and capacitate the two covering storage capacitors SC respectively. sexual connection.

2B is a cross-sectional view illustrating an edge portion of two adjacent active areas AA and a portion of the isolation structure 202 extending between the adjacent active areas AA according to some embodiments of the present disclosure.

Referring to FIG. 2B , an isolation structure 202 is formed in a trench TR of the semiconductor substrate 200 that extends from a top surface of the semiconductor substrate 200 into the semiconductor substrate 200 and laterally separates the active area AA. Furthermore, some active areas AA may be recessed relative to other active areas AA, and the top surface of the semiconductor substrate 200 in some areas of those recessed active areas AA may be lower than in other areas of non-recessed active areas AA. . As illustrated in Figure 2B, one of the active areas AA (also referred to as active area AA1) is concave relative to the adjacent active area AA (also referred to as active area AA2). Therefore, the height H1 of the active area AA1 (measured from the depth flush with the bottom end of the isolation structure 202 to the top surface TS1 of the active area AA1 ) is smaller than the height H2 of the active area AA2 (measured from the depth flush with the bottom end of the isolation structure 202 The depth is measured to the top surface TS2) of the active area AA2.

Since the active areas AA1, AA2 have different heights, the trench TR extending between the active areas AA1, AA2 may have an asymmetric shape. As illustrated in FIG. 2B , where the active area AA1 is concave relative to the active area AA2 , the sidewall SW1 of the trench TR defining the boundary of the active area AA1 may be lower than the sidewalls SW1 of the trench TR defining the boundary of the active area AA2 SW2. The heights of side walls SW1 and SW2 are substantially equal to the heights of H1 and H2 respectively. To avoid redundancy, the ratios and ranges of heights H1 and H2 are not repeated.

According to some embodiments, the top surface TS ₂₀₂ of the isolation structure 202 filled in the trench TR is lower than the top surface TS1 of the active area AA1 and lower than the top surface TS2 of the active area AA2. In these embodiments, the height H ₂₀₂ of the isolation structure 202 (measured from the bottom end of the isolation structure 202 to the top surface TS ₂₀₂ of the isolation structure 202 ) is less than the height H1 of the active area AA1 and less than the height H2 of the active area AA2 . Since the isolation structure 202 will not fill the trench TR, the tops of the sidewalls SW1 and SW2 of the trench TR will not be covered by the isolation structure 202 . Since sidewall SW2 is taller than sidewall SW1 , the top of sidewall SW2 spanning over isolation structure 202 may be larger (higher) than the top of sidewall SW1 spanning over isolation structure 202 .

In some embodiments, the top of each active area AA is laterally surrounded by contact enhancement cap 204 and the remainder of each active area AA is laterally surrounded by isolation structure 202 . Contact enhancement cap 204 is semi-conductive or conductive and may serve as an additional portion of active area AA. By having such an extra portion, the active area AA can provide a larger landing area for the capacitor contact CC connecting the active area AA and the upper storage capacitor SC, as shown in Figure 2A. Therefore, the tolerance of the setting tolerance of the capacitor contact CC can be increased, and good electrical contact between the capacitor contact CC and the active area AA can be ensured. For example, the contact enhancement cap 204 includes silicon fabricated using an epitaxy process.

Since the active area AA1 protrudes less than the active area AA2 relative to the isolation structure 202 , the height H 204 - 1 of the contact enhancement cap 204 - 1 laterally surrounding the top of the active area AA1 may be shorter than the height H _{204 - 1} laterally surrounding the top of the active area AA2 Enhance the height H _204-2 of the top cover 204-2. Height _{H 204 - 1} is measured from the bottom end of contact enhancement top cover 204 - 1 , which may be flush with top surface TS ₂₀₂ of isolation structure 202 , to the top end of contact enhancement top cover 204 - 1 . Likewise, height H _204-2 is measured from the bottom end of contact enhancement top cover 204-2, which may be flush with top surface TS ₂₀₂ of isolation structure 202, to the top end of contact enhancement top cover 204-2. Because the contact enhancement caps 204-1, 204-2 extend to different heights from the top surface TS ₂₀₂ of the isolation structure 202, the top corners of the contact enhancement caps 204-1, 204-2 may have considerable lateral thickness (not shown). shown), can be further spaced vertically. Therefore, the contact enhancement caps 204-1, 204-2 can be prevented from merging, especially when the width of the trench TR between the active areas AA1, AA2 is further reduced. Therefore, interference between memory cells 100 formed on adjacent active areas AA can be avoided.

In some embodiments, the top surface of each active area AA is covered by a self-assembly monolayer (SAM) 206 . The self-assembled monolayer 206 may be selectively formed on the top surface of each active area AA and may not extend to the sidewalls of each active area AA. That is, the top of the sidewalls spanning each active area AA above the isolation structure 202 will not be covered by the SAM 206 . Therefore, the contact enhancement cap 204 formed after the SAM 206 may be disposed on top of the sidewalls of the active area AA. According to some embodiments, the contact enhancement cap 204 may also extend to the sidewalls of the SAM 206. In these embodiments, the top end of the contact enhancement cap 204 may be substantially flush with the top surface of the SAM 206 .

Since the active area AA1 is concave relative to the active area AA2, the top surface TS1 of the active area AA1 is lower than the top surface TS2 of the active area AA2. Therefore, the SAM 206 (also called SAM 206-1) covering the top surface TS1 of the active area AA1 is lower than the SAM 206 (also called SAM 206-2) covering the top surface TS2 of the active area AA2.

Self-assembled monolayers (SAMs) are a well-known technology in the art. See, for example, "Reactive Monolayers in Directed Additive Manufacturing-Area Selective Atomic Layer Deposition" Rudy J. Wojtecki et al., Journal of Photopolymer Science and Technology, 2018 Volume 31 Issue 3 Pages 431-436, which is hereby incorporated by reference. In some embodiments, SAMs 206 include organic molecules. According to some embodiments, SAMs 206 include a plurality of molecules having a chemical formula selected from X-R1-SH, X-R1-SS-R2-Y, R1-S-R2, and combinations thereof, wherein R1 and R2 are independent carbon chains or a carbon chain interrupted by at least one heteroatom, where H is hydrogen, where S is sulfur, and where X and Y are chemical groups that are substantially non-chemically reactive with the copper surface. In some embodiments, at least one of R1 and R2 is a chain of n carbon atoms, where n is an integer from 1 to 30. In some embodiments, the chemical formula of SAMs 206 is SH(CH ₂ ) ₉ CH ₃ .

In some embodiments, the SAM is fabricated by self-assembled monolayers of polymerizable compounds. The thickness of the monolayer corresponds to the length of one molecule of the compound in the close-packed structure of the monolayer. The close-packed structure is assisted by functional groups of the compound that bind to surface groups of the substrate through electrostatic interactions and/or one or more covalent bonds. The portion of the compound that binds to the surface of the substrate is referred to herein as the "head" of the compound. The rest of the compound is called the "tail". The tail extends from the head of the compound to the atmosphere interface on the top surface of the SAM. The tail has a non-polar peripheral end group on the atmosphere interface. Therefore, a good SAM has few defects in its close-packed structure and can display high contact angles.

The head portion of the SAM-forming compound can be selectively bound to a portion of the top surface of a substrate that includes regions of different compositions such that other portions of the top surface of the substrate have no or substantially no SAM-forming compounds disposed thereon. In this case, the patterned initial SAM can be formed in one step by immersing the substrate in a solution of a given SAM-forming compound (dissolved by an appropriate solvent). In some embodiments, the wavelength of ultraviolet radiation may be from approximately 4 nanometers (nm) to 450 nanometers. Deep ultraviolet (DUV) radiation can have wavelengths from 124 nanometers to 300 nanometers. Extreme ultraviolet (EUV) radiation can have wavelengths from about 4 nanometers to less than 124 nanometers.

In those embodiments where each active area AA is covered by a SAM 206, a capacitor contact CC disposed on the active area AA may penetrate the SAM 206 to establish electrical contact with the active area AA. Likewise, other contacts, such as bit line contacts (not shown), may also pass through SAM 206 to reach active area AA. Furthermore, in some embodiments, the capacitor contact CC extending to the lower active area AA may be higher than the capacitor contact CC extending to the upper active area AA. As illustrated in FIG. 2B , capacitive contact CC extending to active area AA1 (also referred to as capacitive contact CC1 ) may be higher than capacitive contact CC extending to active area AA2 (also referred to as capacitive contact CC2 ).

As mentioned above, the active area AA of the memory cell 100 in the memory array 10 has additional portions (ie, contact enhancement caps 204) at its top corners. By having these extra portions, active area AA can provide a larger landing area for capacitor contacts CC standing on active area AA. Therefore, the electrical contact between the capacitor contact CC and the active area AA may be less affected by process variations in providing the capacitor contact CC (eg, photolithographic coverage issues). In other words, the electrical contact between the capacitor contact CC and the active area AA can be improved. Furthermore, adjacent active areas AA are designed to have different heights, and the top surface of one active area AA may be concave relative to the top surface of the adjacent active area AA. Therefore, additional portions of adjacent active areas AA, ie, portions formed at the vertex corners of the active areas AA, may also be spaced apart in the vertical direction. Therefore, adjacent active areas AA can be prevented from merging together, and thus interference between memory cells 100 formed on adjacent active areas AA can be avoided.

Figure 3 is a flow chart illustrating a method of preparing the structure shown in Figure 2B according to some embodiments of the present disclosure. 4A to 4K are plan views illustrating structures at an intermediate stage of the preparation method shown in FIG. 3 according to some embodiments of the present disclosure. 5A to 5K are cross-sectional views illustrating structures at an intermediate stage of the preparation method shown in FIG. 3 according to some embodiments of the present disclosure. In particular, FIG. 5B is a cross-sectional view illustrating the structure taken along line AA' shown in FIG. 4B, and FIGS. 5C to 5K are cross-sectional views illustrating the structure taken along line BB' shown in FIGS. 4C to 4K. .

Referring to FIG. 3 , FIG. 4A and FIG. 5A , step S11 is performed, and a first insulating layer 300 , a second insulating layer 302 and a mask layer 304 are sequentially formed on the semiconductor substrate 200 . According to some embodiments, the first insulating layer 300 is made of silicon oxide, and the second insulating layer 302 is made of silicon nitride. In these embodiments, the first insulating layer 300 may be fabricated through a thermal oxidation process or a deposition process (eg, chemical vapor deposition (CVD) process), while the second insulating layer 302 may be fabricated through a deposition process (eg, CVD process). Additionally, in some embodiments, mask layer 304 is a photoresist layer and may be coated on semiconductor substrate 200 . In another embodiment, the mask layer 304 is a hard mask layer, and its manufacturing technology can be through a deposition process (such as a CVD process).

Referring to FIG. 3, FIG. 4B and FIG. 5B, step S13 is performed, and the mask layer 304 is patterned to form a stripe pattern 304a. The stripe pattern 304a may extend along the direction D1, and the direction D1 may be consistent with the direction in which each column of active areas AA shown in FIG. 2A extends. By partially removing the mask layer 304 to form the stripe pattern 304a, portions of the second insulating layer 302 between the stripes 304a may now be exposed. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method for forming the stripe pattern 304a on the mask layer 304 may include a photolithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method for forming the stripe pattern 304a on the mask layer 304 may include a photolithography process and an etching process.

Referring to FIG. 3 , FIG. 4C and FIG. 5C , step S15 is performed, and the stripe pattern 304 a is further patterned to form an array of island patterns 304 b. The island patterns 304b of each column may be arranged along the direction D1, while the island patterns 304b of each row may be arranged along the direction D2 intersecting the direction D1. The island pattern 304b will serve as a shadow mask when forming the initial trench TR′ in subsequent steps. Each row of island patterns 304b is part of the same stripe pattern 304a and may be laterally spaced apart from each other along direction D1. By partially removing the stripe pattern 304a to form the island pattern 304b, portions of the second insulating layer 302 between the island patterns 304b may now be exposed. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method for forming the stripe pattern 304a into the island pattern 304b includes a photolithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method for forming the stripe pattern 304a into the island pattern 304b includes a photolithography process and an etching process.

As described above, in some embodiments, two patterning steps are used to form the island pattern 304b. In another embodiment, a single patterning process may be used to pattern the mask layer 304 shown in FIGS. 4A and 5A into the island pattern 304b shown in FIGS. 4C and 5C.

Referring to FIG. 3 , FIG. 4D and FIG. 5D , step S17 is performed, and an initial trench TR′ is formed in the semiconductor substrate 200 . The initial trench TR' may penetrate a portion of the first and second insulating layers 300, 302, span between the island patterns 304b, and further extend into the semiconductor substrate 200. By forming the initial trench TR', surface portions of the semiconductor substrate 200 are laterally separated from each other and are called initial active areas AA'. The top surfaces of the initial active areas AA' may be substantially coplanar with each other. According to some embodiments, an etching process is used to form the initial trench TR'. During the etching process, the island pattern 304b can be used as a shadow mask. In addition, after the etching process, the island pattern 304b can be removed, and the underlying second insulating layer 302 can be exposed.

Referring to FIG. 3 , FIG. 4E and FIG. 5E , step S19 is performed to remove the first and second insulating layers 300 and 302 . Therefore, the top surface of the initial active area AA' can be exposed. In some embodiments, the method of removing the first and second insulating layers 300, 302 includes an etching process.

Referring to FIG. 3 , FIG. 4F and FIG. 5F , step S21 is performed to form an isolation structure 202 in the initial trench TR′. In some embodiments, methods of preparing isolation structure 202 include providing an insulating material over the structure as shown in Figures 4E and 5E. The insulating material can fill the initial trench TR' and cover the top surface of the initial active area AA'. Subsequently, the portion of the insulating material spanning the top surface of the active area AA may be removed through a planarization process, such as a polishing process and an etching process, or a combination process thereof. Furthermore, a portion of the insulating material filled in the initial trench TR′ may be recessed relative to the top surface of the initial active area AA′, and the remaining insulating material may form the isolation structure 202 . For example, the method of recessing the portion of the insulating material in the initial trench TR′ may include an etching process.

Referring to FIG. 3, FIG. 4G and FIG. 5G, step S23 is performed to selectively form a mask layer 306 on some initial active areas AA'. Therefore, as shown in Figure 5G, one of the adjacent initial active areas AA' is covered by the mask layer 306, while the other may remain exposed. According to some embodiments, the initial active areas AA' of each column are alternately covered along the column direction (eg, direction D1). In these embodiments, the mask layer 306 is periodically arranged along the column direction (eg, direction Dl). For example, a method of preparing the mask layer 306 may include forming a material layer across the entire domain, and patterning the material layer through a photolithography process and an etching process to form the mask layer 306 . The mask layer 306 is made of a material with sufficient etching selectivity relative to the semiconductor substrate 200 .

Referring to FIG. 3 , FIG. 4H and FIG. 5H , step S25 is performed, and the uncovered initial active area AA′ is recessed relative to the initial active area AA′ covered by the mask layer 306 . Therefore, the initial active area AA' is selectively recessed, and forms the active area AA as described with reference to FIG. 2B. As shown in FIG. 5H , the active area AA1 is one of the recessed active areas AA, and the active area AA2 is one of the non-recessed active areas AA. Furthermore, in the recessing step, the initial trench TR′ is shaped to have a trench TR with one side wall higher than the other side wall, as shown in FIG. 2B . In some embodiments, the selective recessing method of the initial active area AA' includes an etching process. In these embodiments, the mask layer 306 and the isolation structure 202 have sufficient etch selectivity with respect to the semiconductor substrate 200 such that the mask layer 306 and the isolation structure 202 may be almost not consumed in the etching process for the semiconductor substrate 200 .

Referring to FIG. 3 , FIG. 4I and FIG. 5I , step S27 is performed to remove the mask layer 306 . With the mask layer 306 removed, the previously covered active area AA can now be exposed. For example, as shown in Figure 5I, active areas AA1 and AA2 can be exposed simultaneously in the current step. According to some embodiments, the method of preparing the mask layer 306 includes an etching process. Since the mask layer 306 has sufficient etching selectivity with respect to the isolation structure 202 and the semiconductor substrate 200 , the isolation structure 202 and the active area AA may be hardly recessed during the etching process.

Referring to Figures 3, 4J and 5J, step S29 is performed to form SAMs 206 on the top surface of the active area AA. According to some embodiments, SAMs 206 are selectively adsorbed on the top surface of active area AA, while the tops of the sidewalls of trench TR' may remain uncovered.

In some embodiments, the SAM-forming compound may be dissolved or dispersed in a solvent. The composition of the solvent is suitable for forming the SAM layer (including SAM-forming compounds). Solvents include, but are not limited to, for example, Toluene, xylene, DCM, chloroform, carbon tetrachloride, ethyl acetate, butyl acetate Butyl acetate, amyl acetate, propylene glycol monomethyl ether acetate (PGMEA), propylene glycol monomethyl ether (PGME), ethoxy ethyl propionate, anisole ), ethyl lactate, diethyl ether, dioxane, tetrahydrofuran (THF), acetonitrile, acetic acid, amyl acetate, acetic acid n-butyl acetate, γ-butyrolactone (GBL), acetone, methyl isobutylketone (methyl isobutylketone), 2-heptanone (2-heptanone), cyclohexanone (cyclohexanone), methanol , ethanol, ethylene glycol ether (2-ethoxyethanol), 2-butoxyethanol (2-butoxyethanol), isopropyl alcohol, n-butanol (n-butanol), N,N-dimethylformamide (DMF) , N,N-dimethylacetamide, pyridine, and dimethyl sulfoxide (DMSO). These solvents can be used alone or in combination.

In some embodiments, any suitable coating technique (eg, dip coating, spin coating) can be used to apply the solution to the top surface of the substrate and then remove the solvent, thus forming an initial SAM layer. The initial SAM layer has a top surface that is in contact with the atmosphere, and a bottom surface that is in contact with a selected surface of the substrate to which the SAM-forming compound has preferential affinity. Generally, the SAM has a thickness of about 0.5 to about 20 nanometers, particularly about 0.5 to about 10 nanometers, or even about 0.5 to 2 nanometers.

Referring to FIG. 3 , FIG. 4K and FIG. 5K , step S31 is performed to form the contact enhancement top cover 204 . According to some embodiments, the contact enhancement cap 204 is fabricated through an epitaxial process. In an epitaxial process, the material of contact enhancement cap 204 may be grown from the exposed portion of active area AA, which is the top of the sidewalls of active area AA, extending between SAM 206 and isolation structure 202 . In some cases, the contact enhancement cap 204 may also extend to the sidewalls of the SAM 206 . By forming the contact enhancement cap 204, the top of the active area AA is laterally surrounded, as described with reference to Figure 2A, with additional portions.

Referring to FIG. 3 and FIG. 2B, step S33 is performed to form a capacitor contact CC on the active area AA. Although not shown, several process steps may be performed before forming capacitor contacts CC. For example, before forming the capacitor contact CC, a dielectric layer (not shown) may be formed throughout the active area AA and the isolation structure 202 . In addition, a through hole may be formed in the dielectric layer through a photolithography process and an etching process to define the location of the capacitor contact CC. Subsequently, the conductive material may be filled into the through hole through a deposition process, an electroplating process, or a combination thereof, and excess conductive material on the dielectric layer may be partially removed through a planarization process. The remaining portion of the conductive material in the via may form the capacitor contact CC.

So far, the structure shown in Figure 2B has been formed. Although not shown, additional process steps may be performed to form other elements of memory array 10 (as described with reference to FIGS. 1B and 2A ), including word lines WL, bit lines BL, and storage capacitors SC. These additional process steps may be performed during and after the process steps described with reference to Figures 3, 4A-4K, 5A-5K, and 2B.

6 is a cross-sectional view illustrating an edge portion of two adjacent active areas AA and a portion of an isolation structure 202 extending between these adjacent active areas AA in some other embodiments of the present disclosure.

Referring to Figure 6, in some embodiments, SAMs 206 described with reference to Figure 2B are omitted. In these embodiments, the top of each active area AA is covered by a contact enhancement cap layer 604 . Contact enhancement cap layer 604 is similar in material selection and functionality to contact enhancement cap 204 (as described with reference to Figure 2B). In other words, the contact enhancement capping layer 604 is semi-conductive or conductive and can be used as an additional portion of the active area AA for improving the electrical contact between the active area AA and the capacitor contact CC standing on the active area AA. In some embodiments, the contact enhancement cap layer 604 includes a contact enhancement layer 604a on the top surface of the active area AA and includes a contact enhancement cap 604b laterally surrounding the top of the active area AA. Contact enhancement cap 604b may extend from contact enhancement layer 604a along the sidewalls of active area AA to the top surface of isolation structure 202 and provide additional landing area for capacitor contacts CC provided on active area AA. In some embodiments, capacitor contact CC penetrates contact enhancement layer 604a to establish electrical contact with active area AA.

As mentioned above, some active areas AA (eg, active area AA1 ) project less than other active areas AA (eg, active area AA2 ) relative to isolation structure 202 . Therefore, the contact enhancement capping layer 604 covering the less protruding active area AA (referred to as contact enhancement capping layer 604 - 1 ) is lower than the contact enhancement capping layer 604 covering the more protruding active area AA (referred to as contact enhancement capping layer 604 -2). In other words, the contact enhancement layer 604a of the contact enhancement cap layer 604-1 may extend on a lower plane than the plane in which the contact enhancement layer 604a of the contact enhancement cap layer 604-2 extends. Additionally, the contact enhancement cap 604b of the contact enhancement cap layer 604-1 may have a height H _604-1 that is shorter than the height H 604-2 of the contact enhancement cap 604b of the contact enhancement cap layer _604-2 . Height H _604-1 is measured from the bottom end of contact enhancement cap 604b of contact enhancement cap layer 604-1 (which may be flush with top surface TS ₂₀₂ of isolation structure 202) to the top end of contact enhancement cap 604b. Likewise, height H _604-2 is measured from the bottom end of contact enhancement cap 604b of contact enhancement cap layer 604-2 (which may be flush with top surface TS ₂₀₂ of isolation structure 202) to the top end of contact enhancement cap 604b. Since the contact enhancement cap layer 604-1 is lower than the contact enhancement cap layer 604-2, the top corners of the contact enhancement cap layers 604-1, 604-2 can be further spaced apart in the vertical direction. Therefore, when adjacent active areas AA When the width of the trench TR is greatly reduced, the contact enhancement cover layers 604-1 and 604-2 can be prevented from merging. Therefore, interference between memory cells 100 formed on adjacent active areas AA can be avoided.

In preparing the structure as shown in Figure 6, the step of forming the SAM 206 (as described with reference to Figures 4J and 5J) can be omitted. In addition, after the active area AA1 is recessed and the mask layer 306 is removed (as described with reference to FIGS. 4H-4I and 5H-5I ), a contact enhancement capping layer 604 is formed on the active area AA by, for example, an epitaxial process. In addition, the capacitor contact CC may be formed on the active area AA.

As mentioned above, the active area of a memory cell in a memory array has extra portions (i.e., contact-enhancing caps) at its top corners. By having these extra sections, the active area can provide a larger landing area for the capacitor contacts standing on the active area. Therefore, the electrical contact between the capacitor contacts and the active region may be less affected by process variations in arranging the capacitor contacts. In other words, the electrical contact between the capacitor contacts and the active area can be improved. Furthermore, adjacent active regions are designed to have different heights, and the top surface of one active region may be concave relative to the top surface of an adjacent active region. Therefore, additional portions of adjacent active areas can be further spaced apart vertically. Therefore, adjacent active areas can be prevented from merging together, thus avoiding interference between memory cells formed on adjacent active areas.

In an embodiment of the present disclosure, a method for manufacturing a memory array is provided, including: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated cells formed by a surface area of the semiconductor substrate. Active region; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active regions; moving a first group of active regions of the active regions from a top surface recess, while covering a top surface of a second group of active areas of the plurality of active areas; and integrating to form a plurality of contact-enhancing sidewall spacers and a plurality of contact-enhancing top covers, the contact-enhancing sidewall gaps The sub-surface laterally surrounds the tops of the active areas, and the contact enhancement top covers cover the upper surfaces of the active areas.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, materials that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with the present disclosure. Composition, means, method, or step. Accordingly, these processes, machines, manufactures, material compositions, means, methods, or steps are included in the disclosed claims of the present disclosure.

Claims (9)

1. A method of preparing a memory array, comprising: Forming a trench on a front side of a semiconductor substrate, wherein the trench defines a plurality of laterally separated active regions formed by a surface region of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the plurality of active regions; Recessing a first group of active areas of the plurality of active areas from a top surface while covering a top surface of a second group of active areas of the plurality of active areas; and A plurality of contact-enhancing sidewall spacers and a plurality of contact-enhancing top covers are integrally formed. The plurality of contact-enhancing sidewall spacers laterally surround the tops of the plurality of active regions. The plurality of contact-enhancing top covers cover the plurality of active areas. the upper surface of the area. 2. The method of manufacturing a memory array as claimed in claim 1, wherein the formation of the trench comprises: forming at least one insulating layer on the front side of the semiconductor substrate; forming a plurality of mask patterns on the at least one insulating layer; performing an etching process on the at least one insulating layer and the semiconductor substrate to form the trench by using the plurality of mask patterns as a shadow mask; and The plurality of mask patterns and the at least one insulation layer are removed. 3. The method of manufacturing a memory array according to claim 2, wherein the at least one insulating layer includes a first insulating layer and a second insulating layer stacked on the first insulating layer. 4. The method of manufacturing a memory array according to claim 1, wherein forming the isolation structure includes: providing an insulating material in the trench; and The insulating material is recessed, thereby recessing the insulating material relative to the top surface of the active region, and forming the isolation structure. 5. The method of manufacturing a memory array according to claim 1, wherein the second group of active areas is covered by a plurality of mask layers, and the first group of active areas is recessed and forms a plurality of contact enhancement sidewalls. Before spacers, remove the multiple mask layers. 6. The method of preparing a memory array according to claim 1, further comprising: Before forming the contact enhancement caps, a plurality of self-assembled monolayers are formed on the top surfaces of the active regions. 7. The method of manufacturing a memory array according to claim 6, wherein before forming the contact enhancement caps, sidewalls of the tops of the active regions remain uncovered by the self-assembled monolayers. 8. The method of manufacturing a memory array as claimed in claim 6, wherein the method of manufacturing the plurality of contact enhancement caps includes an epitaxial process. 9. The method of manufacturing a memory array as claimed in claim 1, wherein the plurality of contact enhancement top caps and the plurality of contact enhancement sidewall spacers cover tops of the plurality of active regions.