CN117337036A

CN117337036A - Method for preparing memory array with contact enhancement top cover

Info

Publication number: CN117337036A
Application number: CN202311498596.8A
Authority: CN
Inventors: 许平
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2021-11-17
Filing date: 2022-06-23
Publication date: 2024-01-02
Also published as: CN116156871A; TW202410415A; TWI833159B; TW202322365A

Abstract

The present disclosure provides a method of fabricating a dynamic random access memory array with a contact enhanced cap. The method comprises the following steps: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated active regions formed by a surface region of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active regions; recessing a first set of active regions of the plurality of active regions from a top surface while covering a top surface of a second set of active regions of the plurality of active regions; and integrally forming a plurality of contact enhancement sidewall spacers and a plurality of contact enhancement caps, wherein the contact enhancement sidewall spacers transversely surround the tops of the active regions, and the contact enhancement caps cover the upper surfaces of the active regions.

Description

Method for preparing memory array with contact enhancement top cover

The present application is a division of chinese patent application No. 202210723522.9, filed on day 2022, month 6, and 23, entitled "memory array with contact enhancing cap and method of making same," application No. 202210723522.9, claims priority and benefit of U.S. official application No. 17/528,505 and U.S. official application No. 17/528,617, filed on day 2021, month 11, and 17, the contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a memory array and a method for fabricating the same, and more particularly, to a dynamic random access memory (dynamic random access memory, DRAM) array with a contact enhanced cap and a method for fabricating the same.

Background

In recent decades, as electronic products continue to improve, the need for memory capacity has increased. In order to improve the storage capacity of a memory element (e.g., a DRAM element), more memory cells (memory cells) are arranged in the memory element, and the size of each memory cell in the memory element becomes smaller. The memory cells are each fabricated on an active region, which may be part of a semiconductor substrate. Scaling of the active area is an option to reduce the size of each memory cell.

Each DRAM cell may include a storage capacitor disposed on the active region and connected to the active region through a capacitor contact. The reduction in active area may result in a reduction in the landing area for capacitor contacts. Accordingly, the contact resistance between the capacitor contact and the active region may be increased due to the semiconductor photolithography process overlay (lithography overlay) problem. In other words, pursuing high memory density by minimizing the active area may impair the performance of the DRAM device. There is a need in the art for a method of increasing the landing area of a capacitor contact without expanding the layout pattern of the active area.

The above description of "prior art" merely provides background, and it is not admitted that the above description of "prior art" reveals the subject matter of the present disclosure, the prior art of the present disclosure is not provided, and any description of "prior art" above should not be taken as any part of the present disclosure.

Disclosure of Invention

In one embodiment of the present disclosure, a method for manufacturing a memory array is provided, including: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated active regions formed by a surface region of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active regions; recessing a first set of active regions of the plurality of active regions from a top surface while covering a top surface of a second set of active regions of the plurality of active regions; and integrally forming a plurality of contact enhancement sidewall spacers and a plurality of contact enhancement caps, wherein the contact enhancement sidewall spacers transversely surround the tops of the active regions, and the contact enhancement caps cover the upper surfaces of the active regions.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages of the present disclosure that set forth the subject matter of the claims will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure will be more fully understood when the detailed description and the appended claims are taken together and considered to be read in connection with the accompanying drawings, in which like reference numerals refer to like elements.

Fig. 1A is a circuit diagram illustrating memory cells in a memory array according to some embodiments of the present disclosure.

FIG. 1B is a block diagram illustrating a memory array including a plurality of memory cells according to some embodiments of the present disclosure.

Fig. 2A is a plan view illustrating a partial layout of a memory array according to some embodiments of the present disclosure.

Figure 2B is a cross-sectional view illustrating edge portions of two adjacent active areas and a portion of an isolation structure extending between the adjacent active areas in accordance with some embodiments of the present disclosure.

Fig. 3 is a flow chart illustrating a method of preparing the structure shown in fig. 2B according to some embodiments of the present disclosure.

Fig. 4A to 4K are plan views illustrating structures of intermediate stages of the preparation method shown in fig. 3 according to some embodiments of the present disclosure.

Fig. 5A to 5K are cross-sectional views illustrating structures at intermediate stages of the preparation method shown in fig. 3 according to some embodiments of the present disclosure.

Figure 6 is a cross-sectional view illustrating edge portions of two adjacent active regions and a portion of an isolation structure extending between the adjacent active regions in accordance with some other embodiments of the present disclosure.

Reference numerals illustrate:

10: memory array

100: memory cell

200: semiconductor substrate

202: isolation structure

204: contact enhancement top cap

204-1: contact enhancement top cap

204-2: contact enhancement top cap

206: self-assembled monolayer (SAM)

206-1: self-assembled monolayer

206-2: self-assembled monolayer

300: a first insulating layer

302: second insulating layer

304: mask layer

304a: stripe pattern

304b: island pattern

306: mask layer

604: contact enhancement cap layer

604-1: contact enhancement cap layer

604-2: contact enhancement cap layer

604a: contact enhancement layer

604b: contact enhancement top cap

AA: active region

AA': initial active region

A-A': wire (C)

AA1: active region

AA2: active region

AT: access transistor

B-B': wire (C)

BL: bit line

CC: capacitor contact

CC1: capacitor contact

CC2: capacitor contact

D1: direction of

D2: direction of

H1: height of (1)

H2: height of (1)

H202: height of (1)

H204-1: height of (1)

H204-2: height of (1)

H604-1: height of (1)

H604-2: height of (1)

S11: step (a)

S13: step (a)

S15: step (a)

S17: step (a)

S19: step (a)

S21: step (a)

S23: step (a)

S25: step (a)

S27: step (a)

S29: step (a)

S31: step (a)

S33: step (a)

SC: storage capacitor

SW1: side wall

SW2: side wall

TR: groove(s)

TR': initial trench

TS1: top surface

TS2: top surface

TS202: top surface

WL: word line

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired properties of the elements. Furthermore, the formation of a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. For simplicity and clarity, some features may be arbitrarily drawn in different scales. In the drawings, some layers/features may be omitted for simplicity.

Further, for ease of description, spatially relative terms, such as "below", "lower", "above", "upper", and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The elements may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1A is a circuit diagram illustrating a memory cell (memory cell) 100 in a memory array according to some embodiments of the present disclosure. Referring to fig. 1A, the memory array may be a dynamic random access memory (dynamic random access memory, DRAM) array structure. Each memory cell 100 in the memory array may include an access transistor AT and a storage capacitor SC. The access transistor AT may be a field effect transistor (field effect transistor, FET). One terminal of the storage capacitor SC is coupled to the source/drain terminal of the access transistor AT, while the other terminal of the storage capacitor SC may be coupled to a reference voltage (e.g., ground voltage as depicted in fig. 1A). When the access transistor AT is turned on (turn on), the storage capacitor SC can be accessed. On the other hand, when the access transistor AT is in the off state (off state), the storage capacitor SC cannot be accessed.

During a write operation, the access transistor AT is turned on by asserting the word line WL coupled to a gate terminal of the access transistor AT, and the voltage applied to the bit line BL (coupled to one source/drain terminal of the access transistor AT) may be transferred to the storage capacitor SC (coupled to the other source/drain terminal of the access transistor AT). Accordingly, the storage capacitor SC may be charged or discharged, and a logic state "1" or a logic state "0" may be stored in the storage capacitor SC. During a read operation, the access transistor AT is also turned on, and the pre-charged bit line BL may be pulled high or low according to the charge state of the storage capacitor SC. By comparing the voltage of the bit line BL and the precharge voltage, the charge state of the storage capacitor SC can be sensed, and the logic state of the memory cell 100 can be recognized.

FIG. 1B is a block diagram illustrating a memory array 10 including a plurality of memory cells 100 according to some embodiments of the present disclosure. Referring to fig. 1B, the memory array 10 has columns (row) and rows (column). The memory cells 100 of each column may be arranged along a first direction, and the memory cells 100 of each row may be arranged along a second direction intersecting the first direction. A plurality of bit lines BL may be respectively coupled to one column of the memory cells 100. On the other hand, a plurality of word lines WL may be coupled to one row of the memory cells 100, respectively. In some embodiments, during a write operation, a word line WL coupled to the selected memory cell 100 is asserted and the storage capacitor SC in the selected memory cell 100 is programmed (programmed) by providing a voltage to a bit line coupled to the selected memory cell 100. In addition, during a read operation, all bit lines BL are precharged and the word line WL coupled to the selected memory cell 100 is asserted, and then the precharged bit line BL is pulled high or low by the storage capacitor SC coupled to the asserted word line WL, respectively. By detecting a voltage change of the bit line BL coupled to the selected memory cell 100, the logic state of the selected memory cell 100 can be identified. As the pre-charge bit line BL is pulled high and/or low, the stored charge in the storage capacitor SC of the memory cell 100 coupled to the asserted word line WL is changed. To restore the logic states of the memory cells 100, a write operation, which may also be referred to as a refresh operation, may be performed after the read operation to program the previous logic states to the memory cells 100.

Fig. 2A is a plan view illustrating a partial layout of a memory array 10 according to some embodiments of the present disclosure.

Referring to fig. 1B and 2A, the memory array 10 may be built on a semiconductor substrate 200. The semiconductor substrate 200 may be, for example, a semiconductor wafer (wafer) or a semiconductor-on-insulator (SOI) wafer. The semiconductor substrate 200 has surface portions laterally separated from each other, which are called Active Areas (AA). The isolation structures 202 extending in the semiconductor substrate 200 may laterally surround each of the active regions AA to physically and electrically isolate the active regions AA from each other. In other words, the active area AA is defined by the isolation structure 202.

According to some embodiments, the active areas AA may be arranged in an array having a plurality of rows and a plurality of columns. Word lines WL may be formed in the semiconductor substrate 200, and each word line laterally penetrates a row of the active area AA. On the other hand, bit lines BL may be formed on the semiconductor substrate 200 and each intersect with one row of the active regions AA.

The access transistor AT in each memory cell 100 of the memory array 10 is defined in the vicinity of the intersection of the active area AA with the intersecting word line WL and the intersecting bit line BL. The word line WL serves as a gate terminal of the access transistor AT, and portions of the active area AA located on opposite sides of the word line WL may serve as source/drain terminals of the access transistor AT. The bit line BL is coupled to one of the source and/or drain terminals. In addition, another source/drain terminal may be coupled with one of the storage capacitors SC formed over the semiconductor substrate 200. It should be understood that the storage capacitor SC is depicted as a separate pattern, representing a separate bottom electrode of the storage capacitor SC. Although not shown, the storage capacitors SC may actually have a common top electrode.

In some embodiments, the word lines WL extend in a first direction. In addition, the bit line BL may extend in a second direction substantially perpendicular to the first direction. Alternatively, each bit line BL may be curved along its extending direction (e.g., the second direction). In addition, the active areas AA may each extend along a third direction intersecting the first direction and the second direction.

In some embodiments, each active area AA is shared by two access transistors AT having a common source/drain terminal. In these embodiments, each active area AA is penetrated by two word lines WL and intersects one of the bit lines BL. Furthermore, each active region AA may overlap two storage capacitors SC. The bit line BL overlaps and is electrically connected to a portion of the active region AA that spans between the two word lines WL, which may serve as a common source/drain terminal for the two access transistors AT. Other portions of the active area AA on opposite sides of the two word lines WL may serve as separate source/drain terminals of the two access transistors AT and may overlap and electrically connect with the two overlying storage capacitors SC, respectively.

Figure 2B is a cross-sectional view illustrating edge portions of two adjacent active regions AA and a portion of an isolation structure 202 extending between adjacent active regions AA in accordance with some embodiments of the present disclosure.

Referring to fig. 2B, an isolation structure 202 is formed in a trench TR of the semiconductor substrate 200, the trench TR extending from a top surface of the semiconductor substrate 200 into the semiconductor substrate 200 and laterally separating the active region AA. In addition, some of the active regions AA may be recessed with respect to other active regions AA, and the top surface of the semiconductor substrate 200 in some regions of those recessed active regions AA may be lower than in other regions of the non-recessed active regions AA. As illustrated in fig. 2B, one of the active regions AA (also referred to as active region AA 1) is recessed relative to the adjacent active region AA (also referred to as active region AA 2). Thus, the height H1 of the active region AA1 (measured from a depth flush with the bottom end of the isolation structure 202 to the top surface TS1 of the active region AA 1) is less than the height H2 of the active region AA2 (measured from a depth flush with the bottom end of the isolation structure 202 to the top surface TS2 of the active region AA 2).

Since the active regions AA1, AA2 have different heights, the trench TR extending between the active regions AA1, AA2 may have an asymmetric shape. As illustrated in fig. 2B, i.e., the active region AA 1is recessed with respect to the active region AA2, the sidewall SW1 of the trench TR defining the boundary of the active region AA1 may be lower than the sidewall SW2 of the trench TR defining the boundary of the active region AA 2. The heights of the sidewalls SW1, SW2 are substantially equal to the heights of H1, H2, respectively. To avoid redundancy, the ratio and range of heights H1, H2 are not repeated.

According to some embodiments, top surface TS of isolation structure 202 filled in trench TR ₂₀₂ Lower than the top surface TS1 of the active area AA1 and lower than the top surface TS2 of the active area AA 2. In these embodiments, the height H of the isolation structure 202 ₂₀₂ (measured from the bottom end of isolation structure 202 to the top surface TS of isolation structure 202) ₂₀₂ ) Less than the height H1 of the active area AA1 and less than the height H2 of the active area AA 2. Since the isolation structure 202 does not fill the trench TR, the top of the sidewalls SW1, SW2 of the trench TR are not covered by the isolation structure 202. Since sidewall SW2 is higher than sidewall SW1, the top of sidewall SW2 that spans over isolation structure 202 may be larger (higher) than the top of sidewall SW1 that spans over isolation structure 202.

In some embodiments, the top of each active area AA is laterally surrounded by the contact enhancement cap 204, while the remainder of each active area AA is laterally surrounded by the isolation structure 202. The contact enhancement cap 204 is semiconductive or conductive and may be used as an additional portion of the active area AA. By having such an additional portion, the active area AA may provide a larger landing area (landing area) for the capacitor contact CC connecting the active area AA and the upper storage capacitor SC, as shown in fig. 2A. Accordingly, tolerance of the capacitor contact CC to the setting tolerance can be increased, and good electrical contact between the capacitor contact CC and the active area AA can be ensured. For example, the contact enhancement cap 204 comprises silicon whose fabrication technique is an epitaxial (epi) process.

Since the protruding degree of the active region AA1 with respect to the isolation structure 202 is smaller than that of the active region AA2, the height H of the contact enhancing cap 204-1 laterally surrounding the top of the active region AA1 _204-1 May be shorter than the height H of the contact enhancement cap 204-2 laterally surrounding the top of the active area AA2 _204-2 . Height of (1) _H204-1 From the bottom end of the contact enhancement cap 204-1, which may be in contact with the top surface TS of the isolation structures 202 ₂₀₂ Flush, the top end of the contact enhancement cap 204-1 is measured. Also, height H _204-2 From the bottom end of the contact enhancement cap 204-2, which may be in contact with the top surface TS of the isolation structures 202 ₂₀₂ Flush, the top end of the contact enhancement cap 204-2 is measured. Since the contact enhancing caps 204-1, 204-2 are spaced from the top surface TS of the isolation structures 202 ₂₀₂ The top corners of the contact enhancing caps 204-1, 204-2 may have substantial lateral thickness (not shown) extending to different heights and may be more vertically spaced apart. Thus, the contact enhancement caps 204-1, 204-2 may be prevented from merging, particularly when the width of the trench TR between the active regions AA1, AA2 is more reduced. Thus, interference between memory cells 100 formed on adjacent active regions AA can be avoided.

In some embodiments, the top surface of each active region AA is covered by a self-assembled monolayer (self-assembly monolayer, SAM) 206. The self-assembled monolayer 206 may be selectively formed on the top surface of each active region AA and may not extend to the sidewalls of each active region AA. That is, the top of the sidewalls of each active region AA that spans over isolation structures 202 is not covered by SAM 206. Thus, the contact enhancement cap 204 formed after the SAM 206 may be disposed on top of the sidewalls of the active region AA. According to some embodiments, the contact enhancing cap 204 may also extend to the sidewalls of the SAM 206. In these embodiments, the top end of the contact enhancing cap 204 may be substantially flush with the top surface of the SAM 206.

Since the active area AA 1is recessed with respect to the active area AA2, the top surface TS1 of the active area AA 1is lower than the top surface TS2 of the active area AA 2. Thus, SAM 206 (also referred to as SAM 206-1) covering the top surface TS1 of active area AA 1is lower than SAM 206 (also referred to as SAM 206-2) covering the top surface TS2 of active area AA 2.

Self-assembled monolayers (SAMs) are well known in the art. For example, reference is made to "Reactive Monolayers in Directed Additive Manufacturing-Area Selective Atomic Layer Deposition" Rudy j.wojitecki et al, journal of Photopolymer Science and Technology,2018Volume 31Issue 3Pages 431-436, which is incorporated herein by reference. In some embodiments, SAMs206 comprises organic molecules. According to some embodiments, SAMs206 comprises a plurality of molecules having a chemical formula selected from the group consisting of X-R1-SH, X-R1-S-R2-Y, R1-S-R2, and combinations thereof, wherein R1 and R2 are independent carbon chains or carbon chains interrupted by at least one heteroatom, wherein H is hydrogen, wherein S is sulfur, and wherein X and Y are chemical groups that do not substantially chemically react with the copper surface. In some embodiments, at least one of R1 and R2 is a chain of n carbon atoms, where n is an integer from 1 to 30. In some embodiments, SAMs206 has the formula SH (CH ₂ ) ₉ CH ₃ 。

In some embodiments, the fabrication technique of the SAM is a monolayer self-assembled by a polymerizable compound. The thickness of the monolayer corresponds to the length of one molecule of the compound in the close-packed structure of the monolayer. The close-packed structure is aided by functional groups (functional groups) of the compound that bind to surface groups of the substrate by electrostatic interactions and/or one or more covalent bonds. The portion of the compound that binds to the surface of the substrate is referred to herein as the "head" of the compound. The remainder of the compound is referred to as the "tail". The tail extends from the head of the compound to the atmosphere interface of the top surface of the SAM. The tail portion has a non-polar peripheral end group at the atmospheric interface. Thus, a good SAM has few defects in its close-packed structure and can exhibit a high contact angle.

The head of the SAM-forming compound can be selectively bonded to a portion of the top surface of a substrate that includes regions of different composition such that no or substantially no SAM-forming compound is disposed on other portions of the top surface of the substrate. In this case, the patterned initial SAM can be formed in one step by immersing the substrate in a solution of the given SAM-forming compound (dissolved by an appropriate solvent). In some embodiments, the wavelength of the ultraviolet radiation may be from about 4 nanometers (nm) to 450 nm. The wavelength of Deep Ultraviolet (DUV) radiation may be from 124 nanometers to 300 nanometers. The wavelength of Extreme Ultraviolet (EUV) radiation may be from about 4 nanometers to less than 124 nanometers.

In those embodiments in which each active area AA is covered by a SAM 206, a capacitor contact CC disposed on the active area AA may penetrate the SAM 206 to establish electrical contact with the active area AA. Likewise, other contacts (e.g., bit line contacts (not shown)) may also pass through the SAM 206 to reach the active area AA. Furthermore, in some embodiments, the capacitor contact CC extending to the lower active region AA may be higher than the capacitor contact CC extending to the higher active region AA. As illustrated in fig. 2B, the capacitive contact CC (also referred to as capacitive contact CC 1) extending to active region AA1 may be higher than the capacitive contact CC (also referred to as capacitive contact CC 2) extending to active region AA 2.

As described above, the active area AA of the memory cell 100 in the memory array 10 has an additional portion (i.e., contact enhancement cap 204) at its top corner. By having these additional portions, the active area AA can provide a larger landing area for the capacitor contacts CC standing on the active area AA. Thus, the electrical contact between the capacitor contact CC and the active region AA may be less affected by process variations (e.g., photolithographic overlay problems) in the placement of the capacitor contact CC. In other words, the electrical contact between the capacitor contact CC and the active area AA can be improved. In addition, adjacent active regions AA are designed to have different heights, and the top surface of one active region AA may be recessed with respect to the top surface of an adjacent active region AA. Thus, additional portions of adjacent active regions AA, i.e., portions formed at the top corners of the active regions AA, may also be spaced apart in the vertical direction. Accordingly, adjacent active regions AA can be prevented from being merged together, and thus interference between memory cells 100 formed on the adjacent active regions AA can be avoided.

Fig. 3 is a flow chart illustrating a method of preparing the structure shown in fig. 2B according to some embodiments of the present disclosure. Fig. 4A to 4K are plan views illustrating structures of intermediate stages of the preparation method shown in fig. 3 according to some embodiments of the present disclosure. Fig. 5A to 5K are cross-sectional views illustrating structures at intermediate stages of the preparation method shown in fig. 3 according to some embodiments of the present disclosure. In particular, fig. 5B is a sectional view illustrating a structure taken along the line A-A 'shown in fig. 4B, and fig. 5C to 5K are sectional views illustrating a structure taken along the line B-B' shown in fig. 4C to 4K.

Referring to fig. 3, 4A and 5A, step S11 is performed, and a first insulating layer 300, a second insulating layer 302 and a mask layer 304 are sequentially formed on the semiconductor substrate 200. According to some embodiments, the fabrication technique of the first insulating layer 300 is silicon oxide, and the fabrication technique of the second insulating layer 302 is silicon nitride. In these embodiments, the fabrication technique of the first insulating layer 300 may be through a thermal oxidation process or a deposition process (e.g., a Chemical Vapor Deposition (CVD) process), while the fabrication technique of the second insulating layer 302 may be through a deposition process (e.g., a CVD process). Furthermore, in some embodiments, the mask layer 304 is a photoresist layer and may be coated on the semiconductor substrate 200. In another embodiment, the mask layer 304 is a hard mask layer, which may be fabricated by a deposition process (e.g., a CVD process).

Referring to fig. 3, 4B and 5B, step S13 is performed, and the mask layer 304 is patterned to form a stripe pattern 304a. The stripe pattern 304a may extend in a direction D1, and the direction D1 may be identical to the direction in which each column of the active regions AA extends as shown in fig. 2A. By partially removing the mask layer 304 to form the stripe pattern 304a, portions of the second insulating layer 302 between the stripes 304a may be exposed at present. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method that causes the mask layer 304 to form the stripe pattern 304a may include a photolithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method for forming the mask layer 304 into the stripe pattern 304a may include a photolithography process and an etching process.

Referring to fig. 3, 4C and 5C, step S15 is performed, and the stripe pattern 304a is further patterned to form an array of island patterns 304b. The island patterns 304b of each column may be arranged along the direction D1, while the island patterns 304b of each row may be arranged along the direction D2 intersecting the direction D1. Island pattern 304b will act as a shadow mask when forming the initial trench TR' in a subsequent step. The island patterns 304b of each column are part of the same stripe pattern 304a and may be laterally spaced from each other along the direction D1. By partially removing the stripe patterns 304a to form island patterns 304b, portions of the second insulating layer 302 between the island patterns 304b may be exposed at present. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method that forms the stripe pattern 304a into the island pattern 304b includes a photolithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method for forming the stripe pattern 304a into the island pattern 304b includes a photolithography process and an etching process.

As described above, in some embodiments, two patterning steps are used to form island pattern 304b. In another embodiment, the mask layer 304 shown in fig. 4A and 5A may be patterned into the island pattern 304b shown in fig. 4C and 5C using a single patterning process.

Referring to fig. 3, 4D, and 5D, step S17 is performed, and an initial trench TR' is formed in the semiconductor substrate 200. The initial trench TR' may penetrate a portion of the first and second insulating layers 300, 302, cross between the island patterns 304b, and extend further into the semiconductor substrate 200. By forming the initial trench TR ', surface portions of the semiconductor substrate 200 are separated from each other in a lateral direction and are referred to as initial active regions AA'. The top surfaces of the initial active regions AA' may be substantially coplanar with each other. According to some embodiments, the initial trench TR' is formed using an etching process. In the etching process, the island pattern 304b may be used as a shadow mask. In addition, after the etching process, the island pattern 304b may be removed while the underlying second insulating layer 302 may be exposed.

Referring to fig. 3, 4E and 5E, step S19 is performed to remove the first and second insulating layers 300, 302. Thus, the top surface of the initial active region AA' may be exposed. In some embodiments, the method of removing the first and second insulating layers 300, 302 includes an etching process.

Referring to fig. 3, 4F and 5F, step S21 is performed to form an isolation structure 202 in the initial trench TR'. In some embodiments, the method of making the isolation structure 202 includes providing an insulating material over the structure as shown in fig. 4E and 5E. The insulating material may fill the initial trench TR 'and cover the top surface of the initial active region AA'. Subsequently, portions of the insulating material that span the top surface of the active area AA may be removed by a planarization process, such as a polishing (polishing) process and an etching process, or a combination thereof. In addition, a portion of the insulating material filled in the initial trench TR 'may be recessed with respect to a top surface of the initial active region AA', and the remaining insulating material may form the isolation structure 202. For example, the recessing method of the portion of the insulating material in the initial trench TR' may include an etching process.

Referring to fig. 3, 4G and 5G, step S23 is performed to selectively form a mask layer 306 on some of the initial active areas AA'. Thus, as shown in fig. 5G, one of the adjacent initial active areas AA' is covered by the mask layer 306, while the other may remain exposed. According to some embodiments, the initial active regions AA' of each column are alternately covered along the column direction (e.g., direction D1). In these embodiments, the mask layers 306 are periodically arranged along the column direction (e.g., direction D1). For example, the mask layer 306 may be prepared by forming a globally crossing material layer and patterning the material layer by a photolithography process and an etching process to form the mask layer 306. The masking layer 306 is fabricated from a material having sufficient etch selectivity relative to the semiconductor substrate 200.

Referring to fig. 3, 4H and 5H, step S25 is performed in which the uncovered initial active area AA 'is recessed with respect to the initial active area AA' covered by the mask layer 306. Thus, the initial active region AA' is selectively recessed and forms the active region AA as described with reference to fig. 2B. As shown in fig. 5H, the active area AA 1is one of the recessed active areas AA, and the active area AA2 is one of the non-recessed active areas AA. Further, in the recessing step, the initial trench TR' is shaped to have a trench TR with a sidewall higher than the other sidewall, as shown in fig. 2B. In some embodiments, the selective recessing method of the initial active area AA' includes an etching process. In these embodiments, the mask layer 306 and the isolation structure 202 have a sufficient etch selectivity with respect to the semiconductor substrate 200, so that the mask layer 306 and the isolation structure 202 may be hardly consumed in the etching process for the semiconductor substrate 200.

Referring to fig. 3, 4I and 5I, step S27 is performed to remove the mask layer 306. With the mask layer 306 removed, the previously covered active area AA may be exposed at the present time. For example, as shown in fig. 5I, the active areas AA1, AA2 may be exposed simultaneously in the current step. According to some embodiments, the method of preparing the mask layer 306 includes an etching process. Since the mask layer 306 has a sufficient etch selectivity with respect to the isolation structure 202 and the semiconductor substrate 200, the isolation structure 202 and the active region AA may be hardly recessed in the etching process.

Referring to fig. 3, 4J and 5J, step S29 is performed to form SAMs206 on the top surface of the active area AA. SAMs206, according to some embodiments, selectively adsorbs on the top surface of active area AA while the top of the sidewalls of trench TR' may remain uncovered.

In some embodiments, the SAM-forming compound may be dissolved or dispersed in a solvent. The composition of the solvent is suitable for forming a SAM layer (including SAM-forming compounds). Solvents include, but are not limited to, for example, toluene (Toluene), xylene (xylene), dichloromethane (DCM), chloroform (chloroformate), carbon tetrachloride (carbon tetrachloride), ethyl acetate (ethyl acetate), butyl acetate (butyl acetate), amyl acetate (amyl acetate), propylene Glycol Monomethyl Ether Acetate (PGMEA), propylene Glycol Monomethyl Ether (PGME), ethoxyethyl propionate (ethoxy ethyl propionate), anisole (anisole), ethyl lactate (methyl lactate), diethyl ether (diethyl ether), dioxane (dioxane), tetrahydrofuran (THF), acetonitrile (acetyl), acetic acid (acetic acid), amyl acetate (amyl acetate), N-butyl acetate (N-butyl acetate), gamma-butyrolactone (GBL), acetone, methyl isobutyl ketone (methyl isobutyl ketone), 2-heptanone (2-heptane), cyclohexanone (methyl), methyl alcohol, ethyl alcohol (2-ethyl alcohol), diethyl ether (2-ethyl alcohol), diethyl amide (N-butyl alcohol), diethyl amide (N-methyl ethyl alcohol), diethyl amide (N-butyl alcohol, N-methyl ethyl alcohol), dimethyl amide (dimethyl sulfoxide (N-butyl alcohol, N-methyl amide). These solvents may be used alone or in combination.

In some embodiments, the solution may be applied to the top surface of the substrate using any suitable coating technique (e.g., dip coating, spin coating), and then the solvent is removed, thus forming an initial SAM layer. The initial SAM layer has a top surface that is in contact with the atmosphere and a bottom surface that is in contact with a selected surface of the substrate (the surface having preferential affinity for SAM-forming compounds). Generally, the SAM has a thickness of about 0.5 to about 20 nanometers, particularly about 0.5 to about 10 nanometers, and even about 0.5 to 2 nanometers.

Referring to fig. 3, 4K and 5K, step S31 is performed to form the contact enhancing cap 204. According to some embodiments, the fabrication technique of contact enhancement cap 204 is by an epitaxial process. During the epitaxial process, material contacting enhancement cap 204 may grow from the exposed portion of active region AA, which is the top of the sidewalls of active region AA, extending between SAM 206 and isolation structure 202. In some cases, contact enhancement cap 204 can also extend to the sidewalls of SAM 206. By forming the contact enhancement cap 204, the top of the active area AA is laterally surrounded, with additional portions as described with reference to fig. 2A.

Referring to fig. 3 and 2B, step S33 is performed to form a capacitor contact CC on the active area AA. Although not shown, several process steps may be performed prior to forming capacitor contact CC. For example, a dielectric layer (not shown) may be formed over the active area AA and the isolation structure 202 prior to forming the capacitor contact CC. In addition, a via (through hole) may be formed in the dielectric layer by a photolithography process and an etching process to define the position of the capacitor contact CC. Subsequently, the conductive material may be filled into the via by a deposition process, an electroplating process, or a combination thereof, and the excess conductive material portion on the dielectric layer may be removed by a planarization process. The remaining portion of the conductive material in the via may form capacitor contact CC.

Up to this point, the structure shown in fig. 2B has been formed. Although not shown, additional process steps may be performed to form other elements of the memory array 10 (as described with reference to fig. 1B and 2A), including word lines WL, bit lines BL, and storage capacitors SC. These additional process steps may be performed during and after the process steps described with reference to fig. 3, 4A-4K, 5A-5K, and 2B.

Figure 6 is a cross-sectional view illustrating edge portions of two adjacent active regions AA and a portion of an isolation structure 202 extending between the adjacent active regions AA in accordance with some other embodiments of the present disclosure.

Referring to FIG. 6, in some embodiments, SAMs206 described with reference to FIG. 2B is omitted. In these embodiments, the top of each active area AA is covered by a contact enhancement cap layer 604. The contact enhancing cap layer 604 is similar in material selection and function to the contact enhancing cap 204 (as described with reference to fig. 2B). In other words, the contact enhancing cap layer 604 is semiconductive or conductive and may serve as an additional portion of the active area AA for improving electrical contact between the active area AA and the capacitor contact CC standing on the active area AA. In some embodiments, the contact enhancement cap layer 604 includes a contact enhancement layer 604a on top of the active area AA and includes a contact enhancement cap 604b laterally surrounding the top of the active area AA. The contact enhancement cap 604b can extend from the contact enhancement layer 604a along the sidewalls of the active region AA to the top surface of the isolation structure 202 and provide an additional landing area for the capacitor contact CC provided on the active region AA. In some embodiments, capacitor contact CC penetrates contact enhancement layer 604a, establishing electrical contact with active area AA.

As described above, some active regions AA (e.g., active region AA 1) protrude less than other active regions AA (e.g., active region AA 2) relative to the isolation structure 202. Thus, the contact enhancing cap layer 604 (referred to as contact enhancing cap layer 604-1) covering the less protruding active region AA is lower than the contact enhancing cap layer 604 (referred to as contact enhancing cap layer 604-2) covering the more protruding active region AA. In other words, the contact enhancing layer 604a of the contact enhancing cap layer 604-1 may extend on a lower plane than the plane on which the contact enhancing layer 604a of the contact enhancing cap layer 604-2 extends. In addition, the contact enhancing cap 604b of the contact enhancing cap layer 604-1 may have a height H _604-1 Height H of contact enhancement cap 604b shorter than contact enhancement cap 604-2 _604-2 . Height H _604-1 Is increased from contactThe bottom end of the contact enhancement cap 604b of the strong cap layer 604-1 (which may be in contact with the top surface TS of the isolation structures 202) ₂₀₂ Flush) measured to contact the top end of the enhanced top cap 604b. Also, height H _604-2 From the bottom end of the contact enhancing cap 604b of the contact enhancing cap layer 604-2 (which may be in contact with the top surface TS of the isolation structures 202) ₂₀₂ Flush) measured to contact the top end of the enhanced top cap 604b. Since the contact enhancing cap layer 604-1 is lower than the contact enhancing cap layer 604-2, the top corners of the contact enhancing cap layers 604-1, 604-2 may be more vertically spaced apart, and thus, the contact enhancing cap layers 604-1, 604-2 may be prevented from merging when the width of the trench TR between adjacent active regions AA is substantially reduced. Thus, interference between memory cells 100 formed on adjacent active regions AA can be avoided.

In the preparation of the structure shown in fig. 6, the step of forming SAM 206 (as described with reference to fig. 4J and 5J) may be omitted. In addition, after the active area AA1 recess and the mask layer 306 is removed (as described with reference to fig. 4H-4I and fig. 5H-5I), a contact enhancing cap layer 604 is formed over the active area AA, for example, by an epitaxial process. In addition, a capacitor contact CC may be formed on the active area AA.

As described above, the active region of a memory cell in a memory array has an additional portion (i.e., contact enhancement cap) at its top corner. By having these additional portions more, the active region can provide a larger landing area for capacitor contacts standing on the active region. Thus, the electrical contact between the capacitor contact and the active region may be less affected by process variations in the placement of the capacitor contact. In other words, the electrical contact between the capacitor contact and the active region can be improved. In addition, adjacent active regions are designed to have different heights, and the top surface of one active region may be recessed relative to the top surface of an adjacent active region. Thus, additional portions of adjacent active regions may be more spaced apart in the vertical direction. Therefore, adjacent active regions can be prevented from merging together, and thus, interference between memory cells formed on the adjacent active regions is avoided.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those of skill in the art will appreciate from the disclosure that a process, machine, manufacture, composition of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of the present disclosure.

Claims

1. A method of fabricating a memory array, comprising:

forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated active regions formed by a surface region of the semiconductor substrate;

filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the plurality of active regions;

recessing a first set of active regions of the plurality of active regions from a top surface while covering a top surface of a second set of active regions of the plurality of active regions; and

a plurality of contact enhancement sidewall spacers and a plurality of contact enhancement caps are integrally formed, the plurality of contact enhancement sidewall spacers laterally surrounding the tops of the plurality of active regions, the plurality of contact enhancement caps covering the upper surfaces of the plurality of active regions.

2. The method of claim 1, wherein the forming of the trench comprises:

forming at least one insulating layer on the front surface of the semiconductor substrate;

forming a plurality of mask patterns on the at least one insulating layer;

performing an etching process on the at least one insulating layer and the semiconductor substrate by using the plurality of mask patterns as a shadow mask to form the trench; and

the plurality of mask patterns and the at least one insulating layer are removed.

3. The method of claim 2, wherein the at least one insulating layer comprises a first insulating layer and a second insulating layer stacked on the first insulating layer.

4. The method of claim 1, wherein the forming of the isolation structure comprises:

providing an insulating material in the trench; and

the insulating material is recessed such that the insulating material is recessed relative to the top surface of the active region and the isolation structure is formed.

5. The method of claim 1, wherein the second set of active regions is covered by a plurality of masking layers and the first set of active regions is recessed and the plurality of masking layers are removed prior to forming a plurality of contact enhancing sidewall spacers.

6. The method of manufacturing a memory array of claim 1, further comprising:

a plurality of self-assembled monolayers are formed on the top surfaces of the plurality of active regions prior to forming the plurality of contact enhancement caps.

7. The method of claim 6, wherein sidewalls of tops of the plurality of active regions remain uncovered by the plurality of self-assembled monolayers prior to forming the plurality of contact enhancement caps.

8. The method of claim 6, wherein the method of fabricating the plurality of contact enhancement caps comprises an epitaxial process.

9. The method of claim 1, wherein the plurality of contact enhancement caps and the plurality of contact enhancement sidewall spacers cover tops of the plurality of active regions.