TWI825556B - Memory array structure with contact enhancement sidewall spacers - Google Patents

Abstract

The present disclosure provides a dynamic random access memory (DRAM) array structure with contact enhancement sidewall spacers and a method for preparing the same. The memory array structure includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

Description

Memory array structure with contact-enhanced sidewall spacers

This application claims the priority and benefits of U.S. Patent Application Nos. 17/528,490 and 17/528,799 (the priority date is "November 17, 2021"). The contents of these U.S. applications are cited in their entirety. method is incorporated into this article.

The present disclosure provides a memory array structure and a manufacturing method thereof, particularly a dynamic random access memory (DRAM) array with contact-enhanced sidewall spacers and a manufacturing method thereof.

As electronics have continued to improve in recent decades, the need for storage capacity has increased. In order to increase the storage capacity of a memory device (eg, a DRAM device), more memory cells are arranged in the memory device, and the size of each memory cell in the memory device becomes smaller. These memory cells are respectively fabricated on an active area, which may be part of the semiconductor substrate. Active area scaling is an option to reduce the size of each memory cell.

Each DRAM cell may include a storage capacitor disposed on the active area and connected to the active area through capacitive contacts. A reduction in active area may result in a reduction in the landing area for capacitor contact. Therefore, due to the problem of lithography overlay in the semiconductor lithography process The problem is that the contact resistance between the capacitor contacts and the active area may increase. In other words, pursuing high storage density by minimizing the active area may compromise the performance of DRAM devices. There is a need in the art for a method of increasing the landing area of capacitor contacts without expanding the layout pattern of the active area.

The above description of "prior art" is merely to provide background technology, and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure. It does not set up the prior art of the present disclosure, and any description of the above "prior art" They should not be used as any part of this case.

In an embodiment of the present disclosure, a memory array structure is provided, including: a semiconductor substrate, a trench defining an active region laterally separated by a surface area of the semiconductor substrate, wherein a first portion of the active region a top surface of one set of active regions is recessed relative to a top surface of a second set of active regions; an isolation structure filled in the trench and in lateral contact with a bottom portion of the active region; and a contact enhancement sidewall gap sub, respectively, laterally surrounding a top of the active area.

In an embodiment of the present disclosure, a memory array structure is provided, including: an active area formed by a laterally separated surface portion of a semiconductor substrate, wherein a top surface of a first group of active areas is relative to A top surface of a second group of active areas is recessed; an isolation structure extends between the active areas and is in contact with a bottom portion of the active area; and a contact enhancement cover layer covers a portion of the active area respectively. top.

In yet another embodiment of the present disclosure, a method for manufacturing a memory array is provided, including: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines an active area laterally separated by a surface area of the semiconductor substrate. area; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active area; placing a first group The active area is recessed from a top surface of the first group of active areas and covers a top surface of a second group of active areas; and a contact-enhancing sidewall spacer is formed to laterally surround a top of the active area.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that set the patentable scope of the present disclosure are described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent scope.

10: Memory array structure

100:Memory cell

200:Semiconductor substrate

202:Isolation structure

204: Contact enhanced sidewall spacer

204-1: Contact enhanced sidewall spacer

204-2: Contact enhanced sidewall spacers

206:Self-assembled monolayer (SAM)

206-1: Self-assembled single layer

206-2: Self-assembled single layer

300: First insulation layer

302: Second insulation layer

304:Mask layer

304a: Striped pattern

304b: Island pattern

306:Mask layer

604: Contact enhancement cover

604-1: Contact Enhanced Cover

604-2: Contact Enhanced Capping

604a: Contact enhancement layer

604b: Contact enhanced sidewall spacer

AA: active area

AA': initial active area

A-A':line

AA1: Active area

AA2: Active area

AT: access transistor

B-B': line

BL: bit line

CC: capacitor contact

CC1: Capacitor contact

CC2: Capacitor contact

D1: direction

D2: Direction

H1: height

H2: height

H202:Height

H204-1:Height

H204-2:Height

H604-1:Height

H604-2:Height

S11: Steps

S13: Steps

S15: Steps

S17: Steps

S19: Steps

S21: Steps

S23: Steps

S25: Steps

S27: Steps

S29: Steps

S31: Steps

S33: Steps

SC: storage capacitor

SW1: side wall

SW2: Side wall

TR: trench

TR': initial trench

TS1: Top surface

TS2: Top surface

TS202:Top surface

WL: word line

The disclosure content of the present disclosure can be more fully understood by referring to the embodiments and the disclosed patent scope together with the drawings. The same element numbers in the drawings refer to the same elements.

FIG. 1A is a circuit diagram illustrating memory cells in a memory array structure according to some embodiments of the present disclosure.

FIG. 1B is a structural diagram illustrating a memory array structure including a plurality of memory cells according to some embodiments of the present disclosure.

FIG. 2A is a plan view illustrating a partial layout of a memory array according to some embodiments of the present disclosure.

2B is a cross-sectional view illustrating an edge portion of two adjacent active areas and a portion of an isolation structure extending between the adjacent active areas according to some embodiments of the present disclosure.

FIG. 3 is a flow chart illustrating a method of manufacturing the structure shown in FIG. 2B according to some embodiments of the present disclosure.

4A to 4K are plan views illustrating structures at an intermediate stage of the manufacturing method shown in FIG. 3 according to some embodiments of the present disclosure.

5A to 5K are cross-sectional views illustrating structures at an intermediate stage of the manufacturing method shown in FIG. 3 according to some embodiments of the present disclosure.

6 is a cross-sectional view illustrating an edge portion of two adjacent active regions and a portion of an isolation structure extending between the adjacent active regions in some other embodiments of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, device dimensions are not limited to the disclosed ranges or values, but may depend on process conditions and/or desired properties of the device. In addition, in the following description, forming the first feature "over" or "on" the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which the first feature and the second feature are formed in direct contact. Embodiments may be made in which additional features may be formed between features and second features such that the first feature and the second feature may not be in direct contact. For the sake of simplicity and clarity, some features may be drawn arbitrarily at different scales. In the figures, some layers/features may be omitted for simplicity.

In addition, for ease of explanation, "beneath", "below", "lower", "above", "upper", etc. may be used herein. Spatially relative terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The elements may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be Literal translation is performed accordingly.

FIG. 1A is a circuit diagram illustrating a memory cell 100 in a memory array structure according to some embodiments of the present disclosure. Referring to FIG. 1A , the memory array structure may be a dynamic random access memory (DRAM) array structure. Each memory cell 100 in the memory array structure may include an access transistor AT and a storage capacitor SC. The access transistor AT may be a field effect transistor (FET). One end of the storage capacitor SC is coupled to the source/or drain terminal of the access transistor AT, while the other end of the storage capacitor SC may be coupled to a reference voltage (e.g., the ground voltage described in Figure 1A) coupled. When the access transistor AT is turned on, the storage capacitor SC can be accessed. On the other hand, when the access transistor AT is in the off state, the storage capacitor SC cannot be accessed.

During a write operation, access transistor AT is turned on by establishing word line WL coupled to a gate terminal of access transistor AT, and applying force to bit line BL (together with access transistor The voltage on one source/or drain terminal of AT can be transferred to a storage capacitor SC (coupled to the other source/or drain terminal of access transistor AT). Therefore, the storage capacitor SC can be charged or discharged, and the logic state "1" or the logic state "0" can be stored in the storage capacitor SC. During a read operation, the access transistor AT is also turned on, and the pre-charged bit line BL can be pulled high or low depending on the charge state of the storage capacitor SC. By comparing the voltage of the bit line BL and the precharge voltage, the charge state of the storage capacitor SC can be sensed, and the logic state of the memory cell 100 can be identified.

FIG. 1B is a structural diagram illustrating a memory array structure 10 including a plurality of memory cells 100 according to some embodiments of the present disclosure. Referring to FIG. 1B , the memory array structure 10 has rows and columns. The memory cells 100 in each column may be arranged along a first direction, and the memory cells 100 in each row The memory cells 100 may be arranged along a second direction intersecting the first direction. A plurality of bit lines BL may be coupled to one column of the memory cell 100 respectively. On the other hand, a plurality of word lines WL may be coupled to one row of the memory cells 100 respectively. In some embodiments, during a write operation, the word line WL coupled to the selected memory cell 100 is established, and the selected memory cell is configured by providing a voltage to the bit line coupled to the selected memory cell 100 . The storage capacitor SC in 100 is programmed. In addition, during the read operation, all the bit lines BL are precharged, and the word line WL coupled to the selected memory cell 100 is established, and then the storage capacitors coupled to the established word line WL are respectively SC to pull high or low the precharged bit line BL. By detecting the voltage change of the bit line BL coupled to the selected memory cell 100, the logic state of the selected memory cell 100 can be identified. As a result of pulling the precharge bit line BL high/low, the stored charge in the storage capacitor SC of the memory cell 100 coupled to the established word line WL is changed. In order to restore the logic state of these memory cells 100, a write operation can be performed after the read operation to program the previous logic state into these memory cells 100. This write operation can also be called a refresh operation.

FIG. 2A is a plan view illustrating a partial layout of a memory array structure 10 according to some embodiments of the present disclosure.

Referring to FIGS. 1B and 2A , the memory array structure 10 may be built on a semiconductor substrate 200 . The semiconductor substrate 200 may be, for example, a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. The semiconductor substrate 200 has surface portions laterally separated from each other, called active areas AA. The isolation structure 202 extending in the semiconductor substrate 200 may laterally surround each active area AA to physically and electrically isolate the active areas AA from each other. In other words, active area AA is defined by isolation structure 202 .

According to some embodiments, active area AA may be arranged to have multiple rows and columns array. Word lines WL may be formed in the semiconductor substrate 200, and each word line laterally penetrates one row of the active area AA. On the other hand, the bit lines BL may be formed on the semiconductor substrate 200 and each intersect one column of the active areas AA.

The access transistor AT in each memory cell 100 of the memory array structure 10 is defined near the intersection of the active area AA, the penetrating word line WL and the intersecting bit line BL. The word line WL serves as the gate terminal of the access transistor AT, and the portions of the active area AA located on opposite sides of the word line WL can serve as the source/drain terminal of the access transistor AT. Bit line BL is coupled to one of the source/drain terminals. Additionally, the other source/drain terminal may be coupled with one of the storage capacitors SC formed over the semiconductor substrate 200 . It should be understood that depicting storage capacitor SC as a separate pattern represents the separate bottom electrode of storage capacitor SC. Although not shown, the storage capacitors SC may actually have a common top electrode.

In some embodiments, the word line WL extends along a first direction. In addition, the bit line BL may extend along a second direction that is substantially perpendicular to the first direction. Optionally, each bit line BL may form a curve along its extending direction (eg, the second direction). Furthermore, the active areas AA may each extend along a third direction intersecting the first direction and the second direction.

In some embodiments, each active area AA is shared by two access transistors AT having a common source/or drain terminal. In these embodiments, each active area AA is penetrated by two word lines WL and intersects one of the bit lines BL. Furthermore, each active area AA can overlap with two storage capacitors SC. The bit line BL overlaps and is electrically connected to a part of the active area AA spanning between the two word lines WL. This part of the active area AA can be used as the common source of the two access transistors AT. /or draw extreme points. Located on two word lines WL phase Other parts of the active area AA on both sides can be used as separate source/drain terminals of the two access transistors AT, and can be overlapped and electrically connected to the two covered storage capacitors SC respectively.

FIG. 2B is a cross-sectional view illustrating the edge portions of two adjacent active areas AA and a portion of the isolation structure 202 extending between the adjacent active areas AA according to some embodiments of the present disclosure.

Referring to FIG. 2B , an isolation structure 202 is formed in a trench TR of the semiconductor substrate 200 that extends from a top surface of the semiconductor substrate 200 into the semiconductor substrate 200 and laterally separates the active area AA. Furthermore, some active areas AA may be recessed relative to other active areas AA, and the top surface of the semiconductor substrate 200 in some areas of those recessed active areas AA may be lower than in other areas of non-recessed active areas AA. . As illustrated in Figure 2B, one of the active areas AA (also referred to as active area AA1) is concave relative to the adjacent active area AA (also referred to as active area AA2). Therefore, the height H1 of the active area AA1 (measured from the depth flush with the bottom end of the isolation structure 202 to the top surface TS1 of the active area AA1 ) is smaller than the height H2 of the active area AA2 (measured from the depth flush with the bottom end of the isolation structure 202 The depth is measured to the top surface TS2) of the active area AA2.

Since the active areas AA1, AA2 have different heights, the trench TR extending between the active areas AA1, AA2 may have an asymmetric shape. As illustrated in FIG. 2B , where the active area AA1 is concave relative to the active area AA2 , the sidewall SW1 of the trench TR defining the boundary of the active area AA1 may be lower than the sidewall SW2 of the trench TR defining the boundary of the active area AA2 . The heights of side walls SW1 and SW2 are substantially equal to the heights of H1 and H2 respectively. To avoid redundancy, the ratios and ranges of heights H1 and H2 are not repeated.

According to some embodiments, the top surface TS ₂₀₂ of the isolation structure 202 filled in the trench TR is lower than the top surface TS1 of the active area AA1 and lower than the top surface TS2 of the active area AA2. In these embodiments, the height H ₂₀₂ of the isolation structure 202 (measured from the bottom end of the isolation structure 202 to the top surface TS ₂₀₂ of the isolation structure 202 ) is less than the height H1 of the active area AA1 and less than the height H2 of the active area AA2 . Since the isolation structure 202 will not fill the trench TR, the tops of the sidewalls SW1 and SW2 of the trench TR will not be covered by the isolation structure 202 . Since sidewall SW2 is taller than sidewall SW1 , the top of sidewall SW2 spanning over isolation structure 202 may be larger (higher) than the top of sidewall SW1 spanning over isolation structure 202 .

In some embodiments, the top of each active area AA is laterally surrounded by contact enhancement sidewall spacers 204 and the remainder of each active area AA is laterally surrounded by isolation structures 202 . Contact enhancement sidewall spacers 204 are semiconductive or conductive and may serve as an additional portion of active area AA. By having such extra portions, the active area AA can provide a larger landing area for the capacitor contact CC connecting the active area AA and the upper storage capacitor SC, as shown in Figure 2A. Therefore, the tolerance of the setting tolerance of the capacitor contact CC can be increased, and good electrical contact between the capacitor contact CC and the active area AA can be ensured. For example, the contact enhancement sidewall spacers 204 include silicon fabricated using an epitaxy process.

Since the active area AA1 protrudes less than the active area AA2 relative to the isolation structure 202 , the height H 204 - 1 of the contact-enhancing sidewall spacers 204 - 1 laterally surrounding the top of the active area AA1 may be shorter than the height H _{204 - 1} laterally surrounding the top of the active area AA2 The contact enhancement sidewall spacer 204-2 has a height H _204-2 . Height _{H 204 - 1} is measured from the bottom end of contact enhancement sidewall spacer 204 - 1 , which may be flush with top surface TS ₂₀₂ of isolation structure 202 , to the top end of contact enhancement sidewall spacer 204 - 1 . Likewise, height H _{204 - 2} is measured from the bottom end of contact enhancement sidewall spacer 204 - 2 , which may be flush with top surface TS ₂₀₂ of isolation structure 202 , to the top end of contact enhancement sidewall spacer 204 - 2 . Because the contact-enhancing sidewall spacers 204-1, 204-2 extend to different heights from the top surface TS ₂₀₂ of the isolation structure 202, the top corners of the contact-enhancing sidewall spacers 204-1, 204-2 may have considerable lateral thickness. (not shown), may be further spaced vertically. Therefore, the contact enhancement sidewall spacers 204-1, 204-2 can be prevented from merging, especially when the width of the trench TR between the active areas AA1, AA2 is further reduced. Therefore, interference between memory cells 100 formed on adjacent active areas AA can be avoided.

In some embodiments, the top surface of each active area AA is covered by a self-assembly monolayer (SAM) 206. The self-assembled monolayer 206 may be selectively formed on the top surface of each active area AA and may not extend to the sidewalls of each active area AA. That is, the top of the sidewalls spanning each active area AA above the isolation structure 202 will not be covered by the SAM 206 . Accordingly, contact-enhancing sidewall spacers 204 formed after SAM 206 may be disposed on top of the sidewalls of active area AA. According to some embodiments, the contact-enhancing sidewall spacers 204 may further extend to the sidewalls of the SAM 206 . In these embodiments, the top end of the contact enhancement sidewall spacer 204 may be substantially flush with the top surface of the SAM 206 .

Since the active area AA1 is concave relative to the active area AA2, the top surface TS1 of the active area AA1 is lower than the top surface TS2 of the active area AA2. Therefore, the SAM 206 (also called SAM 206-1) covering the top surface TS1 of the active area AA1 is lower than the SAM 206 (also called SAM 206-2) covering the top surface TS2 of the active area AA2.

Self-assembled monolayers (SAMs) are a well-known technology in the art. For example, see "Reactive Monolayers in Directed Additive Manufacturing-Area Selective Atomic Layer Deposition" Rudy J. Wojtecki et al., Journal of Photopolymer Science and Technology, 2018 Volume 31 Issue 3 Pages 431-436, which is hereby incorporated by reference. Herein. In some embodiments, SAMs 206 include organic molecules. According to some embodiments, SAMs 206 include compounds having a compound selected from the group consisting of X-R1-SH, X-R1-SS-R2-Y, R1-S-R2, and combinations thereof A plurality of molecules of chemical formula, wherein R1 and R2 are independent carbon chains or carbon chains interrupted by at least one heteroatom, where H is hydrogen, where S is sulfur, and where X and Y are not substantially associated with the copper surface The chemical base of the chemical reaction. In some embodiments, at least one of R1 and R2 is a chain of n carbon atoms, where n is an integer from 1 to 30. In some embodiments, the chemical formula of SAMs 206 is SH(CH ₂ ) ₉ CH ₃ .

In some embodiments, the SAM is fabricated by self-assembled monolayers of polymerizable compounds. The thickness of the monolayer corresponds to the length of one molecule of the compound in the close-packed structure of the monolayer. The close-packed structure is assisted by functional groups of the compound that bind to the surface groups of the substrate through electrostatic interactions and/or one or more covalent bonds. The portion of the compound that binds to the surface of the substrate is referred to herein as the "head" of the compound. The rest of the compound is called the "tail". The tail extends from the head of the compound to the atmospheric interface at the top of the SAM. The tail has a non-polar peripheral end group on the atmospheric interface. Therefore, a good SAM has few defects in its close-packed structure and can display high contact angles.

The head portion of the SAM-forming compound can be selectively bound to a portion of the top surface of a substrate that includes regions of different compositions such that other portions of the top surface of the substrate have no or substantially no SAM-forming compounds disposed thereon. In this case, a patterned initial SAM can be formed in one step by immersing the substrate in a given solution of SAM-forming compounds (dissolved in an appropriate solvent). In some embodiments, the wavelength of ultraviolet radiation can be from approximately 4 nanometers (nm) to 450 nanometers. Deep ultraviolet (DUV) radiation can have wavelengths from 124 nanometers to 300 nanometers. Extreme ultraviolet (EUV) radiation can have wavelengths from about 4 nanometers to less than 124 nanometers.

In those embodiments where each active area AA is covered by a SAM 206, a capacitor contact CC disposed on the active area AA may penetrate the SAM 206 to establish electrical contact with the active area AA. Likewise, other contacts, such as bit line contacts (not shown), may also pass through SAM 206 to reach active area AA. Furthermore, in some embodiments, the capacitor contact CC extending to the lower active area AA may be longer than the capacitor contact CC extending to the upper active area AA. high. As illustrated in FIG. 2B , capacitive contact CC extending to active area AA1 (also referred to as capacitive contact CC1 ) may be higher than capacitive contact CC extending to active area AA2 (also referred to as capacitive contact CC2 ).

As mentioned above, the active area AA of the memory cell 100 in the memory array structure 10 has additional portions (ie, contact enhancement sidewall spacers 204) at its top corners. By having these extra portions, active area AA can provide a larger landing area for capacitor contact CC standing on active area AA. Therefore, the electrical contact between the capacitor contact CC and the active area AA may be less affected by process variations (eg, lithography coverage issues) in arranging the capacitor contact CC. In other words, the electrical contact between the capacitor contact CC and the active area AA can be improved. Furthermore, adjacent active areas AA are designed to have different heights, and the top surface of one active area AA may be concave relative to the top surface of the adjacent active area AA. Therefore, the additional portions of adjacent active areas AA, ie, the portions formed at the vertex corners of the active areas AA, may be further spaced apart in the vertical direction. Therefore, adjacent active areas AA can be prevented from merging together, and thus interference between memory cells 100 formed on adjacent active areas AA can be avoided.

FIG. 3 is a flow chart illustrating a method of manufacturing the structure shown in FIG. 2B according to some embodiments of the present disclosure. 4A to 4K are plan views illustrating structures at an intermediate stage of the manufacturing method shown in FIG. 3 according to some embodiments of the present disclosure. 5A to 5K are cross-sectional views illustrating structures at an intermediate stage of the manufacturing method shown in FIG. 3 according to some embodiments of the present disclosure. In particular, FIG. 5B is a cross-sectional view illustrating the structure taken along line AA' shown in FIG. 4B, and FIGS. 5C to 5K are cross-sectional views illustrating the structure taken along line BB' shown in FIGS. 4C to 4K. .

Referring to FIG. 3 , FIG. 4A and FIG. 5A , step S11 is performed, and a first insulating layer 300 , a second insulating layer 302 and a mask layer 304 are sequentially formed on the semiconductor substrate 200 . According to some embodiments, the manufacturing technology of the first insulating layer 300 is silicon oxide, and the manufacturing technology of the second insulating layer 302 is silicon oxide. The technology is silicon nitride. In these embodiments, the manufacturing technology of the first insulating layer 300 can be through a thermal oxidation process or a deposition process (for example, a chemical vapor deposition (CVD) process), and the manufacturing technology of the second insulating layer 302 can be through a deposition process. (For example, CVD process). Additionally, in some embodiments, mask layer 304 is a photoresist layer and may be coated on semiconductor substrate 200 . In another embodiment, the mask layer 304 is a hard mask layer, and its fabrication technology can be through a deposition process (such as a CVD process).

Referring to FIG. 3, FIG. 4B and FIG. 5B, step S13 is performed, and the mask layer 304 is patterned to form a stripe pattern 304a. The stripe pattern 304a may extend along the direction D1, and the direction D1 may be consistent with the direction in which each column of active areas AA shown in FIG. 2A extends. By partially removing the mask layer 304 to form the stripe pattern 304a, portions of the second insulating layer 302 between the stripes 304a may now be exposed. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method for forming the stripe pattern 304a on the mask layer 304 may include a photolithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method for forming the stripe pattern 304a on the mask layer 304 may include a photolithography process and an etching process.

Referring to FIG. 3 , FIG. 4C and FIG. 5C , step S15 is performed, and the stripe pattern 304 a is further patterned to form an array of island patterns 304 b. The island patterns 304b of each column may be arranged along the direction D1, while the island patterns 304b of each row may be arranged along the direction D2 intersecting the direction D1. The island pattern 304b will serve as a shadow mask when forming the initial trench TR' in subsequent steps. Each row of island patterns 304b is part of the same stripe pattern 304a and may be laterally spaced apart from each other along direction D1. By partially removing the stripe pattern 304a to form the island pattern 304b, portions of the second insulating layer 302 between the island patterns 304b may now be exposed. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method for forming the stripe pattern 304a into the island pattern 304b includes a photolithography process. In another embodiment, mask layer 304 is The patterning method of forming a hard mask layer to form the stripe pattern 304a into the island pattern 304b includes a photolithography process and an etching process.

As described above, in some embodiments, two patterning steps are used to form the island pattern 304b. In another embodiment, a single patterning process may be used to pattern the mask layer 304 shown in FIGS. 4A and 5A into the island pattern 304b shown in FIGS. 4C and 5C.

Referring to FIG. 3 , FIG. 4D and FIG. 5D , step S17 is performed, and an initial trench TR′ is formed in the semiconductor substrate 200 . The initial trench TR' may penetrate a portion of the first and second insulating layers 300, 302, span between the island patterns 304b, and further extend into the semiconductor substrate 200. By forming the initial trench TR', surface portions of the semiconductor substrate 200 are laterally separated from each other and are called initial active areas AA'. The top surfaces of the initial active areas AA' may be substantially coplanar with each other. According to some embodiments, an etching process is used to form the initial trench TR'. During the etching process, the island pattern 304b can be used as a shadow mask. In addition, after the etching process, the island pattern 304b can be removed, and the underlying second insulating layer 302 can be exposed.

Referring to FIG. 3 , FIG. 4E and FIG. 5E , step S19 is performed to remove the first and second insulating layers 300 and 302 . Therefore, the top surface of the initial active area AA' can be exposed. In some embodiments, the method of removing the first and second insulating layers 300, 302 includes an etching process.

Referring to FIG. 3 , FIG. 4F and FIG. 5F , step S21 is performed to form an isolation structure 202 in the initial trench TR′. In some embodiments, methods of preparing isolation structure 202 include providing an insulating material over the structure as shown in Figures 4E and 5E. The insulating material can fill the initial trench TR' and cover the top surface of the initial active area AA'. Subsequently, the portion of the insulating material spanning the top surface of the active area AA may be removed by a planarization process, such as a polishing process and an etching process, or a combination thereof. Additionally, the portion of the insulating material filled in the initial trench TR' may The top surface is recessed relative to the initial active area AA', and the remaining insulating material may form the isolation structure 202 . For example, the method of recessing the portion of the insulating material in the initial trench TR′ may include an etching process.

Referring to FIG. 3, FIG. 4G and FIG. 5G, step S23 is performed to selectively form a mask layer 306 on some initial active areas AA'. Therefore, as shown in Figure 5G, one of the adjacent initial active areas AA' is covered by the mask layer 306, while the other may remain exposed. According to some embodiments, the initial active areas AA' of each column are alternately covered along the column direction (eg, direction D1). In these embodiments, the mask layer 306 is periodically arranged along the column direction (eg, direction Dl). For example, a method of preparing the mask layer 306 may include forming a material layer spanning the entire area, and patterning the material layer through a photolithography process and an etching process to form the mask layer 306 . The mask layer 306 is made of a material with sufficient etching selectivity relative to the semiconductor substrate 200 .

Referring to FIG. 3 , FIG. 4H and FIG. 5H , step S25 is performed, and the uncovered initial active area AA′ is recessed relative to the initial active area AA′ covered by the mask layer 306 . Therefore, the initial active area AA' is selectively recessed, and forms the active area AA as described with reference to FIG. 2B. As shown in FIG. 5H , the active area AA1 is one of the recessed active areas AA, and the active area AA2 is one of the non-recessed active areas AA. Furthermore, in the recessing step, the initial trench TR′ is shaped to have a trench TR with one side wall higher than the other side wall, as shown in FIG. 2B . In some embodiments, the selective recessing method of the initial active area AA' includes an etching process. In these embodiments, the mask layer 306 and the isolation structure 202 have sufficient etch selectivity with respect to the semiconductor substrate 200 , so the mask layer 306 and the isolation structure 202 can be almost not consumed in the etching process for the semiconductor substrate 200 .

Referring to FIG. 3 , FIG. 4I and FIG. 5I , step S27 is performed to remove the mask layer 306 . With the mask layer 306 removed, the previously covered active area AA can now be exposed. For example, as shown in Figure 5I, active areas AA1 and AA2 can be exposed simultaneously in the current step. According to some facts In an embodiment, the preparation method of the mask layer 306 includes an etching process. Since the mask layer 306 has sufficient etching selectivity with respect to the isolation structure 202 and the semiconductor substrate 200 , the isolation structure 202 and the active area AA can be hardly recessed during the etching process.

Referring to Figures 3, 4J and 5J, step S29 is performed to form SAMs 206 on the top surface of the active area AA. According to some embodiments, SAMs 206 are selectively adsorbed on the top surface of active area AA, while the tops of the sidewalls of trench TR' may remain uncovered.

In some embodiments, the SAM-forming compound may be dissolved or dispersed in a solvent. The composition of the solvent is suitable for forming the SAM layer (including SAM-forming compounds). Solvents include, but are not limited to, for example, Toluene, xylene, DCM, chloroform, carbon tetrachloride, ethyl acetate, butyl acetate Butyl acetate, amyl acetate, propylene glycol monomethyl ether acetate (PGMEA), propylene glycol monomethyl ether (PGME), ethoxy ethyl propionate, anisole ), ethyl lactate, diethyl ether, dioxane, tetrahydrofuran (THF), acetonitrile, acetic acid, amyl acetate, acetic acid n-butyl acetate, γ-butyrolactone (GBL), acetone, methyl isobutyl ketone, 2-heptanone, cyclohexanone, Methanol, ethanol, ethylene glycol ether (2-ethoxyethanol), 2-butoxyethanol (2-butoxyethanol), isopropyl alcohol, n-butanol (n-butanol), N,N-dimethylformamide ( DMF), N,N-dimethylacetamide (N,N-dimethylacetamide), pyridine, and dimethylsulfoxide (DMSO). These solvents can be used alone or in combination.

In some embodiments, any suitable coating technique (eg, dip coating, spin coating) can be used to apply the solution to the top surface of the substrate and then remove the solvent, thus forming an initial SAM layer. The initial SAM layer has a top surface in contact with the atmosphere, and a selected surface with the substrate (SAM-forming compounds A surface with preferential affinity) for contact with the bottom surface. Generally, the thickness of the SAM is about 0.5 to about 20 nanometers, especially about 0.5 to about 10 nanometers, or even about 0.5 to 2 nanometers.

Referring to FIG. 3 , FIG. 4K and FIG. 5K , step S31 is performed to form the contact enhancement sidewall spacer 204 . According to some embodiments, the contact enhancement sidewall spacers 204 are fabricated through an epitaxial process. During the epitaxial process, material contacting enhanced sidewall spacers 204 may be grown from the exposed portion of active area AA, which is the top of the sidewalls of active area AA, extending between SAM 206 and isolation structure 202 . In some cases, the contact-enhancing sidewall spacers 204 may extend to the sidewalls of the SAM 206 . By forming contact-enhancing sidewall spacers 204, the top of active area AA is laterally surrounded, with additional portions, as described with reference to Figure 2A.

Referring to FIG. 3 and FIG. 2B, step S33 is performed to form a capacitor contact CC on the active area AA. Although not shown, several process steps may be performed before forming capacitor contact CC. For example, before forming the capacitor contact CC, a dielectric layer (not shown) may be formed throughout the active area AA and the isolation structure 202 . In addition, a through hole can be formed in the dielectric layer through a lithography process and an etching process to define the position of the capacitor contact CC. Subsequently, the conductive material can be filled into the through holes through a deposition process, an electroplating process, or a combination thereof, and the excess conductive material on the dielectric layer can be removed through a planarization process. The remaining portion of the conductive material in the via may form the capacitor contact CC.

So far, the structure shown in Figure 2B has been formed. Although not shown, additional process steps may be performed to form other elements of memory array structure 10 (as described with reference to FIGS. 1B and 2A ), including word lines WL, bit lines BL, and storage capacitors SC. These additional process steps may be performed during and after the process steps described with reference to Figures 3, 4A-4K, 5A-5K, and 2B.

FIG. 6 is a cross-sectional view illustrating an edge portion of two adjacent active areas AA and a portion of the isolation structure 202 extending between the adjacent active areas AA in some other embodiments of the present disclosure.

Referring to Figure 6, in some embodiments, SAMs 206 described with reference to Figure 2B are omitted. In these embodiments, the top of each active area AA is covered by a contact enhancement cap layer 604 . Contact enhancement cap layer 604 is similar in material selection and functionality to contact enhancement sidewall spacers 204 (as described with reference to Figure 2B). In other words, the contact enhancement capping layer 604 is semi-conductive or conductive and can be used as an additional portion of the active area AA for improving the electrical contact between the active area AA and the capacitor contact CC standing on the active area AA. In some embodiments, contact enhancement capping layer 604 includes a contact enhancement layer 604a on the top surface of active area AA and includes contact enhancement sidewall spacers 604b laterally surrounding the top of active area AA. Contact enhancement sidewall spacers 604b may extend from the contact enhancement layer 604a along the sidewalls of active area AA to the top surface of isolation structure 202 and provide additional landing areas for capacitor contacts CC provided on active area AA. In some embodiments, capacitor contact CC penetrates contact enhancement layer 604a to establish electrical contact with active area AA.

As mentioned above, some active areas AA (eg, active area AA1 ) project less than other active areas AA (eg, active area AA2 ) relative to isolation structure 202 . Therefore, the contact enhancement capping layer 604 covering the less protruding active area AA (referred to as contact enhancement capping layer 604 - 1 ) is lower than the contact enhancement capping layer 604 covering the more protruding active area AA (referred to as contact enhancement capping layer 604 -2). In other words, the contact enhancement layer 604a of the contact enhancement cap layer 604-1 may extend on a lower plane than the plane in which the contact enhancement layer 604a of the contact enhancement cap layer 604-2 extends. Additionally, the contact enhancement sidewall spacers 604b of the contact enhancement cap layer 604-1 may have a height H _604-1 that is shorter than the height H 604-2 of the contact enhancement sidewall spacers 604b of the contact enhancement cap layer _604-2 . Height H _{604 - 1} is measured from the bottom end of contact enhancement sidewall spacer 604 b of contact enhancement cap layer 604 - 1 (which may be flush with top surface TS ₂₀₂ of isolation structure 202 ) to the top end of contact enhancement sidewall spacer 604 b. Likewise, height H _{604 - 2} is measured from the bottom end of contact enhancement sidewall spacer 604 b of contact enhancement cap layer 604 - 2 (which may be flush with top surface TS ₂₀₂ of isolation structure 202 ) to contact enhancement sidewall spacer 604 b top. Since the contact enhancement cap layer 604-1 is lower than the contact enhancement cap layer 604-2, the top corners of the contact enhancement cap layers 604-1, 604-2 can be further spaced apart in the vertical direction. Therefore, when adjacent active areas AA When the width of the trench TR is greatly reduced, the contact enhancement cover layers 604-1 and 604-2 can be prevented from merging. Therefore, interference between memory cells 100 formed on adjacent active areas AA can be avoided.

In preparing the structure as shown in Figure 6, the step of forming the SAM 206 (as described with reference to Figures 4J and 5J) can be omitted. In addition, after the active area AA1 is recessed and the mask layer 306 is removed (as described with reference to FIGS. 4H-4I and 5H-5I ), a contact enhancement capping layer 604 is formed on the active area AA by, for example, an epitaxial process. In addition, the capacitor contact CC may be formed on the active area AA.

As mentioned above, the active region of a memory cell in a memory array structure has extra portions (i.e., contact-enhancing sidewall spacers) at its top corners. By having these extra portions, the active area can provide a larger landing area for the capacitor contacts standing on the active area. Therefore, the electrical contact between the capacitor contacts and the active region may be less affected by process variations in arranging the capacitor contacts. In other words, the electrical contact between the capacitor contacts and the active area can be improved. Furthermore, adjacent active areas are designed to have different heights, and the top surface of one active area may be concave relative to the top surface of an adjacent active area. Therefore, additional portions of adjacent active areas can be further spaced apart vertically. Therefore, adjacent active areas can be prevented from merging together, thus avoiding interference between memory cells formed on adjacent active areas.

In an embodiment of the present disclosure, a memory array structure is provided, including: a semiconductor substrate, a trench defined by a surface area of the semiconductor substrate forming a lateral separation an active area, wherein a top surface of a first group of active areas in the active area is recessed relative to a top surface of a second group of active areas; an isolation structure is filled in the trench and connected with the active area A bottom portion of the active area is laterally contacted; and a contact-enhancing sidewall spacer is laterally surrounding a top of the active region.

In an embodiment of the present disclosure, a memory array structure is provided, including: an active area formed by a laterally separated surface portion of a semiconductor substrate, wherein a top surface of a first group of active areas is relative to A top surface of a second group of active areas is recessed; an isolation structure extends between the active areas and is in contact with a bottom portion of the active area; and a contact enhancement cover layer covers a portion of the active area respectively. top.

In yet another embodiment of the present disclosure, a method for manufacturing a memory array is provided, including: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines an active area laterally separated by a surface area of the semiconductor substrate. area; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of the active area; recessing a first group of active areas from a top surface of the first group of active areas into, while covering a top surface of a second group of active regions; and forming a contact-enhancing sidewall spacer, respectively laterally surrounding a top surface of the active region.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the disclosed patent scope. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the process, machinery, manufacture, compositions of matter, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure that the methods described herein can be used in accordance with the disclosure. Corresponding embodiments refer to existing or future processes, machines, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same result. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of the present disclosure.

200:Semiconductor substrate

202:Isolation structure

204: Contact enhanced sidewall spacer

204-1: Contact enhanced sidewall spacers

204-2: Contact enhanced sidewall spacers

206:Self-assembled monolayer (SAM)

206-1: Self-assembled single layer

206-2: Self-assembled single layer

AA: active area

AA1: Active area

AA2: Active area

CC: capacitor contact

CC1: Capacitor contact

CC2: Capacitor contact

H1: height

H2: height

H202:Height

H204-1:Height

H204-2:Height

SW1: side wall

SW2: Side wall

TR: trench

TS1: Top surface

TS2: Top surface

TS202:Top surface

Claims (11)

A memory array structure includes: a semiconductor substrate, a trench defining an active region laterally separated by a surface area of the semiconductor substrate, wherein a top surface of a first group of active regions of the active region is relative to a A top surface of the second group of active areas is recessed; an isolation structure is filled in the trench and is laterally in contact with a bottom portion of the active area; and a contact enhancement sidewall spacer is laterally surrounding the active area. One top. The memory array structure of claim 1, wherein each of the first group of active areas is adjacent to one or more of the second group of active areas. The memory array structure of claim 1, wherein a second sidewall of the trench that defines a boundary of the first group of active areas is compared with a second sidewall of the trench that defines a boundary of the first group of active areas. The first side wall is shorter in height. The memory array structure of claim 1, wherein a top surface of the isolation structure is lower than the top surface of the first group of active areas and the top surface of the second group of active areas. The memory array structure of claim 1, wherein the top surface of the isolation structure is in contact with a bottom end of the contact enhancement sidewall spacer. The memory array structure of claim 1, wherein compared with a second set of contact enhancement sidewall spacers laterally surrounding the top of the first set of active regions, the number of contact enhancement sidewall spacers laterally surrounding the top of the first set of active regions is A first set of contact-enhanced sidewall spacers are shorter in height. The memory array structure of claim 1, wherein a top corner of the first group of contact-enhancing sidewall spacers laterally surrounding the top of the first group of active regions is along a lateral direction and a vertical direction and laterally surrounding the first group of contact-enhanced sidewall spacers. A vertex corner of the second set of contact-enhanced sidewall spacers on the top of the second set of active regions is spaced apart. The memory array structure as claimed in claim 1 further includes: a self-assembly monolayer (SAMs) covering the top surface of the active area. The memory array structure of claim 8, wherein the contact-enhancing sidewall spacer further covers one side wall of the SAM. The memory array structure of claim 8, wherein the height of a first group of SAMs covering the top of the first group of active areas is lower than the height of a second group of SAMs covering the top of the second group of active areas. high. The memory array structure of claim 1, wherein the contact-enhancing sidewall spacers are semiconductive or conductive.