CN117335361B

CN117335361B - Overvoltage detection circuit, protection circuit and control method

Info

Publication number: CN117335361B
Application number: CN202311326937.3A
Authority: CN
Inventors: 李明远; 郝春华
Original assignee: Qingdao Hantai Intelligent Technology Co ltd
Current assignee: Qingdao Hantai Intelligent Technology Co ltd
Priority date: 2023-10-13
Filing date: 2023-10-13
Publication date: 2024-05-10
Anticipated expiration: 2043-10-13
Also published as: CN117335361A

Abstract

The invention discloses an overvoltage detection circuit, a protection circuit and a control method, wherein the overvoltage detection circuit comprises: the voltage sampling assembly, the voltage peak value setting circuit, the first logic driving circuit and the second logic driving circuit; wherein, the voltage sampling assembly includes: diode CR1 and diode CR2, and load the sampling signal of a sampling point W of the output end of the drive protection circuit between said diode CR1 and diode CR 2; the voltage sampling assembly samples positive and negative voltages of a sampling point W, and transmits the result to the FPGA, the FPGA receives an overvoltage result detected by the overvoltage monitoring circuit and then sends a set logic control signal to the drive protection circuit through an output control end FPGA OUT, and the FPGA controls the drive protection circuit to protect the whole follow-up circuit by sending a high-level drive signal.

Description

Overvoltage detection circuit, protection circuit and control method

Technical Field

The invention relates to the technical field of measurement, in particular to an overvoltage detection circuit, a protection circuit and a control method.

Background

The sampling precision and the withstand voltage of the direct current sampling of the oscilloscope are contrary, because a certain withstand voltage is required to ensure the normal operation of the oscilloscope, the withstand voltage value of the oscilloscope is correspondingly reduced under the requirement of improving the precision of the oscilloscope, the sampling channel is required to be subjected to overvoltage protection, and a corresponding overvoltage detection circuit is introduced based on the requirements of the sampling precision of the oscilloscope and the withstand voltage of the sampling channel;

The more accurate the detection value of the overvoltage detection circuit is, the smaller the damage degree of the subsequent circuit is, however, the technical scheme of the overvoltage detection circuit adopted at present is divided into two cases, wherein the first case can directly introduce additional interference to a sampling channel and reduce the overvoltage detection precision, and the second case can reduce the interference of an external introduced signal, but the interference signal is higher, the influence on the circuit is larger, and the overvoltage detection precision applied to an electronic instrument is too high;

The prior art can not meet the demands of people at present, and based on the present situation, the prior art needs to be improved.

Disclosure of Invention

The invention aims to provide an overvoltage detection circuit, a protection circuit and a control method, so as to solve the problems in the background technology.

The invention provides a protection circuit which comprises a driving protection circuit, an overvoltage detection circuit, an operational amplifier circuit, an overvoltage detection circuit, an ADC (analog-to-digital converter) and an FPGA (programmable logic processor);

The input end of the drive protection circuit is provided with HIGH DCV IN ports, and the output end of the drive protection circuit is divided into two paths of outputs, wherein one path of output of the drive protection circuit is loaded to the forward input end of the operational amplifier circuit, the output end of the operational amplifier circuit is coupled to the ADC, and the output end of the ADC is loaded to the FPGA; the other output of the drive protection circuit is loaded to the overvoltage detection circuit, and the output end of the overvoltage detection circuit is loaded to the FPGA; in the embodiment, a detection signal is input from a HIGH DCV IN port, enters an operational amplifier circuit for processing after passing through a drive protection circuit and is transmitted to an ADC, the ADC converts the detection signal of an analog quantity into a digital signal and then transmits the digital signal to an FPGA for processing, the detection of the input detection signal is completed, and in the detection process, if positive voltage or negative voltage reaches a voltage peak value, overvoltage is detected by an overvoltage detection circuit and then is output to the FPGA for processing;

The overvoltage detection circuit includes: the voltage sampling assembly, the voltage peak value setting circuit, the first logic driving circuit and the second logic driving circuit; wherein,

The voltage sampling assembly includes: diode CR1 and diode CR2, and load the sampling signal of a sampling point W of the output end of the drive protection circuit between said diode CR1 and diode CR 2; the diode CR1 and the diode CR2 are connected in anti-parallel according to the flow direction of the sampling signal; the voltage sampling component samples positive and negative voltages of a sampling point W, and outputs the positive voltage through a diode CR2 when the sampling signal is positive voltage, and outputs the negative voltage through a diode CR1 when the sampling signal is negative voltage;

The voltage peak setting circuit includes: a zener diode D1, a zener diode D2, and a capacitor C2; the output ends of the diodes CR1 and CR2 which are reversely connected in parallel are connected with a capacitor C2 in series, the positive and negative ends of the capacitor C2 are also connected with a group of voltage stabilizing diodes D1 and D2 which are reversely connected in series in parallel, and the voltage peak value setting circuit is used for setting a voltage peak value detected by overvoltage;

The first logic driving circuit includes: transistor Q1A, transistor Q1B and transistor Q2A; the output end of the voltage peak value setting circuit is divided into three paths of signal output, wherein the first path of output end is loaded to the base electrode of the triode Q1A, the second path of output end is loaded to the collector electrode of the triode Q1B, the third path of output end is loaded to the emitter electrode of the triode Q2A, the common base electrode of the triode Q1A and the triode Q1B is connected to the emitter electrode of the triode Q2A, and the common collector electrode of the triode Q1A and the triode Q2A is connected to the base electrode of the triode Q2B;

The second logic driving circuit consists of a triode Q2B, a pull-up resistor R2 and a pull-up resistor R3; the base electrode of the triode Q2B is loaded with a 3.3v power supply through a pull-up resistor R2, the collector electrode of the triode Q2B is also loaded with the 3.3v power supply through a pull-up resistor R3, and the output end of the collector electrode of the triode Q2B outputs signals FPGA IN to FPGA.

The invention also provides a control method comprising the protection circuit, wherein the control method is used for controlling the protection circuit, particularly controlling an overvoltage protection circuit, and realizing the overvoltage protection of a later-stage circuit (a driving protection circuit, an operational amplifier circuit, a subsequent ADC and an FPGA), and comprises the following steps:

Step S10: the detection signal is input from a HIGH DCV IN port, when the voltage of the detection signal does not reach an overvoltage peak value, a low-level driving signal is given to the first-stage driving protection circuit and the second-stage driving protection circuit through the FPGA, the first photoelectric coupler U2A and the second photoelectric coupler U2B are controlled to trigger the grid electrode and the source electrode of the first MOS tube Q101, the second MOS tube Q102, the third MOS tube Q103 and the fourth MOS tube Q104 respectively, and a driving signal is generated to enable the whole voltage channel to be conducted.

Step S20: when the voltage of the detection signal reaches an overvoltage peak value, detecting the voltage at a sampling point W at the output end of the drive protection circuit through an overvoltage monitoring circuit, and transmitting the detection result to the FPGA through an FPGA IN at the output end of the overvoltage monitoring circuit;

Step S30: after receiving an overvoltage result detected by the overvoltage monitoring circuit, the FPGA sends a set logic control signal to the drive protection circuit through an output control end FPGA OUT, and the FPGA controls the drive protection circuit to protect the whole subsequent circuit by sending a high-level drive signal;

the invention has the following beneficial effects:

The overvoltage monitoring circuit has the characteristics of high resistance and low noise, and for the signal of the detection channel, when the signal does not reach the overvoltage value, the overvoltage monitoring circuit is not triggered to form a parallel path with infinite impedance to the ground, so that the influence on the signal on the detection channel can be greatly reduced, and the influence on the signal detection result is only 2ppm through relevant tests, and can be regarded as almost no influence; when the signal reaches the overvoltage value, the overvoltage monitoring circuit starts to act, and the FPGA can disconnect the drive protection circuit, so that the ADC does not continuously collect the signal, and the overvoltage protection of the rear-stage circuit is realized under the condition of ensuring that the influence on the detection signal is extremely small.

Drawings

FIG. 1 is a schematic circuit diagram of an overvoltage detection circuit according to the present invention;

FIG. 2 is a schematic diagram of the overall protection circuit of the present invention;

FIG. 3 is a graph showing the linearity trend of the input voltage of 0.1V to 10V at 21 measurement points;

FIG. 4 is a graph showing the linearity trend of the input voltage values of-0.1V to-10V according to the present invention, wherein 21 measurement points are taken.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the present invention without making any inventive effort fall within the scope of the present invention.

In the embodiment, the device on the sampling channel needs to set channel impedance on the sampling channel to prevent current surge due to the self characteristic, and when a common detection circuit such as a resistor voltage dividing circuit is connected in parallel, a ground resistor is introduced, so that a relatively large deviation is generated on a detection signal, and the sampling precision is affected; the addition of the additional circuit can introduce new noise and also can have adverse effect on the sampling precision;

Referring to fig. 2, therefore, in a first aspect, the present invention provides a protection circuit comprising a drive protection circuit, an operational amplifier circuit, an overvoltage detection circuit, an ADC (analog-to-digital converter) and an FPGA (programmable logic processor);

Referring to fig. 1, in a second aspect, in order to prevent an overvoltage phenomenon from damaging subsequent circuit elements in a signal output from an output terminal of a driving protection circuit, the present invention introduces an overvoltage detection circuit for detecting a positive voltage and a negative voltage of the signal, and outputting a detection result to an FPGA for corresponding processing, where the overvoltage detection circuit includes: the voltage sampling assembly, the voltage peak value setting circuit, the first logic driving circuit and the second logic driving circuit; wherein,

The voltage sampling assembly includes: diode CR1 and diode CR2, and load the sampling signal of a sampling point W driving the output end of the protective circuit between said diode CR1 and diode CR 2; the diode CR1 and the diode CR2 are connected in anti-parallel according to the flow direction of the sampling signal, in this embodiment, the diode CR1 and the diode CR2 are connected in series in the same direction in terms of a simple slave circuit, but in this embodiment, by sampling the positive and negative voltages of the sampling point at the output end of the driving protection circuit, when the sampling signal is the forward voltage, the positive and negative voltages are output through the diode CR2, when the sampling signal is the reverse voltage, the negative voltages are output through the diode CR1, and by reversely connecting the diode CR1 and the diode CR2 in parallel according to the flow direction of the sampling signal, the backflow of the positive and negative sampling signals can be prevented by using the voltage drop of the diode CR1 and the diode CR2, and when the sampling signal is sampled, the sampling signal input to the overvoltage detection circuit generates the voltage drop of the pipe regardless of the forward voltage or the reverse voltage, and the backflow of the sampling signal to the sampling point is prevented by the reverse bias;

The output ends of the diode CR1 and the diode CR2 which are reversely connected in parallel are coupled with the capacitor C2 in series, and the positive and negative ends of the capacitor C2 are also connected with a group of voltage stabilizing diodes D1 and D2 which are reversely connected in series, in this embodiment, the voltage stabilizing diode D1 and the voltage stabilizing diode D2 are reversely connected in series, and then the capacitor C2 is connected in parallel, so that the voltage stabilizing diode D1, the voltage stabilizing diode D2 and the capacitor C2 together form a voltage peak value setting circuit, which can set a voltage peak value detected by overvoltage, wherein, the forward voltage peak value=the voltage stabilizing value of the voltage stabilizing diode D1+the conduction voltage drop of the voltage stabilizing diode D2+the conduction voltage drop of the diode CR 1; negative voltage peak = regulated value of zener diode D2 + on-drop of zener diode D1 + on-drop of diode CR 2;

The output end of the voltage peak value setting circuit is divided into three paths of signal output, wherein the first path of output end is loaded to the base electrode of the triode Q1A, the second path of output end is loaded to the collector electrode of the triode Q1B, the third path of output end is loaded to the emitting electrode of the triode Q2A, the common base electrode of the triode Q1A and the triode Q1B is connected to the emitting electrode of the triode Q2A, the common collector electrode of the triode Q1A and the triode Q2A is connected to the base electrode of the triode Q2B, and the triode Q1A, the triode Q1B and the triode Q2A form a first logic driving circuit.

In this embodiment, the first logic driving circuit performs logic conversion when the negative voltage reaches a peak value through the transistor Q2A, when the voltage peak value reaches a negative overvoltage peak value, the zener diode D1 is broken down, the emitter of the transistor Q2A is pulled down Cheng Fudian to be flat, the base of the transistor Q2A is grounded, and these two voltages act on the transistor Q2A to generate a current flowing into the base of the transistor Q1A, so as to turn on the transistor Q1A, and make the collector of the transistor Q2A generate a negative level, so that the transistor Q2B that is originally driven to be turned off by the 3.3V pull-up resistor R2.

In this embodiment, the first logic driving circuit controls when the positive voltage reaches a peak value through the transistor Q1B and the transistor Q1A, when the voltage peak value reaches a positive overvoltage peak value, the zener diode D2 is broken down, the collector of the transistor Q1B is pulled up to a high level, the base of the transistor Q1B is also at a high level, since the emitter of the transistor Q1B is grounded and the base of the transistor Q1B generates a current flowing into the base of the transistor Q1B, the transistor Q1B is turned on and grounded, and the collector of the transistor Q1B and the high level of the base of the transistor Q1B are pulled down, so that the voltage difference between the base and the emitter of the transistor Q1B is reduced, and in this case, the base current of the transistor Q1B is operated in a weak conduction state (amplification state), and the base current and collector current of the transistor Q1B are positively correlated; the transistor Q1A at this time has the same structure and parameters as the transistor Q1B, and can be deduced according to the terylen theorem according to the two-part circuit topology being completely consistent: the collector current of the triode Q1A is consistent with the collector current of the triode Q1B, and the emitting electrode of the triode Q2A at the moment keeps high level, so that the triode Q2A cannot be conducted, the current of the triode Q1A is generated from a power supply where the pull-up resistor R2 is located, so that the base current of the triode Q2B which is originally generated through the pull-up resistor R2 is reduced after being split, and the triode Q2B is further turned off.

IN this embodiment, the base of the triode Q2B is loaded with a 3.3V power supply through a pull-up resistor R2, the collector of the triode Q2B is also loaded with a 3.3V power supply through a pull-up resistor R3, the output end of the collector of the triode Q2B outputs a signal FPGA IN, the triode Q2B, the pull-up resistor R2 and the pull-up resistor R3 form a second logic driving circuit, IN this embodiment, 3.3V generates a base driving current through the pull-up resistor R2, pulls down the output signal FPGA IN to ground after the triode Q2B is turned on, outputs a low level, and pulls up to a high level after the positive and negative voltages reach a defined peak value; when IN negative overvoltage, as the base electrode of the triode Q2B is pulled to negative voltage and then the triode Q2B is changed from normal on to off, the FPGA IN signal which is originally IN a low level is pulled up to a high level by 3.3V through the pull-up resistor R3; when the voltage is over-voltage, the base current of the triode Q2B generated by the pull-up resistor R2 is reduced after being shunted, so that the triode Q2B is turned off, and the FPGA IN signal which is originally IN a low level is pulled up to a high level by 3.3V through the pull-up resistor R3.

Referring to fig. 2, the driving protection circuit includes: a first MOS (gate turn-off transistor) transistor Q101, a second MOS transistor Q102, a third MOS transistor Q103, a fourth MOS transistor Q104, a zener diode D3, a zener diode D4, a first photo-coupler U2A and a second photo-coupler U2B; the first MOS tube Q101, the second MOS tube Q102, the voltage-stabilizing diode D3 and the first photoelectric coupler U2A form a first-stage driving protection circuit, the third MOS tube Q103, the fourth MOS tube Q104, the voltage-stabilizing diode D4 and the second photoelectric coupler U2B form a second-stage driving protection circuit, the first MOS tube Q101, the second MOS tube Q102, the third MOS tube Q103 and the fourth MOS tube Q104 are connected in series, and the first MOS tube Q101, the second MOS tube Q102 and the voltage-stabilizing diode D3 are connected in parallel and then coupled to the input end of the first photoelectric coupler U2A; similarly, the third MOS transistor Q103 and the fourth MOS transistor Q104 are connected in parallel with the zener diode D4 and then coupled to the input end of the second photo-coupler U2B; the first photoelectric coupler U2A and the second photoelectric coupler U2B are connected in series and then are loaded to the output end of the FPGA;

In this embodiment, the first-stage driving protection circuit and the second-stage driving protection circuit are also connected in series substantially and then loaded to the output end of the FPGA, the first-stage driving protection circuit protects the driving signals of the first MOS transistor Q101 and the second MOS transistor Q102 through the voltage stabilizing tube D3, and the second-stage driving protection circuit protects the driving signals of the second MOS transistor Q102 and the third MOS transistor Q103 through the voltage stabilizing tube D4; because the first-stage driving protection circuit and the second-stage driving protection circuit are connected in series, the 2 driving protection circuits can be controlled simultaneously through the FPGA, one driving protection circuit can be independently controlled, and when one driving protection circuit is short-circuited and cannot work, the other driving protection circuit can be controlled to work continuously by the FPGA;

In this embodiment, since the first-stage driving protection circuit and the second-stage driving protection circuit have the same working principle, taking the first-stage driving protection circuit as an example, the FPGA in the initial state gives a low-level driving signal to the first-stage driving protection circuit, and controls the first photo-coupler U2A to trigger the gate and the source of the first MOS transistor Q101 and the second MOS transistor Q102 to generate the driving signal so as to conduct, thereby conducting the whole voltage channel in the circuit; when the FPGA sets the driving signal of the first-stage driving protection circuit high, namely when the overvoltage detection circuit is triggered, the first photoelectric coupler U2A is turned off, so that the driving of the first MOS tube Q101 and the second MOS tube Q102 is stopped to enable the first MOS tube Q101 and the second MOS tube Q102 to be turned off, and a higher voltage signal is blocked to enable the higher voltage signal not to pass through the later-stage circuit, so that devices on the later-stage circuit are protected; IN the process, the overvoltage monitoring circuit is used for detecting and protecting an input voltage signal, an input voltage is prevented from being excessively high, a peak voltage is set through a voltage stabilizing diode D1 and a voltage stabilizing diode D2 of a voltage peak value setting circuit IN the overvoltage detection circuit, after an input signal to be detected reaches a voltage peak value set by the overvoltage detection circuit, an output end FPGA IN of the overvoltage monitoring circuit gives an action signal to the FPGA, a required control signal is sent to a driving protection circuit through an output control end FPGA OUT through logic set by the FPGA, and the FPGA controls the driving protection circuit to protect the whole follow-up circuit through sending the low-level driving signal or the high-level driving signal.

In the embodiment, when the signal of the detection channel does not reach the overvoltage value, the voltage stabilizing diode D1 or the voltage stabilizing diode D2 in the overvoltage monitoring circuit is disconnected, the overvoltage monitoring circuit is disconnected from the whole circuit, and the subsequent circuit (the drive protection circuit, the operational amplifier circuit and the subsequent ADC and FPGA) normally works, which is equivalent to that the overvoltage monitoring circuit is not triggered, so that a parallel path with infinite impedance to the ground is formed, the influence on the signal on the detection channel can be greatly reduced, and the influence can be regarded as almost no influence; when the signal reaches the overvoltage value, the overvoltage monitoring circuit starts to work, according to the working principles of the drive protection circuit and the overvoltage monitoring circuit, the FPGA can disconnect the drive protection circuit, so that the ADC does not continuously collect the signal, the overvoltage protection on the subsequent-stage circuit is realized under the condition of ensuring that the influence on the detection signal is extremely small, the influence on the whole circuit is very small after the overvoltage protection circuit is added, after relevant tests, the influence on the signal detection result is less than 2ppm after the overvoltage monitoring circuit is introduced, and the test result on the input voltage of 5V-10V is as follows:

input voltage reference value (V)	Measurement value (V) incorporating overvoltage protection circuit	Removing the measurement value (V) of the overvoltage protection circuit
			5	5.002655	5.002574
5.5	5.502915	5.502834
			6	6.003177	6.003087
6.5	6.503435	6.503341
			7	7.003696	7.003597
7.5	7.503959	7.503857
			8	8.004219	8.004114
8.5	8.504482	8.504372
			9	9.004752	9.004637
9.5	9.5050182	9.504902
			10	10.0052886	10.00517

In this embodiment, the input voltage value of 5V is taken as an example for explanation, and it can be seen from the above table that, when the input voltage value is 5V, the measured voltage value is 5.002574V without adding an overvoltage protection circuit, wherein the measured error value is determined by the characteristics of the circuit board and the environmental influence, and is irrelevant to the overvoltage protection circuit, and when the overvoltage protection circuit is added, the measured voltage value is 5.002655v,5.002655v-5.002574 v= 0.000081V, therefore, the influence on the original circuit is very small and is far less than 2ppm after the overvoltage protection circuit is added.

In this embodiment, the magnitude of the influence on the original circuit after the overvoltage protection circuit is added can also be judged through linearity, referring to fig. 3, a linearity trend chart of 21 measurement points is taken for the input voltage value of 0.1V to 10V, referring to fig. 4, a linearity trend chart of 21 measurement points is taken for the input voltage value of-0.1V to-10V, it can be seen that the linearity after the overvoltage protection circuit is added is similar to the linearity after the overvoltage protection circuit is not added, the interval between the linearity and the linearity is kept at a small distance all the time, and the influence on the original circuit is small after the overvoltage protection circuit is added, and is far less than 2ppm.

In a third aspect, the present invention further provides a control method according to another aspect, where the control method is used for controlling the protection circuit to implement overvoltage protection for a later stage circuit (a driving protection circuit, an operational amplifier circuit, and subsequent ADC and FPGA), and the steps include:

Step S201: when the voltage peak value at the sampling point W reaches a negative overvoltage peak value, the emitter of the triode Q2A is pulled down to be at a negative level, the base electrode of the triode Q2A is grounded, and two voltages of the emitter and the base electrode of the triode Q2A act on the triode Q2A to generate current flowing into the base electrode of the triode Q1A, so that the triode Q1A is conducted, the collector of the triode Q2A generates a negative level, and the triode Q2B which is originally driven to be conducted by the 3.3V pull-up resistor R2 is turned off;

Step S202: when the voltage peak value at the sampling point W reaches a positive overvoltage peak value, the collector and the base of the triode Q1B are pulled up to be high level, the emitter of the triode Q1B is grounded to generate current flowing into the base of the triode Q1B, the triode Q1B is grounded after being conducted, the high level of the collector and the base of the triode Q1B is pulled down, the voltage difference between the base and the emitter of the triode Q1B is reduced to reduce the base current, the collector current of the triode Q1A is kept consistent with the collector current of the triode Q1B, the current of the triode Q1A is generated from a power supply where the pull-up resistor R2 is located, the base current of the triode Q2B originally generated by the pull-up resistor R2 is reduced after being shunted, and then the triode Q2B is turned off.

Step S301: the FPGA sends logic control signals to set high driving signals of the first-stage driving protection circuit and the second-stage driving protection circuit, the first photoelectric coupler U2A and the second photoelectric coupler U2B are turned off, driving of the first MOS tube Q101, the second MOS tube Q102, the third MOS tube Q103 and the fourth MOS tube Q104 is stopped, the first MOS tube Q101, the second MOS tube Q102, the third MOS tube Q103 and the fourth MOS tube Q104 are turned off, high voltage signals are blocked, and the high voltage signals cannot pass through the later-stage circuit, so that device protection on the later-stage circuit is realized.

Although the present invention has been described with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements and changes may be made without departing from the spirit and principles of the present invention.

Claims

1. An overvoltage detection circuit, comprising: the voltage sampling assembly, the voltage peak value setting circuit, the first logic driving circuit and the second logic driving circuit; wherein,

2. The overvoltage detection circuit of claim 1, wherein: the diode CR1 and the diode CR2 are connected in anti-parallel according to the flow direction of the sampling signal, so that the sampling signal input to the overvoltage detection circuit is either forward voltage or reverse voltage, and the diode CR1 and the diode CR2 form a forward bias to generate a tube voltage drop, and the other diode CR is reverse biased to prevent the backflow of the sampling signal to the sampling point.

3. The overvoltage detection circuit of claim 1, wherein: the forward voltage peak value set by the voltage peak value=the regulated value of the zener diode D1+the conduction voltage drop of the zener diode D2+the conduction voltage drop of the diode CR 1;

Negative voltage peak value set by the voltage peak value=regulated value of the zener diode D2+conduction voltage drop of the zener diode D1+conduction voltage drop of the diode CR 2.

4. The overvoltage detection circuit of claim 1, wherein: the first logic driving circuit performs logic conversion when the negative voltage reaches a peak value through the triode Q2A control: when the voltage peak reaches a negative overvoltage peak, the zener diode D1 is broken down, the emitter of the triode Q2A is pulled down Cheng Fudian to be flat, the base of the triode Q2A is grounded, so that current flowing into the base of the triode Q1A is generated, the triode Q1A is conducted, the collector of the triode Q2A generates negative level, and the triode Q2B which is originally driven to be conducted by the 3.3V pull-up resistor R2 is turned off;

The first logic driving circuit performs logic conversion when the positive voltage reaches a peak value through the triode Q1B and the triode Q1A control: when the voltage peak reaches the positive overvoltage peak, the voltage stabilizing diode D2 is broken down, the collector of the triode Q1B is pulled up to be high level, the base of the triode Q1B is also high level, the emitter of the triode Q1B is grounded and the base of the triode Q1B generates current flowing into the base of the triode Q1B, the triode Q1B is grounded after being conducted and the high level of the collector and the base of the triode Q1B is pulled down, the collector current of the triode Q1A is kept consistent with the collector current of the triode Q1B, the emitter of the triode Q2A is kept high level, the current of the triode Q1A is generated from a power supply where the pull-up resistor R2 is located, so that the base current of the triode Q2B originally generated by the pull-up resistor R2 is reduced after being split, and then the triode Q2B is turned off.

5. The overvoltage detection circuit of claim 1, wherein: the 3.3V power supply generates base electrode driving current through a pull-up resistor R2, and an output signal FPGA IN is pulled down to the ground after a transistor Q2B is conducted; and, in addition, the method comprises the steps of,

When the negative overvoltage is carried out, after the base electrode of the triode Q2B is pulled to negative voltage, the triode Q2B is changed from normal on to off;

when the positive overvoltage is performed, the base current of the triode Q2B generated by the pull-up resistor R2 is reduced after being shunted, so that the triode Q2B is turned off.

6. A protection circuit based on an overvoltage detection circuit according to any one of claims 1-5, characterized in that: further comprises: the driving protection circuit, the operational amplifier circuit, the ADC and the FPGA;

the input end of the drive protection circuit is provided with HIGH DCV IN ports for inputting detection signals, and the output end of the drive protection circuit is divided into two paths for output; wherein,

One path of output of the drive protection circuit is loaded to the positive input end of the operational amplifier circuit, the output end of the operational amplifier circuit is coupled to the ADC, and the output end of the ADC is loaded to the FPGA;

The other output of the drive protection circuit is loaded to the overvoltage detection circuit, and the output end of the overvoltage detection circuit is loaded to the FPGA;

The detection signal is input from HIGH DCV IN ports, enters the operational amplifier circuit to be processed and then is transmitted to the ADC, the ADC converts the detection signal of the analog quantity into a digital signal and then is transmitted to the FPGA to be processed, the detection of the input detection signal is completed, and in the detection process, if positive voltage or negative voltage reaches a voltage peak value, the overvoltage is detected by the overvoltage detection circuit and then is output to the FPGA to be processed.

7. The protection circuit of claim 6, wherein: the drive protection circuit includes: the MOS transistor comprises a first MOS transistor Q101, a second MOS transistor Q102, a third MOS transistor Q103, a fourth MOS transistor Q104, a zener diode D3, a zener diode D4, a first photoelectric coupler U2A and a second photoelectric coupler U2B; wherein,

The first MOS tube Q101, the second MOS tube Q102, the zener diode D3 and the first photoelectric coupler U2A form a first-stage driving protection circuit; and, in addition, the method comprises the steps of,

The third MOS transistor Q103, the fourth MOS transistor Q104, the zener diode D4 and the second photoelectric coupler U2B form a second-stage driving protection circuit;

The first MOS tube Q101, the second MOS tube Q102, the third MOS tube Q103 and the fourth MOS tube Q104 are connected in series, and the first MOS tube Q101, the second MOS tube Q102 and the zener diode D3 are connected in parallel and then coupled to the input end of the first photoelectric coupler U2A; the third MOS transistor Q103 and the fourth MOS transistor Q104 are connected with the zener diode D4 in parallel and then coupled to the input end of the second photoelectric coupler U2B; and the first photoelectric coupler U2A and the second photoelectric coupler U2B are connected in series and then are loaded to the output end of the FPGA.

8. The protection circuit of claim 7, wherein: the first-stage driving protection circuit and the second-stage driving protection circuit are connected in series and then are loaded to the output of the FPGA; and, in addition, the method comprises the steps of,

The first-stage driving protection circuit protects driving signals of the first MOS transistor Q101 and the second MOS transistor Q102 through a voltage stabilizing tube D3;

the second-stage driving protection circuit protects driving signals of the second MOS transistor Q102 and the third MOS transistor Q103 through a voltage stabilizing tube D4;

The FPGA can simultaneously control the first-stage drive protection circuit and the second-stage drive protection circuit to work, and also can independently control one of the drive protection circuits to work, and when one of the drive protection circuits is in short circuit and can not work, the FPGA can independently control the other drive protection circuit to work continuously.

9. The protection circuit of claim 6, wherein: when the signal to be detected input by the HIGH DCV IN port is over-voltage, an output end FPGA IN of the over-voltage monitoring circuit gives an action signal to the FPGA, a logic control signal set by the FPGA is sent to the driving protection circuit through an output control end FPGA OUT, so that the first MOS tube Q101, the second MOS tube Q102, the third MOS tube Q103 and the fourth MOS tube Q104 are turned off, high-voltage signals are blocked from entering the later-stage circuit, and devices on the later-stage circuit are protected.

10. A control method based on an overvoltage detection circuit according to any one of claims 1-5 or on a protection circuit according to any one of claims 6-9, characterized in that: the method comprises the following steps:

Step S10: when the voltage of the detection signal does not reach an overvoltage peak value, a low-level driving signal is given to the first-stage driving protection circuit and the second-stage driving protection circuit through the FPGA, the first photoelectric coupler U2A and the second photoelectric coupler U2B are controlled to be respectively triggered on the grid electrode and the source electrode of the first MOS tube Q101, the second MOS tube Q102, the third MOS tube Q103 and the fourth MOS tube Q104, and driving signals are generated to enable the whole voltage channel to be conducted;

Step S202: when the voltage peak value at the sampling point W reaches a positive overvoltage peak value, the collector and the base of the triode Q1B are pulled up to be high level, the emitter of the triode Q1B is grounded to generate current flowing into the base of the triode Q1B, the triode Q1B is grounded after being conducted, the high level of the collector and the base of the triode Q1B is pulled down, the voltage difference between the base and the emitter of the triode Q1B is reduced to reduce the base current, the collector current of the triode Q1A is kept consistent with the collector current of the triode Q1B, the current of the triode Q1A is generated from a power supply where the pull-up resistor R2 is located, the base current of the triode Q2B originally generated by the pull-up resistor R2 is reduced after being shunted, and then the triode Q2B is turned off;