CN117334707A - Vertical charge transfer imaging sensor and method of manufacturing the same - Google Patents

Vertical charge transfer imaging sensor and method of manufacturing the same Download PDF

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Publication number
CN117334707A
CN117334707A CN202311406409.9A CN202311406409A CN117334707A CN 117334707 A CN117334707 A CN 117334707A CN 202311406409 A CN202311406409 A CN 202311406409A CN 117334707 A CN117334707 A CN 117334707A
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substrate
region
trench isolation
deep trench
area
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易开样
曹开玮
郑志强
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Priority to CN202311406409.9A priority Critical patent/CN117334707A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention relates to a vertical charge transfer imaging sensor and a manufacturing method thereof. In the vertical charge transfer imaging sensor, a first number of pixel areas and a second number of first public substrate areas are defined in a substrate through deep groove isolation, a second public substrate area is arranged between the deep groove isolation and the back of the substrate, the second public substrate area is communicated with each pixel area and the first public substrate area, a photosensitive area and a charge reading area are defined in each pixel area through shallow groove isolation, a grid structure is formed on the surface of each pixel area, the grid structure and the pixel areas below the grid structure form a MOS capacitor, wherein a substrate end voltage of the MOS capacitor is applied to the first public substrate area from one side of the front of the substrate, and the substrate end voltage is transmitted to the substrate of each pixel area through the first public substrate area and the second public substrate area, so that a metal electrode does not need to be formed on the back of the substrate, and the problems of high interface defect and large contact resistance when the metal electrode is formed on the back of the substrate can be avoided.

Description

Vertical charge transfer imaging sensor and method of manufacturing the same
Technical Field
The invention relates to the technical field of sensitization, in particular to a vertical charge transfer imaging sensor and a manufacturing method of the vertical charge transfer imaging sensor.
Background
A vertical charge transfer imaging sensor (Vertically charge transferring Pixel Sensors) is an image sensor that employs a substrate and floating gate transistor structure to effect imaging. Fig. 1 is a schematic plan view of a vertical charge transfer imaging sensor. FIG. 2 is a schematic cross-sectional view of the vertical charge transfer imaging sensor taken along the direction XX' in FIG. 1. Referring to fig. 1 and 2, a vertical charge transfer imaging sensor generally includes a plurality of pixels formed based on a substrate 10, each pixel including a photosensitive region 11 and a charge reading region 12 formed in the substrate 10 with a Shallow Trench Isolation (STI) interposed therebetween, and further including a gate structure formed on the photosensitive region 11 and the charge reading region 12, the gate structure including a gate dielectric layer, a floating gate FG, an inter-gate dielectric layer, and a control gate CG stacked in this order on the substrate 10, and further including a source region S and a drain region D formed on the charge reading region 12 and located on both sides of the Control Gate (CG), respectively. In the above vertical charge transfer imaging sensor, the gate structure and the photosensitive region 11 below the gate structure form a MOS capacitor, wherein the Control Gate (CG) and the substrate 10 of the photosensitive region 11 are two electrodes of the MOS capacitor, respectively, and the gate structure, the source region S and the drain region D form a read transistor. The photosensitive mechanism of the vertical charge transfer imaging sensor is: light is incident into the substrate 10 from the side of the substrate 10 away from the gate structure, collides with the substrate lattice to generate photoelectrons, and when a proper bias voltage is applied to the MOS capacitor, the photoelectrons can move towards the control gate CG and gather on the surface of the photosensitive region 11 or cross the potential barrier to enter the Floating Gate (FG), so that the drain current and/or the threshold voltage of the reading transistor are changed, and by detecting the change, the photoelectric sensing and imaging can be realized.
Compared with the traditional photodiode-based sensing device (such as a CMOS image sensor), the vertical charge transfer imaging sensor can realize higher full-well charge under the same pixel size, thereby having higher signal-to-noise ratio and obvious advantages in the aspect of pixel miniaturization.
In order to avoid crosstalk (cross) of photoelectrons between different pixels, as shown in fig. 2, currently, deep Trench Isolation (DTI) penetrating through the substrate 10 is formed to physically isolate adjacent pixels, in order to facilitate voltage application to the substrate 10 as a MOS capacitor electrode, a metal electrode 13 is embedded in a region between the pixels on the back side of the substrate 10, a part of the surface of the metal electrode 13 is in direct contact with the substrate 10, another part of the surface is spaced apart by a high dielectric constant layer 14 to cover the deep trench isolation DTI, and the high dielectric constant layer 14 is also formed on the back side of the substrate 10 around the metal electrode 13.
However, the metal electrode 13 provided on the back surface of the substrate 10 is in direct contact with the substrate 10, so that the interface defect is high and the contact resistance is large, and the process of forming the back surface structure of the substrate is complicated, which increases the manufacturing cost of the vertical charge transfer imaging sensor.
Disclosure of Invention
In order to avoid the problems of high interface defect and large contact resistance when a metal electrode is formed on the back surface of a substrate while forming effective isolation between pixels, the invention provides a vertical charge transfer imaging sensor and a manufacturing method thereof.
In one aspect, the present invention provides a vertical charge transfer imaging sensor comprising:
a substrate having a first doping type and comprising opposite front and back sides;
the deep trench isolation is formed on the front surface of the substrate, the cross section of the deep trench isolation is of a grid structure so as to define a first number of pixel areas and a second number of first common substrate areas positioned between the pixel areas in the substrate, and a second common substrate area is arranged between the lower end of the deep trench isolation and the back surface of the substrate and is communicated with each pixel area and the first common substrate area;
shallow trench isolation formed on the front surface of the substrate, wherein each pixel region comprises a photosensitive region and a charge reading region which are defined by the shallow trench isolation; and
the grid structure is formed on the surface of the pixel area, and the grid structure and the pixel area below the grid structure form a MOS capacitor, wherein the substrate terminal voltage of the MOS capacitor is applied to the first common substrate area from one side of the front surface of the substrate.
Optionally, the gate structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate stacked on the surfaces of the photosensitive region and the charge reading region, wherein the floating gate, the inter-gate dielectric layer and the control gate extend from the photosensitive region to the charge reading region; the vertical charge transfer imaging sensor further comprises a source region and a drain region which are formed in the charge reading region and are respectively positioned on two sides of the gate structure, and the gate structure, the source region and the drain region form a reading transistor.
Optionally, the vertical charge transfer imaging sensor further comprises:
an interlayer dielectric layer formed on one side of the front surface of the substrate and covering the substrate and the gate structure;
a substrate electrode plug penetrating the interlayer dielectric layer and electrically connected to the first common substrate region; and
and the metal connecting line layer is formed on the surface of the interlayer dielectric layer and is electrically connected with the substrate electrode plug.
Optionally, the substrate further includes a peripheral region formed at a periphery of the first number of pixel regions and the second number of first common substrate regions, and the metal wiring layer extends to the peripheral region.
Optionally, the vertical charge transfer imaging sensor further comprises:
at least one via hole located in the peripheral region and penetrating the substrate, the via hole being electrically connected to the metal wiring layer; and
and the substrate electrode plug is electrically connected with the corresponding metal connecting pad through the metal connecting wire layer and the through hole.
Optionally, the deep trench isolation includes a deep trench formed on the front side of the substrate, an isolation medium formed in the deep trench, and a trench electrode surrounded by the isolation medium.
Optionally, in the grid structure, the distance between the lower end area of the deep trench isolation corresponding to each point on the grid line and the back surface of the substrate is equal or varies within a range.
Optionally, in the grid structure, a depth of the deep trench isolation lower end region corresponding to each intersection of grid lines in the substrate is greater than a depth of the deep trench isolation lower end region corresponding to a non-intersection of grid lines in the substrate.
Optionally, the lower end region of the deep trench isolation corresponding to each intersection of the grid lines penetrates through the substrate, and the lower end region of the deep trench isolation corresponding to the non-intersection of the grid lines does not penetrate through the substrate.
Optionally, the vertical charge transfer imaging sensor further comprises a high dielectric constant layer covering the back side of the substrate.
In one aspect, the present invention provides a method of manufacturing a vertical charge transfer imaging sensor, the method comprising:
providing a substrate having a first doping type and comprising opposite front and back sides;
forming deep trench isolation and shallow trench isolation on the front surface of the substrate, wherein the cross section of the deep trench isolation is of a grid structure so as to define a first number of pixel areas and a second number of first common substrate areas positioned between the pixel areas in the substrate, and each pixel area comprises a photosensitive area and a charge reading area which are defined by the shallow trench isolation;
Forming a grid structure on the surface of the pixel region, and forming a source region and a drain region in the charge reading region, wherein the source region and the drain region are respectively positioned at two sides of the grid structure;
thinning the substrate from the back surface, so that a second common substrate area is formed between the lower end of the deep trench isolation and the back surface of the substrate, and the second common substrate area is communicated with each pixel area and the first common substrate area, wherein the grid structure and the pixel area below the grid structure form a MOS capacitor, and the substrate end voltage of the MOS capacitor is applied to the first common substrate area from the front surface side of the substrate.
Optionally, when the substrate is thinned from the back side, the substrate is thinned to a first thickness by a CMP process and then thinned to a second thickness by a wet etching process.
Optionally, in the grid structure, a depth of a lower end region of the deep trench isolation corresponding to each intersection of grid lines in the substrate is greater than a depth of a lower end region of the deep trench isolation corresponding to a non-intersection of the grid lines in the substrate; and when the substrate is thinned from the back side, taking the lower end area of the deep trench isolation corresponding to each intersection point of the grid lines as an etching stopping point.
In the vertical charge transfer imaging sensor and the manufacturing method of the vertical charge transfer imaging sensor provided by the invention, the first number of pixel areas and the second number of first common substrate areas are limited in the substrate by the deep groove isolation, the effective isolation is formed between the pixel areas by the deep groove isolation, so that the crosstalk of photoelectrons between different pixels is avoided, the grid structure and the pixel areas below the grid structure form a MOS capacitor, in order to apply voltage to the substrate serving as an electrode in the MOS capacitor, a second common substrate area is reserved between the deep groove isolation and the back surface of the substrate, the substrate end voltage of the MOS capacitor is applied to the first common substrate area from the front surface side of the substrate, and the substrate end voltage is transmitted to the substrate of each pixel area through the first common substrate area and the second common substrate area, so that the problems of high interface defect and large contact resistance when the metal electrode is formed on the back surface of the substrate are avoided.
Drawings
Fig. 1 is a schematic plan view of a vertical charge transfer imaging sensor.
FIG. 2 is a schematic cross-sectional view of the vertical charge transfer imaging sensor taken along the direction XX' in FIG. 1.
FIG. 3 is a schematic cross-sectional view of a vertical charge transfer imaging sensor according to an embodiment of the invention.
FIG. 4 is a flow chart of a method for fabricating a vertical charge transfer imaging sensor according to an embodiment of the invention.
Fig. 5A to 5J are schematic cross-sectional views of a method of manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present invention.
Detailed Description
The vertical charge transfer imaging sensor and the method of manufacturing the same of the present invention are described in further detail below with reference to the accompanying drawings and detailed examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely to facilitate and clearly assist in describing embodiments of the present invention, which should not be considered to be limited to the particular shapes of the regions illustrated in the drawings, but may include shapes that are actually obtained, such as manufacturing-induced deviations.
Referring to fig. 3, the vertical charge transfer imaging sensor according to an embodiment of the present invention includes a substrate 10, deep trench isolation DTI and shallow trench isolation STI formed on a front surface 10a of the substrate 10, and a gate structure formed on the front surface 10a of the substrate 10.
Substrate 10 may be any suitable substrate in the art and may include silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or the like. The substrate 10 has a first doping type, such as p-type or n-type, the p-type being exemplified in this embodiment, and the substrate 10 is, for example, a silicon substrate doped with boron or boron difluoride. The substrate 10 has opposite front and back surfaces 10a and 10b.
Deep trench isolation DTI and shallow trench isolation STI are formed on the front surface 10a of the substrate 10, respectively. The shallow trench isolation STI includes a shallow trench formed from the front surface 10a of the substrate 10 and an isolation medium (such as silicon oxide or silicon nitride) filled in the shallow trench. The deep trench isolation DTI includes a deep trench formed from the front surface 10a of the substrate 10 and an isolation medium (such as silicon oxide or silicon nitride) filled in the deep trench. As shown in fig. 3, the deep trench isolation DTI optionally includes a deep trench formed on the front surface 10a of the substrate 10, a liner dielectric layer 105 filled in the deep trench, a trench electrode 106, and a cover layer 107, wherein the liner dielectric layer 105 and the cover layer 107 encapsulate the trench electrode 106 to isolate the trench electrode 106 from the substrate 10, and the liner dielectric layer 105 and the cover layer 107 are isolation dielectrics filled in the deep trench. The trench electrode 106 provides an operable electrode terminal for the vertical charge transfer imaging sensor, and can be matched with other electrode terminals in the sensor to realize various operation modes, for example, by applying a positive bias between the substrate 10 and the trench electrode 106, the potential barrier at the interface of the deep trench isolation DTI and the substrate 10 can be improved, the probability of capturing photoelectrons at the interface is reduced, the photoelectric conversion efficiency is improved, and the dark current and white pixel problems are improved. The trench electrode 106 may extend to a peripheral region of the substrate 10 to be connected to an external electrical signal.
According to an embodiment of the present invention, the cross section of the deep trench isolation DTI is a grid structure, so that the plurality of pixel regions and the first common substrate region in the substrate 10 are defined and isolated by the deep trench isolation DTI. As shown in fig. 3, the deep trench isolation DTI defines a first number of pixel regions A1 and a second number of first common substrate regions A2 located between the first number of pixel regions A1 in the substrate 10. The second number is greater than or equal to 1, further, the first number is, for example, greater than or equal to the second number. Each of the first common substrate regions A2 is, for example, adjacent to at least two pixel regions A1 to be shared by at least two pixel regions A1.
As shown in fig. 3, a second common substrate region A3 is provided between a lower end (a "lower end" refers to an end far from the front surface 10a of the substrate 10, and the same applies hereinafter) of the deep trench isolation DTI and the back surface 10b of the substrate 10, and the second common substrate region A3 is located below each pixel region A1 and the first common substrate region A2 and communicates each pixel region A1 and the first common substrate region A2 (it is explained that the deep trench isolation DTI between each pixel region A1 and the first common substrate region A2 does not completely penetrate the substrate 10).
The front surface 10a of the substrate 10 of each pixel region A1 is formed with shallow trench isolation STI to define a photosensitive region and a charge reading region in the vertical charge transfer imaging sensor pixel with the shallow trench isolation STI. As shown in fig. 3, each pixel region A1 is partitioned by a shallow trench isolation STI to form a photosensitive region 11 and a charge reading region 12. It will be appreciated that the depth of the shallow trench isolation STI in the substrate 10 is less than the depth of the deep trench isolation DTI in the substrate 10, based on the front side 10a of the substrate 10.
The gate structure is located on the front surface 10a of the substrate 10 and is formed on the surface of the pixel area A1. As shown in fig. 3, the gate structure formed on the surface of the pixel area A1 includes a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 109 and a control gate CG stacked on the surfaces of the photosensitive area 11 and the charge reading area 12 of the corresponding pixel area A1, and in this embodiment, the floating gate FG, the inter-gate dielectric layer 109 and the control gate CG extend from the photosensitive area 11 to the charge reading area 12. The control gates CG on the plurality of pixel areas A1 may be connected to form a word line WL. In this embodiment, the gate structure is further formed on the first common substrate area A2, and the control gate CG in the gate structure on the first common substrate area A2 is connected to the control gate CG in the gate structure on the adjacent pixel area A1, and is further connected to the word line WL. The word line WL may cross the first common substrate region A2.
The gate structure and the pixel region A1 below the gate structure (i.e., the pixel region A1 with the surface formed with the gate structure) form a MOS capacitor. In the MOS capacitor, the control gate CG forms one electrode, and the substrate 10 of the pixel area A1 forms the other electrode.
The gate structure formed on the surface of the pixel region A1 exposes part of the charge reading region 12 in the corresponding pixel region A1 on both sides of the extending direction, and the vertical charge transfer imaging sensor further includes a source region S and a drain region D formed in the charge reading region 12 and located on both sides of the gate structure, respectively (the positional relationship between the source region S and the drain region D and the gate structure may refer to fig. 1), wherein the gate structure and the source region S and the drain region D form a reading transistor for reading charges. When the vertical charge transfer imaging sensor is used for photosensitive, two electrodes in the MOS capacitor are pressed, the control gate CG is positively biased relative to the substrate 10 of the pixel area A1, a depletion area is formed in the substrate 10, when light is incident from the back surface 10b of the substrate 10 and collides with a crystal lattice of the substrate to generate photoelectrons, the photoelectrons gather on the surface of the photosensitive area 11 or enter the floating gate FG beyond a potential barrier under the action of an electric field of the depletion area, and the floating gate FG of the photosensitive area 11 and the charge reading area 12 is connected, so that the state of the floating gate FG of the charge reading area 12 is changed due to the photoelectron gathering, and further, the drain current and/or the threshold voltage of the reading transistor are changed, and the vertical charge transfer imaging sensor realizes photoelectric sensing and imaging by detecting the change. The read transistor in a vertical charge transfer imaging sensor pixel is described herein as an N-type device, wherein the source region S and the drain region D have N-type doping. It will be appreciated that in the case where the read transistor is a p-type device, the source region S and the drain region D have p-type doping.
In this embodiment, the substrate terminal voltage in the MOS capacitor is applied from the front surface 10a of the substrate 10 to the first common substrate area A2. The substrate terminal voltage applied to the first common substrate area A2 is transferred to the second common substrate area A3 in the thickness direction of the substrate 10, and since the second common substrate area A3 communicates with the plurality of pixel areas A1, the purpose of the voltage at the bottom of the substrate 10 Shi Jiachen of the plurality of pixel areas A1 is achieved, and the transfer path of the voltage is shown by the dotted arrow in fig. 3.
The first common substrate region A2 may have a substrate contact region (not shown) formed near the front surface 10a of the substrate 10, the substrate contact region having a first doping type doping concentration greater than the surrounding substrate region. The substrate terminal voltage in the MOS capacitor can be applied to the first common substrate region A2 through the substrate contact region, and the doping concentration of the substrate contact region is larger, so that the contact resistance can be reduced.
In order to avoid a large difference in the voltages applied to the substrates 10 of the respective pixel areas A1 due to the difference in the distance between the application positions of the substrate bottom voltages and the pixel areas A1, affecting the photosensitivity, a plurality of first common substrate areas A2 may be disposed dispersed in the substrates 10 according to the number of the pixel areas A1, so that, when the voltages are applied to the substrates 10 of the respective pixel areas A1 using the first common substrate areas A2 and the second common substrate areas A3, the voltages are applied from the plurality of first common substrate areas A2, which helps to equalize the voltages of the different positions of the second common substrate areas A3, that is, equalize the voltages applied to the substrates 10 of the respective pixel areas A1. As an example, the ratio of the first number to the second number is about 100:1 to 200:1.
The thickness of the second common substrate region A3 is the distance of the lower end of the deep trench isolation DTI from the back surface 10b of the substrate 10. If the thickness of the second common substrate area A3 is too large, the substrate 10 between the adjacent pixel areas A1 is thicker, which is easy to increase the crosstalk risk, and if the thickness of the second common substrate area A3 is too small, the resistance of the second common substrate area A3 is larger, which increases the voltage loss, so that the thickness of the second common substrate area A3 can be set according to the isolation requirement and the conductivity requirement of the pixel area A1.
The depths of different regions of the lower end of the deep trench isolation DTI within the substrate 10 may be equal or unequal depending on the design and fabrication process of the deep trench isolation DTI. Specifically, in the grid structure formed by the cross sections of the deep trench isolation DTIs, the depth of the lower end region of the deep trench isolation DTIs corresponding to each point on the grid line in the substrate 10 may be the same or may be different (i.e., may vary within a range).
In an embodiment, with the front surface 10a of the substrate 10 as a reference, the depths of different areas of the lower end of the deep trench isolation DTI in the substrate 10 are equal, and in order to form the second common substrate area A3, the depth is smaller than the thickness of the substrate 10, and the thickness of the second common substrate area A3 between the lower end of the deep trench isolation DTI and the back surface of the substrate 10 is the difference between the thickness of the substrate 10 and the depth of the lower end of the deep trench isolation DTI in the substrate 10. As an example, in this embodiment, the thickness of the second common substrate area A3 is between 0.2 micrometers and 0.4 micrometers.
In this embodiment, the depth of the lower end of the deep trench isolation DTI in the substrate 10 varies within a range with reference to the front surface 10a of the substrate 10. As an example, in the grid structure formed by the cross sections of the deep trench isolation DTIs, the lower end region of the deep trench isolation DTIs corresponding to each intersection of the grid lines is deeper than the lower end region of the deep trench isolation DTIs corresponding to the non-intersection of the grid lines, that is, the depth of the lower end region of the deep trench isolation DTIs corresponding to each intersection of the grid lines in the substrate 10 is greater than the depth of the lower end region corresponding to the non-intersection. The depth of the lower end region of the deep trench isolation DTI corresponding to each intersection of the grid lines may be the same or different in the substrate 10. The depths of the lower end regions of the deep trench isolation DTI corresponding to the plurality of non-intersecting points of the grid lines may be the same or different in the substrate 10. Since the pixel areas A1 and the first common substrate area A2 are separated by the deep trench isolation DTI corresponding to the grid lines, the depth of the lower end area of the deep trench isolation DTI corresponding to the non-intersection point on the grid lines in the substrate 10 can be controlled to be not more than the thickness of the substrate 10, so that a second common substrate area A3 communicated with the pixel areas A1 and the first common substrate area A2 is formed, and on the basis, whether the depth of the lower end area of the deep trench isolation DTI corresponding to the intersection point of the grid lines in the substrate 10 is more than the thickness of the substrate 10 or not does not influence the formation of the second common substrate area A3. Optionally, the lower end regions of the deep trench isolation DTI corresponding to the intersections of the grid lines extend through the substrate 10 (e.g., may protrude from the back surface of the substrate 10 or be flush with the back surface of the substrate 10), while the lower end regions of the deep trench isolation DTI corresponding to the non-intersections of the grid lines do not extend through the substrate 10. The thickness of the second common substrate area A3 is the difference between the depth of the lower end area of the deep trench isolation DTI corresponding to each point on the grid line in the substrate 10 and the thickness of the substrate 10, in this embodiment, the thickness of the second common substrate area A3 varies within a range, the minimum value of the difference between the depth of the lower end area of the deep trench isolation DTI corresponding to each intersection point of the grid line in the substrate 10 and the thickness of the substrate 10 is obtained, and the maximum value of the difference between the thickness of the substrate 10 and the depth of the lower end area corresponding to the non-intersection point and shallowest in the substrate 10 is obtained. As an example, the second common substrate area A3 has a minimum thickness of 0 and a maximum thickness of between 0.2 and 0.4 micrometers.
At the back side 10b of the substrate 10, the vertical charge transfer imaging sensor may further include a high dielectric constant layer 110 overlying the back side 10b of the substrate 10. The high-k layer 110 is made of a high-k material (e.g., al 2 O 3 、Ta 2 O 5 、ZrO 2 、LaO、BaZrO、AlO、HfZrO、HfZrON、HfLaO、HfSiON、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO 3 (BST) or TiO 2 Etc., dielectric constant of, for example, greater than 3.9). The high dielectric constant layer 110 can increase the potential barrier on the back surface 10b of the substrate 10, reduce the probability of capturing photoelectrons on the back surface 10b of the substrate 10, and contribute to an improvement in photoelectric conversion efficiency. In addition, the vertical charge transfer imaging sensor may further comprise a high dielectric layerAn oxide layer on the surface of the electric constant layer 110, which protects the back surface 10b of the substrate 10.
In order to apply a substrate termination voltage to the first common substrate area A2, an electrode structure electrically connected to the first common substrate area A2 may be provided on the front surface 10a of the substrate 10, for example, including a substrate electrode plug electrically connected to the first common substrate area A2 and a metal wiring layer (not shown). Specifically, the vertical charge transfer imaging sensor may include an interlayer dielectric layer formed on the front surface 10a of the substrate 10, a substrate electrode plug and a metal wiring layer, wherein the interlayer dielectric layer covers the substrate 10 and the gate structure, the substrate electrode plug penetrates through the interlayer dielectric layer and is electrically connected to the first common substrate area A2, and the metal wiring layer is formed on the surface of the interlayer dielectric layer and is electrically connected to the substrate electrode plug. Conductive plugs electrically connected to the control gate CG, the source region (S) and the drain region (D) of the read transistor may be further formed in the interlayer dielectric layer, and the metal wiring layer may be electrically connected to each of the conductive plugs.
The substrate 10 may further include a peripheral region located at the periphery of the above-described first number of pixel regions A1 and second number of first common substrate regions A2, which may be used to form part of the circuit of the vertical charge transfer imaging sensor.
In one embodiment, an interconnect structure and a front metal pad connected to the interconnect structure are formed on the front side 10a of the substrate 10, and the front metal pad is used as an input port for the substrate terminal voltage. The interconnection structure can comprise a plurality of patterned conductive layers and conductive plugs which are isolated by dielectric materials, and the metal connecting line layer is a bottom metal layer of the interconnection structure. In another embodiment, the vertical charge transfer imaging sensor includes at least one via formed in the peripheral region and at least one back metal pad formed in the peripheral region on one side of the back surface 10b of the substrate 10, wherein the via penetrates through the substrate 10 and is electrically connected to the metal wiring layer, and the back metal pad is electrically connected to the metal wiring layer and the first common substrate region A2 through the via, and is an input port of a substrate terminal voltage. It should be noted that, the input port for applying the substrate end voltage may be disposed on the front surface 10a side of the substrate 10 or on the back surface 10b side of the substrate 10 as needed, but according to the embodiment of the present invention, the substrate end voltage applied through the input port is applied to the first common substrate area A2 from the front surface 10a side of the substrate 10, transferred to the second common substrate area A3, and applied to the substrate 10 of each pixel area A1 through the second common substrate area A3.
The embodiment of the invention also relates to a manufacturing method of the vertical charge transfer imaging sensor, which can be used for manufacturing the vertical charge transfer imaging sensor described in the embodiment. The method of manufacturing the vertical charge transfer imaging sensor is described below with reference to fig. 4 and 5A to 5J.
Referring to fig. 4 and 5A, step S1 is performed, providing a substrate 10, the substrate 10 having a first doping type and comprising a front side 10a and a back side 10b opposite to each other. By way of example, the substrate 10 is, for example, a silicon substrate and has p-type doping.
Referring to fig. 4, step S2 is performed to form deep trench isolation DTI and shallow trench isolation STI (refer to fig. 5F) on the front surface 10a of the substrate 10.
Alternatively, in an embodiment, the shallow trench isolation STI may include a shallow trench formed from the front surface 10a side of the substrate 10 and an isolation medium filled in the shallow trench. The deep trench isolation DTI may include a deep trench formed from the front surface 10a side of the substrate 10 and an isolation medium filled in the deep trench. The isolation medium in the deep trench isolation DTI and the shallow trench isolation STI may include silicon oxide or silicon nitride, etc. The shallow trench isolation STI and the deep trench isolation DTI may be formed by a conventional trench isolation manufacturing process, and the forming sequence of the shallow trench isolation STI and the deep trench isolation DTI is not particularly limited in this application.
In this embodiment, the deep trench isolation DTI includes a deep trench formed on the front surface 10a of the substrate 10, an isolation medium filled in the deep trench, and a trench electrode, wherein the trench electrode provides an operable electrode terminal for the vertical charge transfer imaging sensor. In the following, step S2 is described by taking the example of forming the shallow trench isolation STI and then forming the deep trench isolation DTI as an example, in other embodiments, the deep trench isolation DTI may be formed first and then forming the shallow trench isolation STI, or may be formed simultaneously.
As an example, step S2 may include the following process:
first, referring to fig. 5A, a pad oxide layer 101 and a first hard mask layer 102 are stacked on a front surface 10a of a substrate 10, and shallow trenches penetrating the first hard mask layer 102, the pad oxide layer 101 and a part of the substrate 10 are formed by one or more etching, then dielectric materials are deposited in the shallow trenches and on the substrate 10, and CMP process is performed to expose the first hard mask layer 102, wherein the shallow trenches and the dielectric materials located therein form shallow trench isolation STI, the pad oxide layer 101 is silicon oxide, the first hard mask layer 102 is silicon nitride, and the depth of the shallow trenches extending from the front surface 10a into the substrate 10 is about 100nm to 400nm;
Thereafter, referring to fig. 5B, a second hard mask layer 103 (for example, a silicon nitride layer) covering the shallow trench isolation STI and the first hard mask layer 102 is formed on the front surface 10a of the substrate 10, and then the position of the deep trench isolation is defined by using a photolithography process, and a deep trench DT extending from the front surface 10a to a depth of about 1.5 μm to 2.5 μm within the substrate 10 is formed through the second hard mask layer 103, the first hard mask layer 102, the pad oxide layer 101 and a portion of the substrate 10 by one or more etching; the cross section of the deep trench DT is a grid structure (the "cross section" is parallel to the front surface 10a of the substrate 10) so as to define a first number of pixel regions A1 in the substrate 10 and a second number of first common substrate regions A2 located between the pixel regions A1, the shallow trench isolation STI is formed in each pixel region A1, and each pixel region A1 includes a photosensitive region 11 and a charge reading region 12 separated by the shallow trench isolation STI;
thereafter, referring to fig. 5C, a linear dielectric layer 105 is formed on the inner surface of the deep trench DT, the top of the deep trench DT may be widened to enhance isolation performance before that, and after the linear dielectric layer 105 is formed, annealing may be performed to repair defects on the surface of the deep trench DT;
Thereafter, referring to fig. 5D, a conductive material is deposited in the deep trench DT and on the second hard mask layer 103, and the upper surface of the conductive material around each pixel region A1 is lowered below the front surface 10a of the substrate 10 by using a CMP process and an etching process, so as to form a trench electrode 106 in the deep trench DT, in this embodiment, the deep trench DT and the trench electrode 106 may extend to a peripheral region of the substrate 10, the peripheral region is located at the periphery of the pixel region A1 and the first common substrate region A2, and for convenience of extraction, the upper surface of the trench electrode 106 in the deep trench DT in the peripheral region may exceed the front surface 10a of the substrate 10;
then, referring to fig. 5E, a dielectric material is deposited on the front surface 10a of the substrate 10 and a CMP process is performed to expose the second hard mask layer 103, then a cover layer 107 is formed in the deep trench DT, the linear dielectric layer 105 and the cover layer 107 are isolation dielectrics filled in the deep trench DT, the trench electrode 106 is wrapped by the linear dielectric layer 105 and the cover layer 107 so as to be insulated from the substrate 10, and the deep trench DT and the linear dielectric layer 105, the cover layer 107 and the trench electrode 106 located in the deep trench DT form a deep trench isolation DTI;
thereafter, referring to fig. 5F, the second hard mask layer 103 and the first hard mask layer 102 are removed.
Referring to fig. 4 and 5G, step S3 is performed to form a gate structure on the surface of the pixel region A1 and to form source and drain regions on the charge reading region 12 of the pixel region A1, the source and drain regions being located on both sides of the gate structure, respectively. The positional relationship between the source region and the drain region and the gate structure can be referred to as fig. 1.
In this embodiment, the gate structure includes a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 109 and a control gate CG stacked on the surfaces of the photosensitive region 11 and the charge reading region 12, and may further include a sidewall covering the sides of the floating gate FG, the inter-gate dielectric layer 109 and the control gate CG, where the floating gate FG, the inter-gate dielectric layer 109, the control gate CG and the sidewall extend from the photosensitive region 11 to the charge reading region 12. Alternatively, the control gates CG in a plurality of the gate structures may be connected to form a word line WL, and as shown in fig. 5G, at least a portion of the word line WL spans the first common substrate area A2. The gate structure and source and drain regions may be formed by processes known in the art, for example, the gate dielectric layer 108 may be formed on the front surface 10a of the substrate 10 by a thermal oxidation process after removing the pad oxide layer 101, and in order to fabricate the source and drain regions of the read transistor in the pixel of the vertical charge transfer imaging sensor, a portion of the charge read region 12 is exposed on a side of the sidewall remote from the control gate CG, and the source and drain regions are formed in the charge read region 12 on both sides of the gate structure by ion implantation, respectively. And will not be described in detail herein.
After forming the gate structure, further, the following process (not shown) may be performed on the front surface 10a of the substrate 10:
forming an interlayer dielectric layer which covers the substrate 10 on which the gate structure is formed from the front surface 10a side;
and forming a plurality of conductive plugs in the interlayer dielectric layer and forming a metal connecting layer on the surface of the interlayer dielectric layer, wherein the conductive plugs penetrate through the interlayer dielectric layer, part of the conductive plugs are electrically connected to the control grid CG, part of the conductive plugs are electrically connected to the source region, part of the conductive plugs are electrically connected to the drain region, part of the conductive plugs are substrate electrode plugs, the substrate electrode plugs penetrate through the interlayer dielectric layer and are electrically connected with the first common substrate region A2, in the embodiment, the first common substrate region A2 is provided with a grid structure, the substrate electrode plugs penetrate through the grid structure and are electrically connected with the first common substrate region A2, when the substrate electrode plugs are formed, a dielectric layer can be formed in the corresponding plug holes to isolate the substrate electrode plugs from the grid structure, and the metal connecting layer is electrically connected with each conductive plug.
After the process of the front surface 10a side of the substrate 10 is completed, referring to fig. 4, step S4 is performed to thin the substrate 10 from the back surface, so that a second common substrate area A3 is formed between the lower end of the deep trench isolation DTI and the back surface 10b of the substrate 10, and the second common substrate area A3 communicates with each pixel area A1 and the first common substrate area A2. A carrier plate may be bonded to the front surface 10a side of the substrate 10 as a support before thinning the substrate 10.
As an example, first, as shown in fig. 5H, the substrate 10 is thinned from the back surface 10b to a first thickness, which may be set as needed, by a CMP process, and when the substrate 10 is the first thickness, the deep trench isolation DTI is not exposed; next, as shown in fig. 5I, the substrate 10 is further thinned from the back surface 10b to a second thickness, which may be set as needed, using a wet etching process. After the CMP process and the wet etching process are completed, at least a part of the substrate 10 is located between the deep trench isolation DTI and the thinned back surface 10b of the substrate 10, and communicates with each pixel region A1 and the first common substrate region A2, which constitutes the second common substrate region A3. The substrate 10 is thinned by performing the CMP process and the wet etching process sequentially, so that the substrate 10 can be thinned rapidly by using the CMP process on one hand, and the thickness control and the flatness of the thinned back surface 10b can be improved by using the wet etching process on the other hand.
When the substrate 10 is thinned, on one hand, the isolation performance of the deep trench isolation DTI for the adjacent pixel region A1 needs to be ensured, and on the other hand, the conductivity of the second common substrate region A3 is improved as much as possible, and a suitable second common substrate region A3 can be formed as required.
In an embodiment, the depths of the different areas at the lower end of the deep trench isolation DTI in the substrate 10 are the same, and after the substrate 10 is thinned to the second thickness, the deep trench isolation DTI is not exposed, and the thickness of the second common substrate area A3 formed between the lower end of the deep trench isolation DTI and the back surface 10b of the substrate 10 is uniform.
In one embodiment, the depth of the different areas at the lower end of the deep trench isolation DTI in the substrate 10 varies within a range, and after the substrate 10 is thinned to the second thickness, the deep trench isolation DTI is not exposed, and the thickness of the second common substrate area A3 formed between the lower end of the deep trench isolation DTI and the back surface 10b of the substrate 10 varies within a range.
In this embodiment, the depth of the lower end of the deep trench isolation DTI in the substrate 10 varies within a range, and in the grid structure formed by the cross sections of the deep trench isolation DTI, the depth of the lower end region of the deep trench isolation DTI corresponding to each intersection point of the grid lines in the substrate 10 is greater than the depth of the lower end region of the deep trench isolation DTI corresponding to the non-intersection point of the grid lines in the substrate 10. When the substrate 10 is thinned from the back surface side, the etching stop can be realized by using the lower end region of the deep trench isolation DTI corresponding to each intersection of the grid lines. Specifically, when the substrate 10 is thinned to the first thickness by using the CMP process, the deep trench isolation DTI may be controlled not to be exposed at all, and when the substrate 10 is thinned to the second thickness by further using the wet etching process, the lower end region of the deep trench isolation DTI corresponding to each intersection of the grid lines may be taken as an etching stop point, that is, when the lower end region of the deep trench isolation DTI corresponding to the intersection of the grid lines is exposed during the thinning of the substrate 10 to the second thickness, etching is stopped, and at this time, the lower end region of the deep trench isolation DTI corresponding to the non-intersection of the grid lines is not exposed, and the remaining portion of the substrate 10 between the lower end region of the deep trench isolation DTI corresponding to the non-intersection of the grid lines and the back surface 10b of the substrate 10 constitutes the second common substrate region A3.
After forming the second common substrate region A3, referring to fig. 5J, optionally, a high dielectric constant layer 110 and an oxide layer 111 covering the high dielectric constant layer 110 may be further formed on the back surface 10b of the substrate 10.
In the vertical charge transfer imaging sensor and the method for manufacturing the vertical charge transfer imaging sensor described in the above embodiments, the deep trench isolation DTI formed on the front surface 10a of the substrate 10 defines a first number of pixel areas A1 and a second number of first common substrate areas A2 located between the pixel areas A1 in the substrate 10, and the deep trench isolation DTI can form effective isolation between the pixel areas A1 to avoid crosstalk; in addition, the gate structure formed on the surface of the pixel region A1 and the corresponding pixel region A1 form a MOS capacitor, and in order to apply a substrate terminal voltage to the substrate 10 serving as an electrode in the MOS capacitor, a second common substrate region A3 is reserved between the deep trench isolation DTI and the back surface 10b of the substrate 10, the second common substrate region A3 is communicated with each pixel region A1 and the first common substrate region A2, the substrate terminal voltage in the MOS capacitor is applied to the first common substrate region A2 from the front surface 10a side of the substrate 10, and the substrate terminal voltage can be transferred to the substrate 10 of each pixel region A1 through the first common substrate region A2 and the second common substrate region A3. By using the method for manufacturing the vertical charge transfer imaging sensor described in the above embodiment, applying the substrate terminal voltage to the substrate 10 as an electrode in the MOS capacitor does not require forming a metal electrode contacting the substrate 10 on the back surface 10b of the substrate 10, and the problems of high interface defect and large contact resistance when forming such a metal electrode can be avoided; in addition, by applying the substrate terminal voltage to the first common substrate region A2 from the front surface 10a side of the substrate 10, voltage loss can be reduced, which contributes to making uniform the substrate terminal voltage corresponding to each of the pixel regions A1, as compared with the substrate 10 in which the voltage is directly applied to each of the pixel regions A1 from the peripheral region of the substrate 10.
It should be noted that, the embodiments in this specification are described in a progressive manner, and each part is mainly described as different from the foregoing parts, where identical and similar parts are mutually referred to.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, since any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and the technical solution disclosed above without departing from the spirit and scope of the invention, any simple modification, equivalent variation and modification of the above embodiments according to the technical solution of the present invention shall fall within the scope of the technical solution of the present invention.

Claims (13)

1. A vertical charge transfer imaging sensor, comprising:
a substrate having a first doping type and comprising opposite front and back sides;
the deep trench isolation is formed on the front surface of the substrate, the cross section of the deep trench isolation is of a grid structure so as to define a first number of pixel areas and a second number of first common substrate areas positioned between the pixel areas in the substrate, and a second common substrate area is arranged between the lower end of the deep trench isolation and the back surface of the substrate and is communicated with each pixel area and the first common substrate area;
Shallow trench isolation formed on the front surface of the substrate, wherein each pixel region comprises a photosensitive region and a charge reading region which are defined by the shallow trench isolation; and
the grid structure is formed on the surface of the pixel area, and the grid structure and the pixel area below the grid structure form a MOS capacitor, wherein the substrate terminal voltage of the MOS capacitor is applied to the first common substrate area from one side of the front surface of the substrate.
2. The vertical charge transfer imaging sensor of claim 1, wherein the gate structure comprises a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked on the surface of the photosensitive region and the charge readout region, wherein the floating gate, the inter-gate dielectric layer, and the control gate extend from the photosensitive region to the charge readout region; the vertical charge transfer imaging sensor further comprises a source region and a drain region which are formed in the charge reading region and are respectively positioned on two sides of the gate structure, and the gate structure, the source region and the drain region form a reading transistor.
3. The vertical charge transfer imaging sensor of claim 1, further comprising:
an interlayer dielectric layer formed on one side of the front surface of the substrate and covering the substrate and the gate structure;
A substrate electrode plug penetrating the interlayer dielectric layer and electrically connected to the first common substrate region; and
and the metal connecting line layer is formed on the surface of the interlayer dielectric layer and is electrically connected with the substrate electrode plug.
4. The vertical charge transfer imaging sensor of claim 3, wherein said substrate further comprises a peripheral region formed at a periphery of said first number of pixel regions and said second number of first common substrate regions, said metal wiring layer extending to said peripheral region.
5. The vertical charge transfer imaging sensor of claim 4, further comprising:
at least one via hole located in the peripheral region and penetrating the substrate, the via hole being electrically connected to the metal wiring layer; and
and the substrate electrode plug is electrically connected with the corresponding metal connecting pad through the metal connecting wire layer and the through hole.
6. The vertical charge transfer imaging sensor of claim 1, wherein the deep trench isolation comprises a deep trench formed in the front side of the substrate, an isolation medium formed in the deep trench, and a trench electrode surrounded by the isolation medium.
7. The vertical charge transfer imaging sensor of claim 1, wherein a distance between a lower end region of the deep trench isolation corresponding to each point on a grid line and the back surface of the substrate in the grid structure is equal or varies within a range.
8. The vertical charge transfer imaging sensor of claim 7, wherein a depth of a lower end region of the deep trench isolation corresponding to each intersection of grid lines in the grid structure is greater in the substrate than a depth of a lower end region of the deep trench isolation corresponding to a non-intersection of the grid lines in the substrate.
9. The vertical charge transfer imaging sensor of claim 8, wherein lower end regions of the deep trench isolation corresponding to respective intersections of the grid lines extend through the substrate, and lower end regions of the deep trench isolation corresponding to non-intersections of the grid lines do not extend through the substrate.
10. The vertical charge transfer imaging sensor of claim 1, further comprising a high dielectric constant layer overlying the back surface of the substrate.
11. A method of manufacturing a vertical charge transfer imaging sensor, comprising:
Providing a substrate having a first doping type and comprising opposite front and back sides;
forming deep trench isolation and shallow trench isolation on the front surface of the substrate, wherein the cross section of the deep trench isolation is of a grid structure so as to define a first number of pixel areas and a second number of first common substrate areas positioned between the pixel areas in the substrate, and each pixel area comprises a photosensitive area and a charge reading area which are defined by the shallow trench isolation;
forming a grid structure on the surface of the pixel region, and forming a source region and a drain region in the charge reading region, wherein the source region and the drain region are respectively positioned at two sides of the grid structure;
thinning the substrate from the back surface, so that a second common substrate area is formed between the lower end of the deep trench isolation and the back surface of the substrate, and the second common substrate area is communicated with each pixel area and the first common substrate area, wherein the grid structure and the pixel area below the grid structure form a MOS capacitor, and the substrate end voltage of the MOS capacitor is applied to the first common substrate area from the front surface side of the substrate.
12. The method of manufacturing of claim 11, wherein the substrate is thinned from the back side to a first thickness using a CMP process and then to a second thickness using a wet etching process.
13. The method of manufacturing of claim 11, wherein in the grid structure, a depth of a lower end region of the deep trench isolation corresponding to each intersection of grid lines in the substrate is greater than a depth of a lower end region of the deep trench isolation corresponding to a non-intersection of grid lines in the substrate; and when the substrate is thinned from the back side, taking the lower end area of the deep trench isolation corresponding to each intersection point of the grid lines as an etching stopping point.
CN202311406409.9A 2023-10-26 2023-10-26 Vertical charge transfer imaging sensor and method of manufacturing the same Pending CN117334707A (en)

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