CN117332748A - Method, equipment and storage medium for optimizing insertion redundancy through holes - Google Patents
Method, equipment and storage medium for optimizing insertion redundancy through holes Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuit manufacturing, in particular to an insertion redundancy through hole optimizing method, equipment and a storage medium, wherein the insertion redundancy through hole optimizing method comprises the following steps: providing a physical design tool, respectively inserting typical physical design results by using different types of redundant through holes, and obtaining corresponding first physical design results aiming at each type of redundant through holes; acquiring the weight of each redundant through hole; aiming at different positions of the same typical physical design result, respectively selecting one redundant through hole with the largest weight for insertion to obtain a second physical design result; and optimizing and detecting the second physical design result by using a calculation photoetching tool, judging whether a preset problem occurs, and if the preset problem does not occur, storing the optimization result. The technical problem that more photoetching dead spots are easily caused in the process of inserting the redundant through holes in the prior art is solved.
Description
[ field of technology ]
The invention relates to the technical field of integrated circuit manufacturing, in particular to an inserting redundancy through hole optimizing method, inserting redundancy through hole optimizing equipment and a storage medium.
[ background Art ]
In the integrated circuit field, a redundant via insertion process is an essential process in the physical design phase, and the main purpose of the process is to improve the yield of chip manufacturing. The insertion of conventional redundant vias is mainly at the stage of winding. Some schemes can make insertion attempts in the winding process, most schemes make insertion attempts based on greedy algorithm after winding, the main consideration of the insertion process is that design rules cannot be violated, and then the insertion is selected from a series of redundant through holes with weights set by users, wherein the redundant through holes with the highest weights are inserted.
However, in the conventional redundant via insertion process described above, since there is no direct intervention of the computational lithography tool, the following problems occur. The insertion of the redundant through holes is to replace a single through hole with a double through hole under most conditions, the situation that the rectangle is replaced with a polygon is difficult to avoid when the upper metal layer and the lower metal layer of the through holes are replaced before and after replacement, and the polygon has larger influence on a process window compared with the rectangle, so that more photoetching dead spots are caused.
[ invention ]
In order to solve the technical problem that more photoetching dead spots are easily caused in the insertion process of the redundant through holes in the prior art, the invention provides an optimization method, equipment and a storage medium for inserting the redundant through holes.
The invention provides an optimization method for inserting redundant through holes, which comprises the following steps: providing a physical design tool and typical physical design results, respectively inserting the typical physical design results by using different types of redundant through holes, and obtaining a corresponding first physical design result for each type of redundant through holes; providing a calculation photoetching tool to obtain weights of different positions of each redundant through hole in the insertion typical physical design result according to the first physical design result; aiming at different positions of the same typical physical design result, respectively selecting one redundant through hole with the largest weight for insertion to obtain a second physical design result; and optimizing and detecting a second physical design result by using a calculation photoetching tool, detecting and judging whether a preset problem occurs according to a photoetching rule, and taking the second physical design result and a redundant through hole inserted in a corresponding position as an optimization result if the preset problem does not occur.
Preferably, the step of providing a computational lithography tool to obtain weights for each of the redundant vias at different locations in the inserted typical physical design result based on the first physical design result includes the steps of: providing a calculation photoetching tool, and performing mask optimization on a first physical design result obtained by inserting each redundant through hole; obtaining key indexes of the same redundant through hole, which influence the lithography rule detection result in the insertion of different positions of the first physical design result, according to the lithography rule detection result corresponding to the mask after the mask optimization; and calculating weights of different positions of the corresponding types of redundant through holes in the inserted typical physical design according to the key indexes.
Preferably, the key indicator includes a type of first photolithography rule violation and a first frequency of a corresponding type.
Preferably, the first photolithography rule violation category includes bridging and squeezing.
Preferably, the weights of different positions of the redundant through holes after the insertion of the typical physical design result are obtained by adding the first frequencies corresponding to all the first photoetching rule violation categories in the key indexes.
Preferably, the preset problem is specifically an increase in the frequency of the types of the photolithography rule violations corresponding to the key indexes.
Preferably, the analyzing the second physical design result by using a computational lithography tool, and determining whether the preset problem occurs includes the following steps: performing mask optimization on the second physical design result by using a calculation photoetching tool; obtaining a second photoetching rule violation type and a second frequency of a corresponding type according to a photoetching rule detection result obtained after mask optimization; comparing the second lithographic rule violation category with the first lithographic rule violation category, and comparing the first frequency of the corresponding lithographic rule category with the second frequency; if the second photoetching rule violation type is not larger than the second photoetching rule violation type and the second frequency is not larger than the first frequency, the preset problem does not occur; otherwise, the preset problem occurs.
Preferably, if a preset problem occurs, adding the increased type of the violation of the photolithography rule and/or the increased frequency to the key index, and returning to providing a calculation photolithography tool to obtain the weighted position of each redundant via at a different position in the typical physical design result according to the first physical design result for iteration.
The invention also provides an inserting redundancy through hole optimizing device for solving the technical problems, which comprises a memory for storing a computer program and a second physical design result; and the processor is used for realizing the steps of the method for optimizing the insertion of the redundant through holes when executing the computer program.
The present invention also provides a storage medium, in which a computer program is stored, the computer program implementing the steps of the above-mentioned method for optimizing insertion of redundant vias when executed by a processor.
Compared with the prior art, the method, the device and the storage medium for optimizing the insertion redundancy through holes have the following advantages:
1. the method for optimizing the insertion of the redundant through holes provided by the embodiment of the invention comprises the following steps: providing a physical design tool and typical physical design results, respectively inserting the typical physical design results by using different types of redundant through holes, and obtaining a corresponding first physical design result for each type of redundant through holes; providing a calculation photoetching tool to obtain weights of different positions of each redundant through hole in the insertion typical physical design result according to the first physical design result; aiming at different positions of the same typical physical design result, respectively selecting one redundant through hole with the largest weight for insertion to obtain a second physical design result; and optimizing and detecting a second physical design result by using a calculation photoetching tool, detecting and judging whether a preset problem occurs according to a photoetching rule, and taking the second physical design result and a redundant through hole inserted in a corresponding position as an optimization result if the preset problem does not occur. In the process of inserting the redundant through holes, the auxiliary verification is performed by using a calculation photoetching tool, and photoetching friendly redundant through hole weights are generated, so that a friendly redundant through hole insertion flow is realized, and photoetching dead points are avoided or the number of the photoetching dead points is minimized.
2. The method for optimizing the insertion of the redundant through holes provided by the embodiment of the invention comprises the steps of providing a calculation photoetching tool for optimizing a mask of a first physical design result obtained by inserting each redundant through hole, wherein the calculation photoetching tool obtains weights of different positions of each redundant through hole in the typical physical design result according to the first physical design result; obtaining key indexes of the same redundant through hole, which influence the lithography rule detection result in the insertion of different positions of the first physical design result, according to the lithography rule detection result corresponding to the mask after the mask optimization; and calculating weights of different positions of the corresponding types of redundant through holes in the inserted typical physical design according to the key indexes, and obtaining the inserted weights of the redundant through holes by using a calculation photoetching tool is beneficial to avoiding or minimizing the number of photoetching dead points.
3. According to the optimization method for inserting the redundant through holes, which is provided by the embodiment of the invention, the weights of the redundant through holes at different positions after the typical physical design result is inserted are obtained by adding the first frequencies corresponding to all the first photoetching rule violation types in the key indexes, so that the calculation is simple, the operation is convenient, and the weights of the redundant through holes can be calculated rapidly.
4. The method for optimizing the inserted redundant through holes provided by the embodiment of the invention utilizes a calculation photoetching tool to analyze the second physical design result, and judges whether the preset problem occurs or not, and the method comprises the following steps: performing mask optimization on the second physical design result by using a calculation photoetching tool; and obtaining a second photoetching rule violation type and a second frequency of the corresponding type according to a photoetching rule detection result obtained after mask optimization, judging whether a preset problem is generated according to the first photoetching rule and the second photoetching rule, wherein the preset problem is related to the quality of a process window, if the preset problem does not occur, the process window in the result has no obvious general problem, and if the preset problem occurs, the process window in the result has poor conditions, which cause photoetching dead spots to occur easily. By comparison, the improvement of the number of the photoresist dead pixels in practical application can be clearly understood by utilizing the weight of the redundant through holes detected and obtained by the calculation photoetching tool.
5. In the method for optimizing the insertion of the redundant through holes, if the preset problem does not occur, the second physical design result and the redundant through holes inserted in the corresponding positions are used as the optimized result, and specifically, a memory or a storage device is further provided, and the optimized result is stored in a database, so that the actual physical equipment is convenient to use for example.
6. According to the optimization method for inserting the redundant through holes, if the preset problem occurs, the increased types of photoetching rule violation and/or the increased frequency are added into the key indexes, and the iteration is carried out until a calculation photoetching tool is provided to obtain the weight positions of each redundant through hole at different positions in the typical physical design result according to the first physical design result, and factors which are easy to generate photoetching dead points are continuously added into the key indexes through continuous iteration to further adjust the weights of different redundant through holes, so that the insertion flow of the redundant through holes is continuously optimized.
7. The device for optimizing the inserted redundant through hole provided in the embodiment of the invention comprises a memory and a processor, wherein the memory is used for storing a computer program and a second physical design result, and the processor is used for realizing the steps of the method for optimizing the inserted redundant through hole when executing the computer program, and has the same beneficial effects as the method for optimizing the inserted redundant through hole, and the description is omitted herein.
8. The storage medium provided in the embodiment of the present invention stores a computer program, where the computer program realizes the steps of the above-mentioned method for optimizing insertion of redundant through holes when being executed by a processor, and has the same beneficial effects as the above-mentioned method for optimizing insertion of redundant through holes, and details are not repeated herein.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.
Fig. 1 is a flowchart of an optimization method for inserting redundant vias according to a first embodiment of the present invention.
Fig. 2 is a flowchart of the steps for obtaining weights of redundant vias at different locations according to the first embodiment of the present invention.
Fig. 3 is a flowchart of steps for optimizing and detecting the second physical design result and judging whether the preset problem occurs according to the first embodiment of the present invention.
[ detailed description ] of the invention
The present invention will be described in further detail with reference to the accompanying drawings and examples of implementation in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
For easy understanding, the present invention will be explained first as follows:
physical design tool: refers to a tool or software for performing the physical design of a chip. The function of the circuit is to convert the logic design into physical layout according to the design requirement and rule, and place and connect each element and circuit on the chip to realize the circuit function. The physical design tool can help the designer optimize the chip layout and wiring, and improve the circuit performance and power consumption.
Computing a lithography tool: tools for assisting in lithographic process design and optimization using computer simulations and algorithms. Photolithography is an important step in the chip manufacturing process by which circuit patterns in the chip design can be transferred to a silicon wafer. In integrated circuit fabrication, computational lithography tools are widely used in the simulation of photoresist exposure and development processes, optical pattern correction and optimization, and lithography failure detection.
Referring to fig. 1 and 2, a method for optimizing insertion of redundant vias according to a first embodiment of the present invention includes the following steps:
s1: providing a physical design tool and typical physical design results, respectively inserting the typical physical design results by using different types of redundant through holes, and obtaining a corresponding first physical design result for each type of redundant through holes;
s2: providing a calculation photoetching tool to obtain weights of different positions of each redundant through hole in the insertion typical physical design result according to the first physical design result;
s3: aiming at different positions of the same typical physical design result, respectively selecting one redundant through hole with the largest weight for insertion to obtain a second physical design result;
s4: optimizing and detecting the second physical design result by using a calculation photoetching tool, judging whether a preset problem occurs or not according to photoetching rule detection,
s5a: and if the preset problem does not occur, taking the second physical design result and the redundant through holes inserted in the corresponding positions as optimization results.
S5b: if the preset problem occurs, adding the increased type of the photoetching rule violation and/or the increased frequency into the key index, and returning to the step S2 for iteration.
It should be noted that, S5a and S5b are two different execution modes, that is, after step S4, either one of the modes S5a and S5b is selected to be executed according to the result of the determination.
It should be noted that, in step S1, the typical physical design result refers to an intermediate data result obtained by performing the main physical design process but not performing the redundant via insertion; in the photoetching process, the insertion of the redundant through holes is a method for enhancing circuit connection by adding an additional through hole structure in a specific area of a chip, and the principle of the insertion of the redundant through holes is that the circuit can be connected more flexibly by adding the additional through hole structure in the specific area of the chip during design. The redundant through holes can be divided into multiple types according to the size, shape, material and the like, different types of redundant through holes are respectively used for inserting typical physical design results through a physical design tool, and a group of first physical design results are obtained for one type of redundant through holes. It can be understood that by inserting different kinds of redundant through holes, multiple groups of different first physical design results are obtained, so that the optimal one or more redundant through holes can be conveniently selected for insertion.
It should be noted that in step S2, the weights of different positions of each redundant through hole in the typical physical design result are obtained by analyzing the multiple groups of first physical design results by using the calculation lithography tool, and the weights of the redundant through holes are used to measure the importance of the insertion of the redundant through holes in the insertion process, so that the larger the weights of the redundant through holes are, the more the types of the corresponding selected redundant through holes are beneficial to improving the yield of chip manufacturing after insertion, and the lithography dead spots are not easy to occur.
In step S3, the weights of the redundant vias obtained in step S2 are used to insert the redundant vias with the largest weights at different positions of the typical physical design result, so as to obtain the second physical design result. When the weights of two redundant vias at the same location are equal, one of the two redundant vias may be selected at random.
In step S4, the second physical design result is checked by using the calculation lithography tool, and the optimization is ended or iterated to S2 to continue according to whether the preset problem is violated.
In the prior art, a single through hole may not meet the requirements of design rules and manufacturing processes under some conditions, so in order to improve current transmission capability and anti-interference capability, a process window is optimized, circuit performance is improved, a redundant through hole is usually inserted into a double through hole, after a photoetching dead point is generated, the double through hole is replaced into the single through hole, and the process is contrary to the process of inserting the redundant through hole, therefore, it can be understood that a photoetching friendly redundant through hole weight is generated by performing auxiliary verification by using a calculation photoetching tool in the process of inserting the redundant through hole, so that a friendly redundant through hole inserting process is realized, the photoetching dead point is avoided or the number of the photoetching dead points is minimized.
Further, step S2 includes the steps of:
s21: providing a calculation photoetching tool, and performing mask optimization on a first physical design result obtained by inserting each redundant through hole;
s22: obtaining key indexes of the same redundant through hole, which influence the lithography rule detection result in the insertion of different positions of the first physical design result, according to the corresponding lithography rule detection result after mask optimization;
s23: calculating weights of different positions of the corresponding types of redundant through holes in the typical physical design according to the key indexes;
it should be noted that, the key indicator specifically refers to the type of the first photolithography rule violation and the first frequency of the corresponding type, where occurrence of the photolithography rule violation may cause a change in the shape of the pattern during the manufacturing process, which may negatively affect the circuit performance, and may also cause a defect in the manufacturing process. Therefore, detection and repair of these violation categories is an important step in the lithographic process to ensure good manufacturing quality and circuit performance. Specifically, in this embodiment, the types of first photolithography rule violations include bridging and extrusion, and specifically, bridging refers to an occurrence of an undesirable connection or connection between photolithography patterns, which results in narrowing or disappearance of an interval between patterns, and further results in short circuit or interference between circuit elements; extrusion refers to the occurrence of undesirable gaps or pattern narrowing between photolithographic patterns, resulting in smaller spacing between circuit elements, further resulting in shorting or functional failure between circuit elements. It can be understood that the kind of the lithography rule violation easily occurring in the insertion process of the redundant via is used as a key index, so that the interference of other factors is reduced.
In some embodiments, the types of first lithography rule violations further include cuts, offsets, gaps, and the like, which are not specifically limited.
It should be noted that, in step S5b, if a preset problem occurs, the increased type of violation of the photolithography rule and/or the increased frequency are added to the key index, and the process specifically iterates to S23, and by adding factors that cause occurrence of photolithography damage to the key index, it is convenient to recalculate the weights of the redundant vias according to the factors, and when the insert typical physical design result with the largest weight is selected from the multiple redundant vias, occurrence of photolithography bad pixels due to the factors can be avoided or reduced to the greatest extent.
In step S21, mask optimization is used to optimize the photolithographic exposure of the chip pattern on the silicon wafer. The goal of mask optimization is to maximize the manufacturing quality and performance of the chip. In this process, the lithography tool optimizes the chip pattern based on the characteristics of the lithography machine and the characteristics of the photoresist to achieve the desired exposure effect. Mask optimization can be achieved by adjusting parameters such as dose of exposure agent, exposure time, sensitization degree of photoresist and the like. The optimized physical design result is used for the next lithography rule detection.
It should be noted that, in step S22, the mask-optimized physical design result is subjected to a photolithography rule detection, so as to obtain a photolithography rule detection result, where the photolithography rule detection is a process of regularly checking a photolithography pattern, so as to ensure that a chip can be correctly manufactured in a photolithography process.
It should be noted that, in step S23, the specific method for calculating the weight may be determined according to the specific requirements and design rules. Common methods of computing weights include experience and expert knowledge based evaluations, mathematical model and algorithm based calculations, and the like. The method can carry out weighted calculation according to the importance and the weight of the key indexes, so that the weight values of the redundant through holes at different positions are obtained. The higher the weight value, the greater the impact that the redundant vias representing that location have on chip performance and reliability.
In this embodiment, a preferred method for calculating the weight is to obtain the type of the first photolithography rule violation and the corresponding frequency in the specific position of the typical physical design result, and then add the frequencies of the photolithography rule violations to obtain the weight of the corresponding redundant through hole, which simplifies the calculation process and facilitates the calculation.
It can be understood that by calculating the obtained weight value, a designer can further optimize the insertion process according to the weight of the redundant via hole, and select a suitable position and layout of the redundant via hole, so as to improve the performance and reliability of the chip to the greatest extent.
Further, referring to fig. 1 and 3, step S4 includes the following steps:
s41: performing mask optimization on the second physical design result by using a calculation photoetching tool;
s42: obtaining a second photoetching rule violation type and a second frequency of a corresponding type according to a photoetching rule detection result obtained after mask optimization;
s43: comparing the second type of the violation of the lithography rule with the first type of the violation of the lithography rule, and comparing the first frequency corresponding to the type of the lithography rule with the second frequency to determine whether a preset problem occurs;
it should be noted that, the preset problem is specifically that the number of times of the photolithography rule violation types increases, which is related to the advantages and disadvantages of the process window, if the preset problem does not occur, the process window in the description result has no obvious general problem, if the preset problem occurs, some general process windows in the description result are poor, so that the photolithography dead spots are easy to occur.
Specifically, if the type and frequency of the second photolithography rule violation increase relative to at least one of the type and frequency of the first photolithography rule violation, a predetermined problem is generated, specifically, the type of the second photolithography rule violation is greater than the type of the first photolithography rule violation, and/or the second frequency of the second photolithography rule violation corresponding to the type of the second photolithography rule violation is greater than the first frequency of the first photolithography rule violation corresponding to the type of the first photolithography rule violation, step S5a is performed, and the type and/or frequency of the correspondingly increased violation photolithography rule is further added to the key index, and the process is circulated to S23, i.e. the weight of the corresponding redundant via is recalculated until the predetermined problem is not finally violated.
It should be noted that, in the iterative process, the type and frequency of the first photolithography rule violation are kept unchanged as initial values, and meanwhile, because the parameters for calculating the weights of the redundant vias are changed, correspondingly, the second physical design result obtained by inserting the typical physical design result according to the weights of the redundant vias is changed, and the second photolithography rule violation type and frequency are detected and then compared with the first photolithography rule violation type and frequency until the second photolithography rule violation type and frequency are not greater than the first photolithography rule violation type and frequency.
If the type and frequency of the second photolithography rule violation are not greater than the type and frequency of the first photolithography rule violation, specifically, the type of the second photolithography rule violation is not greater than the type of the first photolithography rule violation, and the second frequency of the second photolithography rule violation corresponding to the type of the second photolithography rule violation is not greater than the first frequency of the first photolithography rule violation corresponding to the type of the first photolithography rule violation, step S5b is performed, and the second physical design result and the redundancy of the corresponding position are used as the optimization result and stored in the database for the actual physical design use case.
It should be noted that, through continuous iteration, factors which are easy to generate lithography dead spots are continuously added into key indexes to further adjust weights of different redundant through holes, so that the insertion flow of the redundant through holes is continuously optimized.
A second embodiment of the present invention provides an insertion redundant via optimization apparatus, including a memory for storing a computer program and a second physical design result, and a processor for implementing the steps of an insertion redundant via optimization method as in embodiment 1 when the processor is configured to execute the computer program.
Specifically, the insertion redundancy through hole optimizing device has the same advantages as the above-mentioned insertion redundancy through hole optimizing method, and details thereof are omitted herein.
A third embodiment of the present invention provides a storage medium having a computer program stored thereon, which when executed by a processor, implements a method for optimizing insertion of redundant vias as in the first embodiment.
Specifically, a storage medium has the same advantages as the above-mentioned method for optimizing insertion of redundant through holes, and will not be described herein.
It will be appreciated that the processes described above with reference to flowcharts may be implemented as computer software programs in accordance with embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such embodiments, the computer program may be downloaded and installed from a network via a communication portion, and/or installed from a removable medium. The above-described functions defined in the method of the present application are performed when the computer program is executed by a Central Processing Unit (CPU). It should be noted that the computer readable medium of the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium includes, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present application may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
In the embodiments provided herein, it should be understood that "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art will also appreciate that the embodiments described in the specification are alternative embodiments and that the acts and modules referred to are not necessarily required for the present invention.
In various embodiments of the present invention, it should be understood that the sequence numbers of the foregoing processes do not imply that the execution sequences of the processes should be determined by the functions and internal logic of the processes, and should not be construed as limiting the implementation of the embodiments of the present invention.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, with the determination being made based upon the functionality involved. It will be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Compared with the prior art, the method, the device and the storage medium for optimizing the insertion redundancy through holes have the following advantages:
1. the method for optimizing the insertion of the redundant through holes provided by the embodiment of the invention comprises the following steps: providing a physical design tool and typical physical design results, respectively inserting the typical physical design results by using different types of redundant through holes, and obtaining a corresponding first physical design result for each type of redundant through holes; providing a calculation photoetching tool to obtain weights of different positions of each redundant through hole in the insertion typical physical design result according to the first physical design result; aiming at different positions of the same typical physical design result, respectively selecting one redundant through hole with the largest weight for insertion to obtain a second physical design result; and optimizing and detecting a second physical design result by using a calculation photoetching tool, detecting and judging whether a preset problem occurs according to a photoetching rule, and taking the second physical design result and a redundant through hole inserted in a corresponding position as an optimization result if the preset problem does not occur. In the process of inserting the redundant through holes, the auxiliary verification is performed by using a calculation photoetching tool, and photoetching friendly redundant through hole weights are generated, so that a friendly redundant through hole insertion flow is realized, and photoetching dead points are avoided or the number of the photoetching dead points is minimized.
2. The method for optimizing the insertion of the redundant through holes provided by the embodiment of the invention comprises the steps of providing a calculation photoetching tool for optimizing a mask of a first physical design result obtained by inserting each redundant through hole, wherein the calculation photoetching tool obtains weights of different positions of each redundant through hole in the typical physical design result according to the first physical design result; obtaining key indexes of the same redundant through hole, which influence the lithography rule detection result in the insertion of different positions of the first physical design result, according to the lithography rule detection result corresponding to the mask after the mask optimization; and calculating weights of different positions of the corresponding types of redundant through holes in the inserted typical physical design according to the key indexes, and obtaining the inserted weights of the redundant through holes by using a calculation photoetching tool is beneficial to avoiding or minimizing the number of photoetching dead points.
3. According to the optimization method for inserting the redundant through holes, which is provided by the embodiment of the invention, the weights of the redundant through holes at different positions after the typical physical design result is inserted are obtained by adding the first frequencies corresponding to all the first photoetching rule violation types in the key indexes, so that the calculation is simple, the operation is convenient, and the weights of the redundant through holes can be calculated rapidly.
4. The method for optimizing the inserted redundant through holes provided by the embodiment of the invention utilizes a calculation photoetching tool to analyze the second physical design result, and judges whether the preset problem occurs or not, and the method comprises the following steps: performing mask optimization on the second physical design result by using a calculation photoetching tool; and obtaining a second photoetching rule violation type and a second frequency of the corresponding type according to a photoetching rule detection result obtained after mask optimization, judging whether a preset problem is generated according to the first photoetching rule and the second photoetching rule, wherein the preset problem is related to the quality of a process window, if the preset problem does not occur, the process window in the result has no obvious general problem, and if the preset problem occurs, the process window in the result has poor conditions, which cause photoetching dead spots to occur easily. By comparison, the improvement of the number of the photoresist dead pixels in practical application can be clearly understood by utilizing the weight of the redundant through holes detected and obtained by the calculation photoetching tool.
5. In the method for optimizing the insertion of the redundant through holes, if the preset problem does not occur, the second physical design result and the redundant through holes inserted in the corresponding positions are used as the optimized result, and specifically, a memory or a storage device is further provided, and the optimized result is stored in a database, so that the actual physical equipment is convenient to use for example.
6. According to the optimization method for inserting the redundant through holes, if the preset problem occurs, the increased types of photoetching rule violation and/or the increased frequency are added into the key indexes, and the iteration is carried out until a calculation photoetching tool is provided to obtain the weight positions of each redundant through hole at different positions in the typical physical design result according to the first physical design result, and factors which are easy to generate photoetching dead points are continuously added into the key indexes through continuous iteration to further adjust the weights of different redundant through holes, so that the insertion flow of the redundant through holes is continuously optimized.
7. The device for optimizing the inserted redundant through hole provided in the embodiment of the invention comprises a memory and a processor, wherein the memory is used for storing a computer program and a second physical design result, and the processor is used for realizing the steps of the method for optimizing the inserted redundant through hole when executing the computer program, and has the same beneficial effects as the method for optimizing the inserted redundant through hole, and the description is omitted herein.
8. The storage medium provided in the embodiment of the present invention stores a computer program, where the computer program realizes the steps of the above-mentioned method for optimizing insertion of redundant through holes when being executed by a processor, and has the same beneficial effects as the above-mentioned method for optimizing insertion of redundant through holes, and details are not repeated herein.
The foregoing describes in detail a method, apparatus and storage medium for optimizing insertion redundancy through holes disclosed in the embodiments of the present invention, and specific examples are applied herein to illustrate the principles and embodiments of the present invention, and the above description of the embodiments is only for helping to understand the method and core idea of the present invention; meanwhile, as for those skilled in the art, according to the idea of the present invention, there are changes in the specific embodiments and the application scope, and in summary, the present disclosure should not be construed as limiting the present invention, and any modifications, equivalent substitutions and improvements made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An insertion redundancy through hole optimizing method is characterized in that:
providing a physical design tool and typical physical design results, respectively inserting the typical physical design results by using different types of redundant through holes, and obtaining a corresponding first physical design result for each type of redundant through holes;
providing a calculation photoetching tool to obtain weights of different positions of each redundant through hole in the insertion typical physical design result according to the first physical design result;
aiming at different positions of the same typical physical design result, respectively selecting one redundant through hole with the largest weight for insertion to obtain a second physical design result;
and optimizing and detecting a second physical design result by using a calculation photoetching tool, detecting and judging whether a preset problem occurs according to a photoetching rule, and taking the second physical design result and a redundant through hole inserted in a corresponding position as an optimization result if the preset problem does not occur.
2. The method of optimizing insertion of redundant vias of claim 1, wherein said providing a computational lithography tool to derive weights for each of the redundant vias at different locations in the insertion of typical physical design results based on the first physical design results comprises the steps of:
providing a calculation photoetching tool, and performing mask optimization on a first physical design result obtained by inserting each redundant through hole;
obtaining key indexes of the same redundant through hole, which influence the lithography rule detection result in the insertion of different positions of the first physical design result, according to the lithography rule detection result corresponding to the mask after the mask optimization;
and calculating weights of different positions of the corresponding types of redundant through holes in the inserted typical physical design according to the key indexes.
3. The method of claim 2, wherein the key indicator comprises a type of first lithography rule violation and a first frequency of a corresponding type.
4. A method of optimizing an inserted redundant via of claim 3, wherein the first lithography rule violation category comprises bridging and extrusion.
5. The method for optimizing an insertion redundancy via as in claim 4,
and adding the first frequencies corresponding to all the first photoetching rule violation categories in the key indexes to obtain weights of different positions of the redundant through holes after the redundant through holes are inserted into typical physical design results.
6. A method of optimizing an inserted redundant via as claimed in claim 3, wherein the predetermined problem is specifically an increase in the number of types of lithography rule violations corresponding to the key indicator.
7. The method for optimizing insertion of redundant vias according to claim 6, wherein said analyzing the second physical design result by using a computational lithography tool, determining whether a preset problem occurs comprises the steps of:
performing mask optimization on the second physical design result by using a calculation photoetching tool;
obtaining a second photoetching rule violation type and a second frequency of a corresponding type according to a photoetching rule detection result obtained after mask optimization;
comparing the second lithographic rule violation category with the first lithographic rule violation category, and comparing the first frequency of the corresponding lithographic rule category with the second frequency; if the second photoetching rule violation type is not larger than the second photoetching rule violation type and the second frequency is not larger than the first frequency, the preset problem does not occur; otherwise, the preset problem occurs.
8. The method of claim 7, wherein if a predetermined problem occurs, adding the increased number of photolithography rule violation categories and/or the increased frequency to the key indicator, and returning to providing a calculation photolithography tool to iterate to obtain the weighted positions of each of the redundant vias at different positions in the typical physical design result according to the first physical design result.
9. An insertion redundancy through-hole optimizing apparatus, characterized by comprising
A memory for storing a computer program and a second physical design result;
a processor for implementing the steps of a method for optimizing insertion of redundant vias as claimed in any of claims 1 to 8 when executing said computer program.
10. A storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of an insertion redundancy via optimizing method according to any one of claims 1 to 8.
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