CN117892666A - Digital circuit layout planning method and device, electronic equipment and storage medium - Google Patents
Digital circuit layout planning method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a digital circuit layout planning method, a digital circuit layout planning device, electronic equipment and a storage medium, which comprise the following steps: acquiring historical streaming data, and estimating area estimation information and shape estimation information of each macro unit in the digital circuit to be planned according to the historical streaming data and the function type of the macro unit in the digital circuit to be planned; carrying out initial layout on macro cells in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro cell by using a preset EDA tool to obtain an initial layout result of the digital circuit to be planned; and acquiring adjustment information, adjusting the initial layout result according to the adjustment information to obtain an adjustment layout result, and determining IO arrangement and lamp arrangement according to the adjustment layout result. By determining the technical scheme of IO arrangement and lamp arrangement according to the historical flow sheet data and the adjustment information, the planning of the digital circuit layout can be completed under the conditions that codes are incomplete and ports are not connected.
Description
Technical Field
The embodiment of the invention relates to the technical field of chip design, in particular to a digital circuit layout planning method, a digital circuit layout planning device, electronic equipment and a storage medium.
Background
Digital circuit design and layout planning are one of the important links of digital system design, and have important influence on the aspects of ensuring the performance, reliability, cost and the like of the digital system. Digital circuit design and layout planning refers to the process of designing and planning a digital circuit, including detailed analysis and design of logic functions, connection relationships, timing relationships, etc. of the circuit, and planning of layout and connection lines of circuit elements.
At present, a specific digital circuit design and layout planning often need to analyze, compare and calculate a plurality of arrangement versions by EDA software, and the whole process is time-consuming, labor-consuming and tedious and error-prone. Under the conditions of incomplete codes and incomplete port butt joint, digital circuit design and layout planning cannot be accurately completed.
Disclosure of Invention
The embodiment of the invention provides a digital circuit layout planning method, a digital circuit layout planning device, electronic equipment and a storage medium, which realize digital circuit design and layout planning under the condition that codes are incomplete and ports are not connected.
According to an aspect of the present invention, there is provided a digital circuit layout planning method, comprising:
Acquiring historical streaming data, and estimating area estimation information and shape estimation information of each macro unit in the digital circuit to be planned according to the historical streaming data and the function type of the macro unit in the digital circuit to be planned;
Carrying out initial layout on macro cells in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro cell by using a preset EDA tool to obtain an initial layout result of the digital circuit to be planned;
And acquiring adjustment information, adjusting the initial layout result according to the adjustment information to obtain an adjustment layout result, and determining IO arrangement and lamp arrangement according to the adjustment layout result.
According to another aspect of the invention, a digital circuit layout arrangement comprises:
The estimating module is used for acquiring historical streaming data and estimating area estimating information and shape estimating information of each macro unit in the digital circuit to be planned according to the historical streaming data and the function type of the macro unit in the digital circuit to be planned;
The layout module is used for carrying out initial layout on macro cells in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro cell by using a preset EDA tool to obtain an initial layout result of the digital circuit to be planned;
The adjusting module is used for acquiring the adjusting information, adjusting the initial layout result according to the adjusting information to obtain an adjusting layout result, and determining IO arrangement and lamp arrangement according to the adjusting layout result.
According to another aspect of the present invention, there is provided an electronic apparatus including:
At least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the digital circuit layout method of any of the embodiments of the present invention.
According to another aspect of the invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to perform a digital circuit layout method according to any of the embodiments of the invention.
According to the embodiment of the invention, the area estimation information and the shape estimation information of each macro-unit in the digital circuit to be planned are estimated through the historical streaming data, the EDA tool and the adjustment information are utilized to adjust the estimation result, the adjustment layout result is obtained, and finally, the technical scheme of IO arrangement and bulb arrangement is determined according to the adjustment layout result, so that the planning of the digital circuit layout can be completed under the conditions that codes are incomplete and ports are not connected.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a digital circuit layout method according to a first embodiment of the present invention;
FIG. 2 is a flow chart of another digital circuit layout method according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a digital circuit layout apparatus according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a flowchart of a digital circuit layout planning method according to an embodiment of the present invention, where the method may be applied to the case of planning a digital circuit layout, and the method may be implemented by a digital circuit layout planning apparatus, where the apparatus may be implemented by software and/or hardware, and may be generally integrated in an electronic device, where the electronic device may be a terminal device or a server device, and is used with a client for completing digital circuit layout. Accordingly, as shown in fig. 2, the method includes the following operations:
S110, acquiring historical streaming data, and estimating area estimation information and shape estimation information of each macro unit in the digital circuit to be planned according to the historical streaming data and the function type of the macro unit in the digital circuit to be planned.
The historical flow sheet data can be data of historical digital circuit layout planning, and comprises historical macro cell function types, and historical area information and historical shape information corresponding to the historical macro cell types. The data can be from experimental data in a company or from a public data set, and the method for acquiring the historical streaming data is not particularly limited in the embodiment of the invention.
In digital circuit layout planning, historical slice data may be used to predict the area and shape of each macro-cell in the digital circuit to be planned. Specifically, the area estimation information and the shape estimation information of each macro unit in the digital circuit to be planned can be estimated according to the historical area information and the historical shape information corresponding to each macro unit type in the historical streaming data.
The macro unit refers to a logic unit in a chip, and is generally composed of a plurality of logic gates, registers, clocks and the like, and has certain computing and storage capabilities. The device can perform logic operation, data storage, state control and other operations according to different input signals, so that specific functions are realized. The functional types of the macro-units may be the functional types of the macro-units in the digital circuit to be planned currently, which refers to the functions or roles the macro-units implement in the digital circuit, and the macro-units may be categorized into a plurality of different functional types, such as combinational logic macro-units, sequential logic macro-units, etc. During the manufacturing process, metal interconnection lines between each predefined unit need to be constructed, and different connection modes can realize different functions at a higher logic level.
After macro units and corresponding data types in the historical data are obtained, whether the macro units are common macro units or key macro units can be defined based on the number, the area and the placement difficulty of the macro unit instantiations, for example, a chip core is difficult to collect in time sequence and has high area occupation ratio, and the macro units are instantiated four times or more, so that the chip core is listed as the key macro units, for example, a high-speed interface, the macro units are large in number and have high area occupation ratio and are also listed as the key macro units, and macro units which have decisive influence on the chip area evaluation can be listed as the key macro units.
The area prediction information may be area information of each macro cell in the digital circuit to be planned according to historical streaming data and the function type of the macro cell in the digital circuit to be planned currently. The shape estimation information can be the shape information of each macro unit in the digital circuit to be planned according to the historical streaming data and the function type of the macro unit in the current digital circuit to be planned.
After the history area information and the history shape information corresponding to each history macro unit type are obtained, the method further comprises the following steps:
And converting the historical area information and the historical shape information corresponding to each historical macro-unit type into a target data structure.
The target data structure may be a data structure that can be identified by the obtained tool after processing the obtained area information and shape information of each macro unit through a part of functions or scripting language of the EDA tool or by combining the EDA tool and the scripting language, and may be edited into EDA tool identifiable data after obtaining the data structure, where the data includes macro units but does not include interconnection information.
Optionally, the converting the historical area information and the historical shape information corresponding to each historical macro-unit type into the target data structure may be converting the historical area information and the historical shape information corresponding to each historical macro-unit type into the target data structure by means of a part of functions of the EDA tool.
Optionally, the converting the historical area information and the historical shape information corresponding to each historical macro-unit type into the target data structure may be converting the historical area information and the historical shape information corresponding to each historical macro-unit type into the target data structure by means of a part of functions of the EDA tool.
Optionally, the historical area information and the historical shape information corresponding to each historical macro unit type are converted into the target data structure, and the historical area information and the historical shape information corresponding to each historical macro unit type can be converted into the target data structure by combining an EDA tool and a scripting language.
The conversion of the data structure is to convert the area information and the shape information of the macro unit into a data structure which can be identified by a tool, and edit the data which contains the macro unit but does not contain the interconnection information into EDA tool identifiable data. The required data can be imported into an EDA tool for area evaluation under the condition that the code is incomplete and the port is not docked.
Specifically, the area estimation information and the shape estimation information of each macro unit in the digital circuit to be planned are estimated according to the historical streaming data and the function type of the macro unit in the digital circuit to be planned currently, and the method comprises the following steps:
For any target macro unit in the digital circuit to be planned, screening out a target historical macro unit function type consistent with the function type of the target macro unit from the historical macro unit function types;
and determining the area estimated information and the shape estimated information of the target macro unit according to the historical area information and the historical shape information corresponding to the function type of the target historical macro unit.
The target macro-cell may be a key macro-cell in the digital circuit to be planned, which requires prediction of area and shape. The macro units are objects which are required to be used by a designer when planning a digital circuit, similar target historical macro unit function types are screened out from the historical macro unit function types according to the function types, and the area estimated information and the shape estimated information of the macro units are determined according to the corresponding historical area information and the historical shape information. By determining the area estimation information and the shape estimation information of the target macro unit, the design of the digital circuit to be planned can be completed better.
Specifically, for any target macro unit in the digital circuit to be planned, the target historical macro unit function type consistent with the function type of the target macro unit is screened out from the historical macro unit function types, and the macro unit type with the same or similar function can be searched out from the historical macro unit function types according to the function type of the target macro unit. For example, if the target macrocell is a logical operation macrocell, then all logical operation macrocell types historically can be filtered out and the type of historic macrocell closest to the functional type of the target macrocell can be selected. These historical macrocell types may be data obtained from previous flowsheet experiments or data obtained from published datasets or resource libraries.
Specifically, determining the area estimation information and the shape estimation information of the target macro unit according to the historical area information and the historical shape information corresponding to the function type of the target historical macro unit includes:
determining the average area of the historical area information corresponding to the functional type of the target historical macro unit as the area estimated information of the target macro unit;
And determining the historical shape information with the largest number of the same shapes in the historical shape information corresponding to the target historical macro unit function type as shape estimated information of the target macro unit.
Specifically, the average area of the historical area information corresponding to the functional type of the target historical macro unit is determined as the area estimation information of the target macro unit, that is, after the target macro unit is determined, the area information of all macro units corresponding to the functional type of the historical macro unit corresponding to the target macro unit is searched in the historical streaming data, statistics is performed on the searched area information, the average value of the area information is calculated, and the average value is used as the area estimation information of the target macro unit. For example, assuming that there is a historical slice data table containing 100 historical macro cell function types, in which 10 macro cells are the same as the target macro cell function type, the areas of the 10 macro cells may be added and then divided by 10 to obtain the estimated information of the target macro cell. For example, if the area addition result of the 10 target macro cells is 120, the area estimation information 12 of the target macro cells may be obtained by dividing 120 by 10. By determining the average area of the historical area information as the area estimation information of the target macro unit, the area information of the target macro unit can be accurately predicted.
Optionally, other statistics, such as median, standard deviation, etc., may be calculated as needed to better evaluate accuracy and reliability of the area prediction information of the target macro-cell.
Specifically, the historical shape information with the largest number of the same shapes is indicated in the historical shape information corresponding to the function type of the target historical macro unit, and the shape estimation information of the target macro unit is determined, which may be that after the target macro unit is determined, the shape information of all macro units corresponding to the function type of the historical macro unit corresponding to the target macro unit is searched in the historical streaming data, statistics is performed on the searched shape information, frequency information of occurrence of each shape is obtained, and the macro unit shape with the largest frequency of occurrence is used as the shape estimation information of the target macro unit. For example, assume a table containing 10 historical macrocell function types, each macrocell type corresponding to a shape information including a rectangle, a circle, a triangle, and the like. Statistics of these shape information shows that 6 macro cells have rectangular shapes, 2 macro cells have circular shapes, and 2 macro cells have triangular shapes. Then the rectangle can be used as shape estimate information for the target macro-cell because the rectangle is the most numerous historical shape information. By determining the historical shape information with the largest number of the same shapes as the shape estimation information of the target macro unit, the shape information of the target macro unit can be accurately predicted.
S120, carrying out initial layout on macro cells in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro cell by using a preset EDA tool, and obtaining an initial layout result of the digital circuit to be planned.
The EDA tool refers to an automatic layout and wiring tool for digital back-end physical implementation, such as an EDA tool like icc2 innovus. The preset EDA tool may be a preset computer aided design software tool when electronic design automation is performed, and a technician may select an appropriate tool according to needs.
The initial layout result may be an initial position and layout of each macro cell in the circuit, which are determined according to the area estimation information and the shape estimation information of the macro cell when the digital circuit is laid out.
Specifically, the preset EDA tool is utilized to perform initial layout on macro units in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro unit, so that an initial layout result of the digital circuit to be planned is obtained, which can be an EDA tool preset by a user or a technician is loaded, the digital circuit to be planned is imported into the EDA tool according to the guide and the requirement of the used EDA tool, and the layout tool in the EDA tool is used to perform initial layout on macro units in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro unit. And determining the relative position between macro cells by using the area estimation information, and adjusting the layout of elements in the macro cells by using the shape estimation information. After the preliminary layout is completed, the initial layout results are verified and checked using the EDA tool's functionality to ensure that the layout is reasonable, meets the design requirements, and meets the relevant standards.
S130, acquiring adjustment information, adjusting the initial layout result according to the adjustment information to obtain an adjustment layout result, and determining IO arrangement and lamp arrangement according to the adjustment layout result.
The adjustment information may be information provided by a circuit designer, a simulation result, a layout and wiring tool, or other related tools, and may be a basis for adjusting the initial layout result. Such information may include information on connection relationships between macro-cells, signal routing, power consumption, etc., for optimizing performance and implementation efficiency of the digital circuit. The adjustment information may also be feedback information regarding circuit performance, such as signal propagation delay, signal integrity issues, etc. But also requirements and limitation information about the circuit implementation, such as available chip area, power consumption limitations, etc. The adjustment information is used to help the layout engineer make corresponding adjustments during the layout process to achieve better circuit performance and implementation.
The adjustment layout result may be a result obtained by adjusting the initial layout result according to the acquired adjustment information. These adjustments include rearranging the locations of macro-cells, adjusting the layout of components within macro-cells, optimizing signal routing, etc., to optimize the performance and implementation efficiency of the digital circuit.
Specifically, obtaining adjustment information, and adjusting an initial layout result according to the adjustment information to obtain an adjustment layout result, including:
Acquiring position adjustment information of each macro unit, and adjusting the position of each macro unit according to the position adjustment information;
And acquiring shape adjustment information of each macro unit according to the area minimization principle, and adjusting the shape of each macro unit according to the shape adjustment information to obtain an adjustment layout result.
The position adjustment information may be specific placement position information of each macro unit on the chip in the chip design. This includes detailed information of coordinates, direction, and rotation angle of the macro-cell. The position adjustment information is used for adjusting the connection relation between macro units, so that the data flow is smoother, and the performance of the chip is improved.
The area minimization principle can be that the area of the chip is reduced as much as possible by adjusting the position and the shape of the macro-unit in the chip design. Because the larger the area of the chip is, the higher the manufacturing cost is, and meanwhile, the problems of signal interference, power consumption and the like are increased. The area of the chip is reduced by utilizing the area minimization principle, so that the manufacturing cost can be effectively reduced, and the chip performance is improved.
The shape adjustment information may be information for fine-tuning the shape and size of the macro cell in the chip design. Such information may include the shape of the border of the macro-cell, the layout of the internal components, the relative position with the neighboring macro-cells, etc. The shapes of the macro units are adjusted, so that the layout and the data flow path of the chip can be optimized. For example, a macro-cell that is too long and narrow in shape may cause a slow signal transmission speed or an increased interference problem. At this time, the macro-cell may be shaped to more closely approximate a square or rectangle to improve signal transmission performance and reduce interference.
The specific adjustment process may be that macro units involved in unreasonable data flow direction in the initial layout result and flow direction rationalization strategies are obtained, then after the positions of the macro units are adjusted according to the flow direction rationalization strategies, the shapes of the macro units are adjusted on the basis of fixed positions, so that the chip area is minimized.
Specifically, the position adjustment information of each macro unit is obtained, and the position of each macro unit is adjusted according to the position adjustment information, which may be that the initial position, direction, size and other information of each macro unit are obtained from the chip design software or the database, and the macro unit needing to be adjusted is identified by analyzing factors such as data flow paths, signal interference, power distribution and the like in the initial layout result. The macro cells needing to be adjusted in position can be macro cells involved in unreasonable data flow in the initial layout result. And then, according to the position adjustment information provided by the chip design software or the database, acquiring the detailed information such as the target position, the target direction and the target size of each macro unit. The detailed information such as the target position, direction and size can be manually input by a user or calculated by using an automatic tool. And performing fine adjustment on the position of the macro unit to be adjusted according to the acquired position adjustment information. It should be noted that, in the embodiment of the present invention, the position adjustment information may be manually input by a user, may be calculated by using an automation tool, or may be obtained from position adjustment information of a history macro unit, which is not limited herein.
Specifically, the shape adjustment information of each macro unit is obtained according to the area minimization principle, and the shape of each macro unit is adjusted according to the shape adjustment information to obtain an adjustment layout result, which may be obtained by obtaining an initial macro unit layout result from chip design software or a database after adjusting the position of each macro unit according to the position adjustment information of each macro unit, determining a corresponding area minimization principle according to the initial shape, size and position of each macro unit in the initial layout result, and determining the shape adjustment information of each macro unit according to the area minimization principle, so as to minimize the area of the chip, where the area minimization principle may be obtained by calculating by using an automation machine according to the initial shape, size and position of each macro unit, or may be obtained by querying the shape, size and position of each macro unit in historical data, or may be obtained by autonomously designing the initial shape, size and position of each macro unit, and layout information. After the shape adjustment information of each macro unit is determined, the internal components of each macro unit are subjected to fine adjustment on shapes such as movement, rotation and scaling according to the obtained shape adjustment information for each macro unit, so that the initial layout result is minimized, and an adjustment layout result is obtained.
According to the technical scheme, after any target macro unit in a digital circuit to be planned is determined, the target historical macro unit function type consistent with the target macro unit function type is screened out from the historical macro unit function types, the area estimated information and the shape estimated information of the target macro unit are determined according to the historical area information and the historical shape information corresponding to the target historical macro unit function type, then the historical area information and the historical shape information corresponding to each historical macro unit type are converted into a target data structure, the area estimated information and the shape estimated information of the target macro unit can be calculated under the condition that data are missing, finally the positions of each macro unit are adjusted according to the position adjustment information, the shape adjustment information of each macro unit is obtained according to the area minimization principle, the shapes of each macro unit are adjusted according to the shape adjustment information, the adjustment layout result is obtained, and the chip area can be minimized on the premise that reasonable arrangement of each macro unit is ensured.
Example two
Fig. 2 is a flowchart of a digital circuit layout method according to a second embodiment of the present invention, where the scheme of determining the IO arrangement and the lamp arrangement according to the adjustment layout result is specifically defined, and is not described in detail in the embodiment of the present invention, but the scheme is described in the foregoing embodiment, for determining the logic level data of any macro cell in the adjustment layout result, adjusting the logic level data of the macro cell according to the implementation difficulty reduction policy, and determining the IO arrangement and the lamp arrangement according to the adjustment layout result, before determining the IO arrangement and the lamp arrangement according to the adjustment layout result. As shown in fig. 2, the method includes:
s210, acquiring historical streaming data, and estimating area estimation information and shape estimation information of each macro unit in the digital circuit to be planned according to the historical streaming data and the function type of the macro unit in the digital circuit to be planned.
S220, carrying out initial layout on macro cells in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro cell by using a preset EDA tool, and obtaining an initial layout result of the digital circuit to be planned.
S230, acquiring adjustment information, and adjusting the initial layout result according to the adjustment information to obtain an adjustment layout result.
S240, for any macro unit in the adjustment layout result, determining logic level data of the macro unit, and adjusting the logic level data of the macro unit according to the implementation difficulty reduction strategy.
The logic level data may be the number of logic units for adjusting any macro unit in the layout result. The number of logic units of the macro unit refers to the number of predefined logic function implementation units consisting of flip-flops, arithmetic logic units, hardware registers and the like which form the macro unit and have higher abstraction level relative to the logic gates. These logic cells are arranged on the silicon as a whole as a macro cell. During the manufacturing process, metal interconnect lines between the individual predefined cells need to be built to achieve higher logic level functionality. For example, the number of the logic units of any macro unit can be 200 ten thousand, 300 ten thousand, 310 ten thousand, etc., wherein the number of the logic units of any macro unit is positively correlated with the physical implementation time, and the more the number is, the longer the time is. This increases the time and complexity of physical implementation because the greater the number of logic cells, the greater the connections and wiring that need to be designed and manufactured. In addition, more logic cells also require more space to place on the silicon wafer, which can also result in more time consuming and difficult manufacturing processes. Therefore, in designing an electronic device, it is required to reduce the number of logic units of macro units as much as possible while satisfying functional requirements in order to shorten the time for physical implementation and improve efficiency.
The implementation of the difficulty reduction strategy may be to judge whether the number of the logic units is greater than a preset threshold, for example, the preset threshold may be set to 300 ten thousand, if the number of the logic units in any macro unit is greater than 300 ten thousand, a warning for reducing the number is prompted, and new logic level data of the macro unit is obtained and replaced; if the number is less than 300 ten thousand, no adjustment is performed; the implementation difficulty reduction strategy may also be to determine the physical implementation time of the macro unit according to the logic level data, where the physical implementation time of the macro unit may be determined by a corresponding relation between the number of units and the implementation time in advance, or may be determined through simulation by simulation software, if the time is greater than 1 week, a warning of reducing the number is prompted, new logic level data of the macro unit is obtained and replaced, and if the time is less than 1 week, no adjustment is performed. Wherein the new logical hierarchy data may be provided by a design developer.
Specifically, for any macro unit in the adjustment layout result, determining logic level data of the macro unit, adjusting the logic level data of the macro unit according to the implementation difficulty reduction strategy, that is, extracting the number of logic units of each macro unit from the adjustment layout result, comparing the number of logic units of the macro unit with a preset threshold value, if the number of logic units of the macro unit is greater than the preset threshold value, generating a warning for prompting the reduction number, further prompting a user to optimize the logic level data of the macro unit, after acquiring the prompting information, acquiring new logic level data provided by a design developer according to the difficulty reduction strategy, and then adjusting the logic level data of the macro unit according to the new logic level data to obtain the adjusted macro unit.
S250, determining initial IO arrangement according to the layout adjustment result, and adjusting the initial IO arrangement according to IO arrangement defects fed back by the sealing and measuring party to obtain IO arrangement.
The initial IO arrangement may refer to an IO distribution of each macro cell determined after the logic level data of the macro cell is adjusted according to the new logic level data to obtain an adjustment layout result. The IO arrangement refers to the distribution of input/output ports or pins on an integrated circuit, a chip and the like, and comprises the positions, the shapes, the sizes, the numbers and the like of the input/output ports or pins.
The IO arrangement defect fed back by the sealing and measuring party can be a problem or a fault caused by unreasonable IO arrangement or defect in the process of sealing and measuring each macro unit. IO arrangement defects may include problems such as poor signal quality, unstable connection, and high manufacturing difficulty.
Specifically, the initial IO arrangement is determined according to the layout adjustment result, the initial IO arrangement is adjusted according to the IO arrangement defect fed back by the sealing and measuring party, and IO arrangement is obtained, namely, after layout adjustment of the macro units is completed, the initial IO arrangement condition of the macro units is determined according to design rules and requirements, then the initial IO arrangement condition of the macro units is provided for the sealing and measuring party, and after receiving the initial IO arrangement condition of each macro unit, the sealing and measuring party feeds back the problem or defect related to the IO arrangement of the macro units according to the problems of poor signal quality, unstable connection, high manufacturing difficulty and the like caused by the initial IO arrangement condition of each macro unit. After receiving the problem of the feedback of the sealing party, the technician can analyze and evaluate the problem to formulate a corresponding adjustment scheme. According to the determined adjustment scheme, the positions, the adjustment shapes, the change sizes and the like of the ports or pins of the initial IO arrangement are adjusted, so that the problem of feedback of a sealing and measuring party is solved, the problems of signal quality improvement, connection stability enhancement, manufacturing difficulty reduction and the like are solved, and a final IO arrangement result is obtained.
S260, determining initial bulb distribution according to the adjustment IO arrangement, and adjusting the initial bulb arrangement according to the bulb arrangement defect fed back by the sealing and measuring party to obtain the bulb arrangement.
Initial bulb distribution: in flip chips, the initial bump distribution refers to the initial arrangement of metal particles (solder balls) at the uppermost layer of the macro-cell (chip) that are connected to external circuits or components. These solder balls serve as connection points to be connected to an external circuit or element through an IO (input/output) port. To ensure stability of the connection, the initial bump distribution needs to be carefully designed to ensure that the solder balls are accurately aligned with the corresponding IO ports.
Bulb arrangement: the bump arrangement refers to the distribution of the positions of solder balls (bumps) on the macro-cells, including their positions, shapes, sizes, etc. This distribution needs to take into account the efficiency and stability of the signal transmission, as well as the difficulty and cost of manufacture. Reasonable bump arrangement can ensure correct transmission of signals, and reduce problems and difficulties in the manufacturing process.
Sealing the bulb arrangement defect fed back by the measuring party: during manufacturing or packaging, the packaging plant may provide feedback indicating whether the provided packaging scheme is viable. If there is a problem or defect, the packaging plant will tell which specific aspects will lead to packaging failure. For example, which signals may not be derived or the wiring is too complex to ensure signal quality, which signals may have serious crosstalk between them to cause signal failure, and certain power distributions may be unreasonable to cause information such as reduced cell integrity. Such feedback information is important to the designer, helping them improve the design and avoid similar problems.
Specifically, the initial bulb distribution is determined according to the adjustment IO arrangement, the initial bulb arrangement is adjusted according to the bulb arrangement defect fed back by the sealing and measuring party, the bulb arrangement is obtained, the positions of the IO and the bulb can be adjusted according to the performance requirement and the manufacturing requirement of the electronic equipment, so that the efficiency and the stability of signal transmission are ensured, and the manufacturing difficulty is reduced. And determining initial bump distribution, namely initial arrangement of metal particles of solder balls (bumps) connected with external circuits or elements at the uppermost layer of the macro unit (chip) according to the determined IO arrangement. During the encapsulation process, if there are problems or defects, the encapsulation factory will tell which specific aspects will lead to the failure of the encapsulation. After receiving the feedback information, determining which problems are to be solved by adjusting the bulb arrangement according to the feedback information, and formulating a corresponding adjustment scheme according to the nature of the problems. And according to the adjustment scheme, adjusting the initial bulb arrangement. Finally, verifying and testing the adjusted bulb arrangement, ensuring that the adjusted bulb arrangement can solve the problem of feedback of a sealing and measuring party and meet the design requirement. If the validation test results meet the requirements, then the adjusted lamp arrangement can be determined to be the final arrangement.
According to the technical scheme provided by the embodiment of the invention, after the adjustment layout result is obtained, any macro cell in the adjustment layout result is subjected to logic level data of the macro cell is determined, the logic level data of the macro cell is adjusted according to the implementation difficulty reduction strategy, the macro cell is processed through the difficulty reduction strategy, the number of the logic cells can be enabled to reach the minimum value on the basis that the chip can be ensured to operate wholly, the physical implementation time of the macro cell is reduced, and the designed chip is more efficient in processing the data. After the layout adjustment result is determined, the initial IO arrangement can be fed back to the sealing and measuring party, and the initial IO arrangement is adjusted according to IO arrangement defects fed back by the sealing and measuring party, so that IO arrangement is obtained; and determining initial bulb distribution according to the adjustment IO arrangement, and adjusting the initial bulb arrangement according to bulb arrangement defects fed back by a sealing and measuring party to obtain the bulb arrangement, so that the planning result of the digital circuit layout is more reasonable, and further the sealing and measuring problem encountered in the follow-up sealing and measuring according to the planning result of the digital circuit layout is avoided.
Example III
Fig. 3 is a schematic diagram of a digital circuit layout apparatus according to a third embodiment of the present invention, where, as shown in fig. 3, the apparatus includes: an estimation module 310, a layout module 320, and an adjustment module 330, wherein:
The estimating module 310 is configured to obtain historical slice data, and estimate area estimating information and shape estimating information of each macro unit in the digital circuit to be planned according to the historical slice data and the function type of the macro unit in the digital circuit to be planned.
The historical streaming data comprises historical macro unit function types, and historical area information and historical shape information corresponding to each historical macro unit type.
The layout module 320 is configured to perform initial layout on macro cells in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro cell by using a preset EDA tool, so as to obtain an initial layout result of the digital circuit to be planned.
The adjustment module 330 is configured to obtain adjustment information, adjust the initial layout result according to the adjustment information, obtain an adjustment layout result, and determine the IO arrangement and the bump arrangement according to the adjustment layout result.
Further, the estimation module 310 is specifically configured to:
For any target macro unit in the digital circuit to be planned, screening out a target historical macro unit function type consistent with the function type of the target macro unit from the historical macro unit function types;
and determining the area estimated information and the shape estimated information of the target macro unit according to the historical area information and the historical shape information corresponding to the function type of the target historical macro unit.
Further, the estimation module 310 is specifically further configured to:
determining the average area of the historical area information corresponding to the functional type of the target historical macro unit as the area estimated information of the target macro unit;
And determining the historical shape information with the largest number of the same shapes in the historical shape information corresponding to the target historical macro unit function type as shape estimated information of the target macro unit.
Further, the adjusting module 330 is specifically configured to:
Acquiring position adjustment information of each macro unit, and adjusting the position of each macro unit according to the position adjustment information;
And acquiring shape adjustment information of each macro unit according to the area minimization principle, and adjusting the shape of each macro unit according to the shape adjustment information to obtain an adjustment layout result.
Further, the adjusting module 330 is specifically further configured to:
Determining initial IO arrangement according to the adjustment layout result, and adjusting the initial IO arrangement according to IO arrangement defects fed back by the sealing and measuring party to obtain IO arrangement;
and determining initial bulb distribution according to the adjustment IO arrangement, and adjusting the initial bulb arrangement according to the bulb arrangement defect fed back by the sealing and measuring party to obtain the bulb arrangement.
Further, the digital circuit layout device further comprises:
And the target data structure generation module is used for converting the historical area information and the historical shape information corresponding to each historical macro unit type into a target data structure.
Further, the digital circuit layout device further comprises:
The logic level data adjusting module is used for determining logic level data of the macro unit for any macro unit in the adjustment layout result before determining IO arrangement and bulb arrangement according to the adjustment layout result, and adjusting the logic level data of the macro unit according to the implementation difficulty reduction strategy.
The digital circuit layout planning device can execute the digital circuit layout planning method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment may be referred to the digital circuit layout method provided in any embodiment of the present invention.
Since the above-described digital circuit layout apparatus is an apparatus capable of executing the digital circuit layout method according to the embodiment of the present application, those skilled in the art will be able to understand the specific implementation of the digital circuit layout apparatus according to the embodiment of the present application and various modifications thereof based on the digital circuit layout method according to the embodiment of the present application, so how the digital circuit layout apparatus implements the digital circuit layout method according to the embodiment of the present application will not be described in detail herein. The apparatus used by those skilled in the art to implement the digital circuit layout method in the embodiments of the present application is within the scope of the present application.
Example IV
Fig. 4 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a digital circuit layout method.
In some embodiments, the digital circuit layout method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the memory unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. One or more of the steps of the digital circuit layout method described above may be performed when the computer program is loaded into the RAM 13 and executed by the processor 11. Alternatively, in other embodiments, the processor 11 may be configured to perform the digital circuit layout method in any other suitable way (e.g. by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
Claims (10)
1. A digital circuit layout method, the method comprising:
Acquiring historical flow sheet data, and estimating area estimation information and shape estimation information of each macro unit in a digital circuit to be planned according to the historical flow sheet data and the function type of the macro unit in the current digital circuit to be planned;
performing initial layout on macro cells in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro cell by using a preset EDA tool to obtain an initial layout result of the digital circuit to be planned;
acquiring adjustment information, adjusting the initial layout result according to the adjustment information to obtain an adjustment layout result, and determining IO arrangement and lamp arrangement according to the adjustment layout result.
2. The method of claim 1, wherein the historical slice data includes historical macro cell function types and historical area information and historical shape information corresponding to each of the historical macro cell types;
the estimating area estimation information and shape estimation information of each macro unit in the digital circuit to be planned according to the historical streaming data and the function type of the macro unit in the digital circuit to be planned currently comprises the following steps:
for any target macro unit in the digital circuit to be planned, screening out a target historical macro unit function type consistent with the function type of the target macro unit from the historical macro unit function types;
And determining the area estimated information and the shape estimated information of the target macro unit according to the historical area information and the historical shape information corresponding to the function type of the target historical macro unit.
3. The method of claim 2, wherein determining the area estimation information and the shape estimation information of the target macro-cell according to the historical area information and the historical shape information corresponding to the target historical macro-cell function type comprises:
determining the average area of the historical area information corresponding to the functional type of the target historical macro unit as the area estimated information of the target macro unit;
And determining the historical shape information with the largest number of the same shapes in the historical shape information corresponding to the target historical macro unit function type as the shape estimated information of the target macro unit.
4. A method according to any one of claims 1 to 3, wherein the method further comprises:
and converting the historical area information and the historical shape information corresponding to each historical macro-unit type into a target data structure.
5. The method of claim 1, wherein the obtaining adjustment information and adjusting the initial layout result according to the adjustment information to obtain an adjusted layout result comprises:
acquiring position adjustment information of each macro unit, and adjusting the position of each macro unit according to the position adjustment information;
And acquiring shape adjustment information of each macro unit according to an area minimization principle, and adjusting the shape of each macro unit according to the shape adjustment information to obtain an adjustment layout result.
6. The method according to claim 1 or 5, wherein before determining the IO arrangement and the lamp arrangement according to the adjustment layout result, the method further comprises:
And for any macro unit in the adjustment layout result, determining logic level data of the macro unit, and adjusting the logic level data of the macro unit according to the implementation difficulty reduction strategy.
7. The method of claim 1, wherein the determining the IO arrangement and the lamp arrangement according to the adjustment layout result comprises:
Determining initial IO arrangement according to the layout adjustment result, and adjusting the initial IO arrangement according to IO arrangement defects fed back by a sealing and measuring party to obtain IO arrangement;
and determining initial bulb distribution according to the adjustment IO arrangement, and adjusting the initial bulb arrangement according to the bulb arrangement defect fed back by the sealing and measuring party to obtain the bulb arrangement.
8. A digital circuit layout arrangement, the arrangement comprising:
The estimating module is used for acquiring historical streaming data and estimating the area estimating information and the shape estimating information of each macro unit in the digital circuit to be planned according to the historical streaming data and the function type of the macro unit in the current digital circuit to be planned;
the layout module is used for carrying out initial layout on macro cells in the digital circuit to be planned according to the area estimation information and the shape estimation information of each macro cell by using a preset EDA tool to obtain an initial layout result of the digital circuit to be planned;
the adjusting module is used for acquiring adjusting information, adjusting the initial layout result according to the adjusting information to obtain an adjusting layout result, and determining IO arrangement and dump arrangement according to the adjusting layout result.
9. An electronic device, comprising:
one or more processors;
Storage means for storing one or more programs,
The one or more programs, when executed by the one or more processors, cause the one or more processors to implement the digital circuit layout method of any of claims 1-7.
10. A storage medium having stored thereon a computer program, which when executed by a processor implements a digital circuit layout method according to any of claims 1-7.
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| CN118133764B (en) * | 2024-05-10 | 2024-07-05 | 深圳市电科星拓科技有限公司 | Macrocell placement method and related device |
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Inventor after: Cui Qian Inventor before: Ren Weili Inventor before: Cui Qian Inventor before: Zhou Fabiao |