CN117331884A - System chip design control method and device based on hardware encapsulation - Google Patents
System chip design control method and device based on hardware encapsulation Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Abstract
The embodiment of the specification provides a system chip design control method and device based on hardware encapsulation, which combines a hardware engine with a software engine in a correlated way, compatibly utilizes the advantages of the hardware engine and the software engine, has higher expansibility and flexibility, and is convenient for realizing design iteration optimization more efficiently. The method is applied to a soft and hard association engine device in a system chip design system, and comprises the following steps: receiving a task data packet forwarded by a work management engine in the system chip design system; performing initial transmission verification on the task data packet; determining the working mode of the soft and hard association engine in response to the passing of the initial transmission verification; generating a function interrupt event aiming at the task data packet in an interrupt working mode, and notifying a software engine connected with the soft and hard association engine; and in an event working mode, generating a hardware event according to the task data packet, arbitrating the hardware event and writing the hardware event into the work management engine.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a system chip design control method and device based on hardware encapsulation.
Background
A system on a chip (SoC) is an integrated circuit chip that integrates various modules of a circuit on a single substrate. The SoC has the functions of digital, simulation, mixed signal, general radio frequency signal processing and the like, can reduce the power consumption and reduce the occupied area of the chip. With the development of high-speed technology, more and more modules and more components are integrated on the same chip, and integrated circuits are coming into the SoC era.
Typically, a SoC is composed of software and hardware. The system chip design can be divided into software design work and hardware design work, and then the two works are combined to form a complete system. The hardware engineer uses hardware description languages such as VHDL or Verilog to design and construct a hardware engine, and based on the hardware circuit module, the information interaction of the circuit, such as an algorithm module and a functional module, is realized. The hardware engine runs faster and runs stably in parallel, but adopting the hardware engine requires long iterative computation, and the recalculation required for the later chip design modification will take a larger time penalty and implementation cost. The software engineer uses programming languages such as C or C++ to design and construct the software engine. The software engine is characterized by higher flexibility and lower cost. However, the software engine has no independent hardware and interface, needs to occupy certain CPU resources, is easily influenced by the stability of an operating system, and has relatively poor performance.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a system chip design system control device, a method, an electronic device, and a storage medium, which combine a hardware engine with a software engine, and compatibly utilize the advantages of both the hardware engine and the software engine, so that the system chip design system control device has higher expansibility and flexibility, and is convenient to implement design iterative optimization more efficiently.
In a first aspect, embodiments of the present disclosure provide a soft and hard association engine apparatus of a system-on-chip design system, including:
the system comprises a data packet reading module, a parity check module, an interrupt generation module, an aggregation module and an arbitration module;
the reading data packet module is used for acquiring data packets in the buffer FIFO queue through a register interface;
the parity check module is used for performing parity check on the data content of the data packet acquired by the reading data packet module;
the interrupt generation module is used for generating a functional interrupt and/or an error interrupt, wherein the priority of the error interrupt is higher than that of the functional interrupt;
the aggregation module is used for executing data aggregation on a plurality of data packets;
and the arbitration module is used for arbitrating hardware events of the hardware engine in the system chip design system in a polling mode.
In a second aspect, embodiments of the present disclosure further provide a system chip design control method based on hardware encapsulation, where the method is applied to the soft-hard correlation engine device in the system chip design system according to the first aspect; the method comprises the following steps:
receiving a task data packet forwarded by a work management engine in the system chip design system, wherein the task data packet comprises task data corresponding to system chip design business;
performing initial transmission verification on the task data packet to determine whether the task data packet is a legal data packet;
determining the working mode of the soft and hard association engine device in response to the passing of the initial transmission verification;
generating a function interrupt event for the task data packet in response to the soft and hard association engine device being in an interrupt working mode, and notifying a software engine connected with the soft and hard association engine device;
and responding to the event working mode of the soft and hard association engine device, generating a hardware event according to the task data packet, arbitrating the hardware event and writing the hardware event into the work management engine.
Embodiments of the present disclosure also provide an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the system-on-chip design control method based on the hardware package according to the second aspect when the program is executed.
The present specification embodiment also provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the system-on-chip design control method based on the hardware package according to the second aspect.
As can be seen from the above, the control device, method, electronic device and storage medium of the system-on-chip design system provided in the embodiments of the present disclosure have the following beneficial technical effects:
the software and hardware association engine device in the form of a hardware packaging structure is connected between the hardware engine and the software engine, and is accessed into the work management module of the system chip through the on-chip internet to receive and process the task data packet of the system chip, so that the task forwarding of the hardware engine is realized, and the software engine can be utilized for processing instead of the hardware engine when the hardware engine has a problem. The hardware engine and the software engine are combined in an associated mode, the advantages of the hardware engine and the software engine can be comprehensively utilized, the time, the cost, the power consumption, the hardware area and the like are considered, the exception can be rapidly processed, the expansibility and the flexibility are higher, and the design iteration optimization can be conveniently and efficiently realized.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be construed as limiting the invention in any way, in which:
fig. 1 shows a schematic structural diagram of a soft and hard association engine device in a system-on-chip design system according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a system-on-chip design control method based on hardware package according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram showing a communication connection manner of the soft and hard association engine in the system chip design control method based on hardware package according to the embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating a method for initial transmission verification in a system chip design control method based on hardware package according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram showing a workflow in an event operation mode in a system-on-chip design control method based on hardware package according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram showing the operation of the soft and hard correlation engine in the system chip design control method based on the hardware package according to the embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a system-on-chip design control electronic device based on a hardware package according to an embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
A system on a chip (SoC) is an integrated circuit chip that integrates various modules of a circuit on a single substrate. The SoC has the functions of digital, simulation, mixed signal, general radio frequency signal processing and the like, can reduce the power consumption and reduce the occupied area of the chip. With the development of high-speed technology, more and more modules and more components are integrated on the same chip, and integrated circuits are coming into the SoC era.
Typically, a SoC is composed of software and hardware. The system chip design can be divided into software design work and hardware design work, and then the two works are combined to form a complete system. The hardware engineer uses hardware description languages such as VHDL or Verilog to design and construct a hardware engine, and based on the hardware circuit module, the information interaction of the circuit, such as an algorithm module and a functional module, is realized. The hardware engine runs faster and runs stably in parallel, but adopting the hardware engine requires long iterative computation, and the recalculation required for the later chip design modification will take a larger time penalty and implementation cost. The software engineer uses programming languages such as C or C++ to design and construct the software engine. The software engine is characterized by higher flexibility and lower cost. However, the software engine has no independent hardware and interface, needs to occupy certain CPU resources, is easily influenced by the stability of an operating system, and has relatively poor performance.
Therefore, in SoC design, there is a conflict between the low cost goal and the high performance goal, and there is a conflict between the design iteration cycle and the design functional complexity.
In view of the above problems, an object of the embodiments of the present disclosure is to provide a system chip design control method based on hardware encapsulation, where a design hardware encapsulation structure is connected between a hardware engine and a software engine, and the task data packet of the system chip is received and processed by a work management module of an on-chip internet access system chip, so as to implement task forwarding of the hardware engine, and the task forwarding of the hardware engine can be processed by using the software engine instead when the hardware engine has a problem. The hardware engine and the software engine are combined in an associated mode, the advantages of the hardware engine and the software engine can be comprehensively utilized, the time, the cost, the power consumption, the hardware area and the like are considered, the exception can be rapidly processed, the expansibility and the flexibility are higher, and the design iteration optimization can be conveniently and efficiently realized.
In view of the above, embodiments of the present disclosure provide a soft-hard association engine device of a system-on-chip design system.
As shown in fig. 1, one or more alternative embodiments of the present disclosure provide a soft and hard association engine (SWEB, software engine bank) device of a system-on-chip design system, which includes a read packet module, a parity module, an interrupt generation module, an aggregation module, and an arbitration module.
And the reading data packet module is used for acquiring the data packet in the buffer FIFO queue through the register interface. The CPU in the software engine notifies the SWEB to read the task data packet forwarded from the work management engine through the write register. The SWEB reads the data packet from the corresponding buffer FIFO according to the trigger signal of the write register, and places the data packet in the register of the read data packet.
And the parity check module is used for performing parity check on the data content of the data packet acquired by the reading data packet module.
The interrupt generation module is used for generating functional interrupt and/or error interrupt, wherein the priority of the error interrupt is higher than that of the functional interrupt. The error interrupt includes eight, at which time the SWEB generates the interrupt notification software and updates the interrupt status register. (1) The hardware event buffer FIFO is full, but there are still hardware event writes. (2) The packet FIFO is full, but there is still a hardware event write; (3) a data packet parity error; (4) the packet FIFO is empty but still performing a read packet operation; (5) the number of data packets in the data packet FIFO exceeds the configuration depth; (6) a certain channel is not configured but still has data packet written; (7) the engine ID of the channel is not matched with the engine ID check in the data packet; (8) the AXI bus returns an error response.
The aggregation module is used for executing data aggregation on a plurality of data packets. The aggregation module starts timing and counting from the first data packet, when the time reaches the configured time or the number of the data packets reaches the preset number, the aggregation module triggers the data packet aggregation and then notifies the software engine.
And the arbitration module is used for arbitrating the hardware event in a polling mode. For a certain software engine, there may be a next packet write during the arbitration wait, so a buffer FIFO is also required for the corresponding hardware event. I.e. the hardware event buffer FIFO is used to buffer the next packet in the process of waiting for arbitration, an erroneous interrupt is triggered when the hardware event buffer FIFO is full. Each hardware event includes information of an engine ID and FIFO load.
The software and hardware association engine device is arranged between the hardware engine and the software engine, and is connected with the work management module of the system chip through the on-chip internet to receive and process the task data packet of the system chip, so that the task forwarding of the hardware engine is realized, and the software engine can be utilized for processing instead of the hardware engine when the hardware engine has a problem.
Based on the same purpose, the embodiment of the specification also provides a system chip design control method based on hardware encapsulation, and the method is applied to the soft and hard association engine device.
As shown in fig. 2, one or more alternative embodiments of the present disclosure provide a system chip design control method based on hardware encapsulation, including:
s1: and receiving a task data packet forwarded by a work management engine in the system chip design system, wherein the task data packet comprises task data corresponding to system chip design business.
As shown in fig. 3, the soft and hard association engine SWEB may be connected with a software engine (CPU) and a hardware engine (e.g. an IO controller) together, and cooperate to form a software and hardware module. One typical application scenario for the software and hardware modules is to use a CPU for IO co-processing. The SWEB is responsible for connecting the software and hardware modules to the network on chip, and the work management engine can issue data packets to the software and hardware modules and notify the CPU to process through interrupt response or hardware event queues after receiving the data packets.
In the software and hardware module, the task data packet can be regarded as a task list for completing a task by a certain engine, and all necessary information for completing the task is covered. Depending on the hardware engine type, the packet size may be 16B, 32B,48B …, up to 128B. The CPU completes the defined engine task by operating the hardware module bound thereto and returns a "complete" and "enqueue" message for the next packet to the work management engine.
When the state of a certain hardware engine in the circuit is abnormal, the software and hardware module processes the data packet, and the abnormal recovery and recording of the hardware engine are completed.
The soft and hard association engine SWEB can also be connected with the CPU to form a universal module, and mainly realizes the software engine of a pure software algorithm class. The SWEB is responsible for accessing the network on chip, and the work management engine can issue a task data packet to the SWEB and notify the CPU to process through an interrupt or a hardware event queue after the SWEB receives the task data packet. After the CPU completes the designated engine task, a 'complete' and 'enqueue' message of the next data packet is returned to the work management engine.
S2: and carrying out initial transmission check on the task data packet to determine whether the task data packet is a legal data packet.
After receiving the data packet from the work management engine, the soft and hard association engine may first perform an initial transmission check on the data packet to ensure validity of the received data packet.
As shown in fig. 4, in a system chip design control method based on hardware encapsulation provided in one or more alternative embodiments of the present disclosure, performing initial transmission verification on the task data packet to determine whether the task data packet is a legal data packet, includes:
s201: and carrying out channel enabling verification on the task data packet to determine whether a corresponding transmission channel of the task data packet is enabled or not.
After receiving the task data packet, determining and judging whether a channel for transmitting the task data packet is enabled. If the channel is not enabled, it indicates that the task data packet is transmitted through an illegal channel, and the current data packet may have a risk. In this case, the current task packet is discarded and an error interrupt is triggered.
S202: and in response to determining that the transmission channel is enabled, performing channel matching verification on the task data packet to determine whether the engine ID in the task data packet is matched with the corresponding engine ID of the transmission channel.
After determining that the transmission channel is enabled, a matching check is further required for the channel to determine whether the task data packet is consistent with the engine ID corresponding to the transmission channel. If the corresponding engine IDs are inconsistent, the data transmission channel is indicated to have errors. In this case, the current task packet is discarded and an error interrupt is triggered.
S203: and responding to the corresponding matching of the task data packet and the engine ID of the transmission channel, and performing data parity check on the task data packet.
And the task data packet channel matching verification passes, which indicates that the task data packet is transmitted through a correct transmission channel legal transmission path, and then content parity verification is required to be executed for the task data packet so as to judge whether the data content of the task data packet changes in the transmission process. If the parity check fails, it indicates that illegal attack may be received in the transmission process of the task data packet, so that the data content in the data packet is changed.
In this case, the current task packet is discarded and an error interrupt is triggered.
S204: and in response to the data parity check passing, determining the task data packet as a legal data packet, and writing the task data packet into a cache FIFO queue.
If the task data packet passes the data parity check, the task data packet is legally transmitted through a correct data channel and is not illegally modified in the transmission process, and the task data packet is a legal data packet. After the task data packet is determined to be legal, the task data packet is written into a cache FIFO queue for subsequent execution of processing on task data in the task data packet.
S3: and determining the working mode of the soft and hard association engine device in response to the passing of the initial transmission check.
After the initial transmission check for the task data packet passes, a work process may be performed for the task data packet. The soft and hard association engine may be in different working modes, and the working mode of the soft and hard association engine is required to be determined first, so that a corresponding processing mode is adopted for the task data packet according to the working mode.
S4: and generating a function interrupt event for the task data packet and notifying a software engine connected with the soft and hard association engine device in response to the soft and hard association engine device being in an interrupt working mode.
In one or more embodiments of the present disclosure, a method for controlling a system chip design based on a hardware package, generating a function interrupt event for the task data packet, and notifying a software engine connected to the soft-hard association engine, includes:
and monitoring the cache FIFO queue in real time to judge whether the interrupt generation condition is met.
Wherein the interrupt generation condition includes that the number of data packets in the buffer FIFO queue reaches a first preset data packet threshold. The preset data packet threshold value is obtained and determined from the software engine.
The interrupt generation condition may further cause the buffer FIFO to store data packets for a time up to a first preset time threshold.
And under the condition that interrupt generation conditions are met, data aggregation is carried out on a plurality of task data packets in the cache FIFO queue, and functional interrupt is generated.
When the number of the data packets in the buffer FIFO queue reaches a preset threshold, or the buffer time of the buffer FIFO queue reaches a preset time threshold, the aggregation module in the soft and hard association engine SWEB executes data aggregation on a plurality of the character data packets in the buffer FIFO queue, and generates a function interrupt.
In some alternative embodiments, the direct notification software of the functional interrupt is generated if the current mode of operation is an interrupt mode. Each software engine independent status register represents the number of valid data packets of the buffer FIFO in real time. When the buffer FIFOs of the 32 software engines are not empty, the packet aggregation register aggregates a certain number of packets or intervals to a configuration time, a functional interrupt is generated. The software reads the software engine independent status registers when handling interrupts and determines the number of packets read based on the value. In addition, the packet buffer FIFO depths of the 32 software engines are not uniform, the smaller the channel ID, the deeper the packet buffer FIFO.
S5: and responding to the event working mode of the soft and hard association engine device, generating a hardware event according to the task data packet, arbitrating the hardware event and writing the hardware event into the work management engine.
As shown in fig. 5, in a system chip design control method based on hardware encapsulation provided in one or more alternative embodiments of the present disclosure, generating a hardware event according to the task data packet, arbitrating the hardware event, and writing the hardware event into the work management engine, where the method includes:
s301: and monitoring the cache FIFO queue in real time to determine whether the event generating condition is met.
The event generating condition includes that the number of data packets in the buffer FIFO queue reaches a second preset data packet threshold, or that the time for storing the data packets in the buffer FIFO reaches a second preset time threshold.
S302: and under the condition that the event generation condition is met, carrying out data aggregation on a plurality of task data packets in the buffer FIFO queue, and generating a hardware event.
S303: and performing parity check on the hardware event, and writing the hardware event into an event FIFO queue after the parity check passes.
S304: and sequentially arbitrating a plurality of hardware events in the event FIFO queue in a training mode, and sending the value of the hardware event after the arbitration to the work management engine.
In some alternative embodiments, if the current operating mode is an event mode, hardware event indirection notification software is generated. And starting timing and counting from the received first data packet, and triggering data packet aggregation when the time reaches the configured time or the number of the data packets reaches the configured number.
The data packet is aggregated to generate hardware time, the hardware event is subjected to parity check and then is cached in a hardware event FIFO, and the arbitration module adopts polling to arbitrate the hardware event and then writes the hardware event into a work management engine through an on-chip internet.
According to the system chip design control method based on the hardware package, the software and hardware association engine device of the design hardware package structure is connected between the hardware engine and the software engine, and is connected with the work management module of the system chip through the on-chip internet to receive and process task data packets of the system chip, so that task forwarding of the hardware engine is realized, and when a problem occurs in the hardware engine, the software engine is utilized for processing instead. The hardware engine and the software engine are combined in an associated mode, the advantages of the hardware engine and the software engine can be comprehensively utilized, the time, the cost, the power consumption, the hardware area and the like are considered, the exception can be rapidly processed, the expansibility and the flexibility are higher, and the design iteration optimization can be conveniently and efficiently realized.
As shown in fig. 6, in a system chip design control method based on hardware encapsulation provided in one or more alternative embodiments of the present disclosure, a SWEB and a work management engine implement communication through registers, so as to complete forwarding of software tasks by the hardware engine.
After receiving the data packet of the work management engine, the SWEB does not analyze the data packet block, and writes the data packet into the FIFO after judging the channel enabling, the engine ID matching and the parity checking. And then carrying out data packet processing according to the working mode classification, generating functional interrupt or generating hardware event and writing the functional interrupt or the hardware event into a working management engine through an AXI bus. The specific flow is as follows:
(1) Initially, a task packet of the work management engine is received using a read packet module in the SWEB.
(2) And judging whether the channel is enabled or not by using the read data packet module.
If not, the current packet is discarded and an error interrupt is triggered.
If enabled, an engine ID check is performed.
(3) And continuously judging whether the engine ID in the data packet is matched with the engine ID of the channel by using the data packet reading module.
If there is no match, the current packet is discarded and an error interrupt is triggered.
And if so, performing parity check.
(4) And performing parity check on the received task data packet by using a parity check module in the SWEB, and judging whether the parity check is matched.
If there is no match, the current packet is discarded and an error interrupt is triggered.
If so, the packet is written to the FIFO.
(5) And judging the working mode by using a data packet reading module according to the data content in the task data packet.
If the interrupt mode is the interrupt mode, the interrupt generation module in the SWEB is utilized to monitor the cache FIFO queue in real time, and whether the interrupt generation condition is met is judged. And under the condition that the interrupt generation condition is met, controlling the interrupt generation module to generate a functional interrupt and notifying the corresponding software engine.
Each software engine independent status register represents the number of valid data packets of the buffer FIFO in real time. When the buffer FIFOs of the 32 software engines are not empty, the packet aggregation register aggregates a certain number of packets or intervals to a configuration time, a functional interrupt is generated. The software reads the software engine independent status registers when handling interrupts and determines the number of packets read based on the value. In addition, the packet buffer FIFO depths of the 32 software engines are not uniform, the smaller the channel ID, the deeper the packet buffer FIFO.
If the event mode is adopted, the buffer FIFO queue is monitored in real time by using the data packet reading module, and whether the event generating condition is met is determined. And under the condition that the event generation condition is met, carrying out data aggregation on a plurality of task data packets in the buffer FIFO queue by utilizing an aggregation module in SWEB, and generating a hardware event.
And starting timing and counting from the received first data packet, triggering data packet aggregation when the time reaches the configured time or the number of the data packets reaches the configured number, and performing data aggregation on a plurality of task data packets in the FIFO by utilizing an aggregation module in the SWEB.
The data packet is aggregated to generate parity check enabling, the hardware event is cached in a hardware event FIFO after parity check is carried out, and an arbitration module in the SWEB is controlled to adopt polling to arbitrate the hardware event and then write into the work management engine through the on-chip Internet.
It should be noted that the methods of one or more embodiments of the present description may be performed by a single device, such as a computer or server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the methods of one or more embodiments of the present description, the devices interacting with each other to accomplish the methods.
It should be noted that the foregoing describes specific embodiments of the present invention. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Fig. 7 is a schematic diagram of a hardware structure of an electronic device according to the embodiment, where the device may include: a processor 1010, a memory 1020, an input/output interface 1030, a communication interface 1040, and a bus 1050. Wherein processor 1010, memory 1020, input/output interface 1030, and communication interface 1040 implement communication connections therebetween within the device via a bus 1050.
The processor 1010 may be implemented by a general-purpose CPU (Central Processing Unit ), microprocessor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.
The Memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), static storage device, dynamic storage device, or the like. Memory 1020 may store an operating system and other application programs, and when the embodiments of the present specification are implemented in software or firmware, the associated program code is stored in memory 1020 and executed by processor 1010.
The input/output interface 1030 is used to connect with an input/output module for inputting and outputting information. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.
Communication interface 1040 is used to connect communication modules (not shown) to enable communication interactions of the present device with other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).
Bus 1050 includes a path for transferring information between components of the device (e.g., processor 1010, memory 1020, input/output interface 1030, and communication interface 1040).
It should be noted that although the above-described device only shows processor 1010, memory 1020, input/output interface 1030, communication interface 1040, and bus 1050, in an implementation, the device may include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.
The electronic device of the foregoing embodiment is configured to implement the corresponding method in the foregoing embodiment, and has the beneficial effects of the corresponding method embodiment, which is not described herein.
Based on the same inventive concept, corresponding to any of the above embodiments, the present disclosure further provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the system-on-chip design control method based on the hardware package according to any of the above embodiments.
The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.
The computer instructions stored in the storage medium of the foregoing embodiments are used to make the computer execute the system chip design control method based on the hardware package according to any one of the foregoing embodiments, and have the beneficial effects of the corresponding method embodiments, which are not described herein.
It will be appreciated by those skilled in the art that implementing all or part of the above-described embodiment method may be implemented by a computer program to instruct related hardware, where the program may be stored in a computer readable storage medium, and the program may include the above-described embodiment method when executed. Wherein the storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a random access Memory (RandomAccessMemory, RAM), a Flash Memory (Flash Memory), a Hard Disk (HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in one or more software and/or hardware elements when implemented in the present application.
It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples; combinations of features of the above embodiments or in different embodiments are also possible within the spirit of the present disclosure, steps may be implemented in any order, and there are many other variations of the different aspects of one or more embodiments described above which are not provided in detail for the sake of brevity.
While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Any omissions, modifications, equivalents, improvements, and the like, which are within the spirit and principles of the one or more embodiments of the disclosure, are therefore intended to be included within the scope of the disclosure.
Claims (10)
1. The soft and hard association engine device of the system chip design system is characterized by comprising a data packet reading module, a parity check module, an interrupt generation module, an aggregation module and an arbitration module;
the reading data packet module is used for acquiring data packets in the buffer FIFO queue through a register interface;
the parity check module is used for performing parity check on the data content of the data packet acquired by the reading data packet module;
the interrupt generation module is used for generating a functional interrupt and/or an error interrupt, wherein the priority of the error interrupt is higher than that of the functional interrupt;
the aggregation module is used for executing data aggregation on a plurality of data packets;
and the arbitration module is used for arbitrating hardware events of the hardware engine in the system chip design system in a polling mode.
2. The hard-soft association engine arrangement according to claim 1, characterized in that the hard-soft association engine arrangement is arranged between a software engine and a hardware engine in the system-on-chip design system;
the software engine and the hardware engine are connected with a work management engine through a network on chip by utilizing the soft and hard association engine device.
3. A system chip design control method based on hardware encapsulation, wherein the method is applied to the soft and hard association engine device according to any one of claims 1 or 2, and the method comprises:
receiving a task data packet forwarded by a work management engine in the system chip design system, wherein the task data packet comprises task data corresponding to system chip design business;
performing initial transmission verification on the task data packet to determine whether the task data packet is a legal data packet;
determining the working mode of the soft and hard association engine device in response to the passing of the initial transmission check;
generating a function interrupt event for the task data packet in response to the soft and hard association engine device being in an interrupt working mode, and notifying a software engine connected with the soft and hard association engine device;
and responding to the event working mode of the soft and hard association engine device, generating a hardware event according to the task data packet, arbitrating the hardware event and writing the hardware event into the work management engine.
4. A method according to claim 3, wherein performing an initial transmission check on the task data packet to determine whether the task data packet is a legitimate data packet comprises:
performing channel enabling verification on the task data packet to determine whether a corresponding transmission channel of the task data packet is enabled or not;
in response to determining that a transmission channel is enabled, performing channel matching verification on the task data packet to determine whether an engine ID in the task data packet is matched with an engine ID corresponding to the transmission channel;
responding to the corresponding matching of the task data packet and the engine ID of the transmission channel, and performing data parity check on the task data packet;
and in response to the data parity check passing, determining the task data packet as a legal data packet, and writing the task data packet into a cache FIFO queue.
5. The method of claim 4, wherein generating a function interrupt event for the task data packet and notifying a software engine connected to the soft and hard association engine comprises:
the buffer FIFO queue is monitored in real time to judge whether the interrupt generation condition is met;
under the condition that interrupt generation conditions are met, data aggregation is carried out on a plurality of task data packets in the cache FIFO queue, and functional interrupt is generated;
the interrupt generation condition comprises that the number of data packets in the buffer FIFO queue reaches a first preset data packet threshold value or the time for storing the data packets in the buffer FIFO reaches a first preset time threshold value;
and the preset data packet threshold value is obtained and determined from the software engine.
6. The method of claim 4, wherein generating a hardware event from the task data packet, arbitrating the hardware event, and writing the hardware event to the job management engine, comprises:
monitoring the cache FIFO queue in real time to determine whether an event generating condition is met;
under the condition that event generating conditions are met, carrying out data aggregation on a plurality of task data packets in the cache FIFO queue, and generating a hardware event;
performing parity check on the hardware event, and writing the hardware event into an event FIFO queue after the parity check passes;
and sequentially arbitrating a plurality of hardware events in the event FIFO queue in a training mode, and sending the value of the hardware event after the arbitration to the work management engine.
7. The method of claim 6, wherein the event generating conditions comprise:
the number of the data packets in the cache FIFO queue reaches a second preset data packet threshold;
or the time of storing the data packets by the buffer FIFO reaches a second preset time threshold.
8. A method according to claim 3, characterized in that the method comprises:
receiving a task data packet forwarded by a work management engine in the system chip design system by using the reading data packet module, wherein the task data packet comprises task data corresponding to system chip design business;
performing channel enabling verification on the task data packet by using the reading data packet module so as to determine whether a corresponding transmission channel of the task data packet is enabled or not;
in response to determining that a transmission channel is enabled, performing channel matching verification on the task data packet by using the read data packet module so as to determine whether an engine ID in the task data packet is matched with an engine ID corresponding to the transmission channel;
responding to the corresponding matching of the task data packet and the engine ID of the transmission channel, and utilizing the task data packet to carry out data parity check;
responding to the data parity check, determining the task data packet as legal data packet, and writing the task data packet into a cache FIFO queue;
determining the working mode of the soft and hard association engine device by using the reading data packet module;
in response to the hard and soft association engine arrangement being in an interrupt mode of operation,
the interrupt generation module is utilized to monitor the cache FIFO queue in real time so as to judge whether the interrupt generation condition is met;
under the condition that interrupt generation conditions are met, the aggregation module is utilized to conduct data aggregation on a plurality of task data packets in the cache FIFO queue, and after data aggregation, the interrupt generation module is controlled to generate functional interrupt;
the interrupt generation condition comprises that the number of data packets in the buffer FIFO queue reaches a first preset data packet threshold value or the time for storing the data packets in the buffer FIFO reaches a first preset time threshold value;
after the function interrupt is generated, a function interrupt message is sent to a software engine connected with the soft and hard association engine device;
responding to the condition that the soft and hard association engine device is in an event working mode, and utilizing the read data packet module to monitor the cache FIFO queue in real time so as to determine whether an event generating condition is met;
under the condition that event generation conditions are met, carrying out data aggregation on a plurality of task data packets in the cache FIFO queue by utilizing the aggregation module, and generating a hardware event;
performing parity check on the hardware event by utilizing the parity check module, and writing the hardware event into an event FIFO queue after the parity check passes;
and sequentially arbitrating a plurality of hardware events in the event FIFO queue by using the arbitration module in a training mode, and sending the value of the hardware event after the arbitration to the work management engine.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any of claims 3 to 8 when executing the program.
10. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 3 to 8.
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