CN110928574A - Microcontroller, interrupt processing chip, device and interrupt processing method - Google Patents
Microcontroller, interrupt processing chip, device and interrupt processing method Download PDFInfo
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Abstract
The embodiment of the application provides a microcontroller, an interrupt processing chip, equipment and an interrupt processing method, wherein the microcontroller comprises: the system comprises a kernel unit, an interrupt control unit and at least one buffer register group; the kernel unit is in communication connection with the interrupt control unit, the kernel unit is in communication connection with a buffer register group, and the buffer register group comprises at least one register; the interrupt control unit is used for determining the storage position of the context data in the kernel unit according to the interrupt signal and generating a storage control signal; and the kernel unit is used for storing the context data into the buffer register group according to the storage control signal when the storage control signal indicates that the storage position of the context data is the buffer register group. The number of system clocks consumed for storing context data when an interrupt occurs can be significantly reduced, and further, the delay of interrupt response can be significantly reduced.
Description
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a microcontroller, an interrupt processing chip, an interrupt processing device and an interrupt processing method.
Background
With the development of computer technology, the application of microcontrollers is becoming more and more widespread. In a microcontroller, the function of interrupt processing is indispensable, and how to process an interrupt becomes a focus of attention.
In one technical solution, when an interrupt request is generated in a normally processed program, in response to the interrupt request, context data of the program being executed in a kernel unit is stored in an SRAM (Static Random-Access Memory), then a corresponding interrupt processing function is executed, and after the execution of the interrupt processing function is completed, the context data corresponding to the program is restored. In the technical scheme, context data of a program being executed by a core unit during interruption is stored in the SRAM, however, the writing of data into the SRAM consumes more system clock, and the delay of interruption response is longer.
Disclosure of Invention
It is therefore one of the objectives of the present invention to provide a microcontroller, an interrupt processing chip, an interrupt processing device and an interrupt processing method, so as to overcome the problem of long delay of interrupt response caused by writing context data of a program executed by a kernel unit into an SRAM when an interrupt occurs.
According to a first aspect of embodiments of the present application, there is provided a microcontroller comprising: the system comprises a kernel unit, an interrupt control unit and at least one buffer register group; the kernel unit is in communication connection with the interrupt control unit, the kernel unit is in communication connection with a buffer register group, and the buffer register group comprises at least one register;
the interrupt control unit is used for determining the storage position of the context data in the kernel unit according to the interrupt signal and generating a storage control signal, the context data comprises data cached in the kernel unit when the interrupt signal is generated, the storage control signal is used for indicating the storage position of the context data, and the storage position of the context data comprises a buffer register group and a random access memory;
and the kernel unit is used for storing the context data into the buffer register group according to the storage control signal when the storage control signal indicates that the storage position of the context data is the buffer register group.
Optionally, in an embodiment of the present application, the buffer register set includes a number configuration register;
the number configuration register is used for storing number configuration information, the number configuration information is used for indicating the interrupt number of the buffer register group, and the interrupt number indicated by the number configuration information is a fixed number or a dynamic number;
and the kernel unit is used for storing the context data into a buffer register with the interrupt number consistent with the number indicated by the storage control signal.
Optionally, in an embodiment of the present application, the buffer register set includes a buffer configuration register;
and the buffer configuration register is used for configuring the type of the buffer register group, the type of the buffer register group comprises a fixed buffer register group and a dynamic buffer register group, the serial number indicated by the serial number configuration information of the fixed buffer register group is a fixed serial number, and the serial number indicated by the serial number configuration information of the dynamic buffer register group is a dynamic serial number.
Optionally, in an embodiment of the present application, the interrupt control unit is further configured to determine, when it is determined that the current interrupt is a fast interrupt according to the interrupt signal, a storage location of the context data as a buffer register set, and when it is determined that the current interrupt is a normal interrupt, the storage location of the context data is determined as a random access memory.
Optionally, in an embodiment of the present application, the interrupt control unit is further configured to generate a storage control signal according to a number of the interrupt signal when it is determined that the interrupt type is a preset fixed interrupt according to the number of the interrupt signal.
Optionally, in an embodiment of the present application, the interrupt control unit is further configured to configure an interrupt number of an idle buffer register group as a number of the interrupt signal when it is determined that the interrupt type is not the preset fixed interrupt according to the number of the interrupt signal, and generate the storage control signal according to the number of the interrupt signal.
Optionally, in an embodiment of the present application, the interrupt control unit is further configured to determine, when it is determined that the interrupt type is not a preset fixed interrupt according to the number of the interrupt signal and a free buffer register set cannot exist, the random access memory as a storage location of the context data, and generate the storage control signal.
Optionally, in an embodiment of the present application, the buffer register set includes a clear register;
the clearing register is used for storing clearing configuration information, and the clearing configuration information is used for indicating whether context data stored in the buffer register group is cleared or not;
and the kernel unit is further used for storing the context data into the random access memory and emptying the context data in the buffer register group when the emptying configuration information indicates to empty the context data stored in the buffer register group.
Optionally, in an embodiment of the present application, the buffer register set includes an address register;
the address register is used for storing address configuration information of the random access memory, and the address configuration information is used for indicating an address of an available space in the random access memory;
and the kernel unit is also used for storing the context data to the position indicated by the address configuration information in the random access memory.
Optionally, in an embodiment of the present application, the microcontroller further includes an interrupt priority management unit, and the interrupt priority management unit is communicatively connected to the interrupt control unit;
and the interrupt priority management unit is used for transmitting the interrupt signal with the highest priority in the at least one interrupt signal to the interrupt control unit.
Optionally, in an embodiment of the present application, the interrupt control unit is further configured to suspend storing the context data corresponding to the previous interrupt signal and store the context data corresponding to the current interrupt signal when the priority of the current interrupt signal is higher than that of the previous interrupt signal.
According to a second aspect of embodiments of the present application, there is provided an interrupt processing chip comprising a microcontroller as described in the first aspect or any one of the embodiments of the first aspect.
According to a third aspect of embodiments herein, there is provided an interrupt handling device comprising a microcontroller as described in the first aspect or any one of the embodiments of the first aspect.
According to a fourth aspect of embodiments of the present application, there is provided an interrupt processing method applied to a microcontroller as described in the first aspect or any one of the embodiments of the first aspect, the method including:
determining a storage position of context data in the kernel unit according to the interrupt signal, and generating a storage control signal, wherein the context data comprises data cached in the kernel unit when the interrupt signal is generated, the storage control signal is used for indicating the storage position of the context data, and the storage position of the context data comprises a buffer register group and a random access memory;
and when the storage control signal indicates that the storage position of the context data is a buffer register group, storing the context data into the buffer register group according to the storage control signal.
According to the technical scheme of the embodiment of the application, the storage position of the context data in the kernel unit is determined according to the interrupt signal, and a storage control signal is generated, wherein the storage position of the context data comprises a buffer register group and a random access memory; and when the storage control signal indicates that the storage position of the context data is a buffer register group, storing the context data into the buffer register group according to the storage control signal. Since the context data can be stored in the buffer register group, the number of system clocks consumed for storing the context data when an interrupt occurs is reduced, and the delay of interrupt response can be significantly reduced.
Drawings
Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
fig. 1 is a schematic structural diagram of a microcontroller according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a microcontroller according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a buffer register set according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a microcontroller according to an embodiment of the present application;
FIG. 5 illustrates a schematic block diagram of a kernel unit provided in accordance with some embodiments of the present application;
fig. 6 is a schematic block diagram of a microcontroller according to an embodiment of the present application;
fig. 7 is a schematic flowchart of an interrupt control method according to an embodiment of the present application;
fig. 8 is a flowchart illustrating an interrupt control method according to an embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic structural diagram of a microcontroller according to an embodiment of the present application. Referring to fig. 1, the microcontroller includes a core unit 110, the core unit 110 includes a general register 114 and a control and status register 112, and the core unit 110 is communicatively connected to an SRAM (Static Random Access Memory) 130 via a bus 120. When an Interrupt occurs, the core unit 110 receives an Interrupt Request IRQ (Interrupt Request), and stores context data of the program being executed, including data of the general purpose register 114 and the control and status register 112 of the core unit 110 when the Interrupt Request occurs, into the SRAM 130 via the bus 120. Assuming that the number of registers to be stored is PRES _ N, if W _ X system clocks are consumed to write data into the SRAM 130 once, when an interrupt request arrives, the system clock to be consumed to store context data is at least RESP _ N — PRES _ N × W _ X system clocks, that is, there is at least a delay of RESP _ N system clocks from the generation of the interrupt request to the execution of the interrupt handler. Assuming that the number of registers PRES _ N in a microcontroller is 8 and the system clock W _ X required to write data once to the SRAM 130 is 1, at least 8 system clocks are required to store context data in the SRAM 130.
The first embodiment,
Based on the above, the first embodiment of the present application provides a microcontroller. Referring to fig. 2, the microcontroller 200 includes: the interrupt protection device comprises a kernel unit 210, an interrupt control unit 220 and at least one buffer register group 230, wherein the kernel unit is in communication connection with the interrupt control unit 210, the kernel unit 210 is in communication connection with the buffer register group, and the buffer register group comprises at least one register;
an interrupt control unit 220, configured to determine a storage location of context data in the core unit according to the interrupt signal, and generate a storage control signal, where the context data includes data cached in the core unit 210 when the interrupt signal is generated, the storage control signal is used to indicate the storage location of the context data, and the storage location of the context data includes a buffer register group 230 and a random access memory;
the core unit 210 is configured to store the context data into the buffer register group 230 according to the storage control signal when the storage control signal indicates that the storage location of the context data is the buffer register group 230.
According to the microcontroller 200 in the exemplary embodiment of fig. 2, the context data of the program executed by the core unit 210 is stored in the buffer register group 230 or the random access memory based on the received interrupt signal, and since the context data can be stored in the buffer register group 230 in parallel when the interrupt signal is received, the number of system clocks consumed for storing the context data when the interrupt occurs can be significantly reduced, and thus the delay of the interrupt response can be significantly reduced.
Further, in an example embodiment, microcontroller 200 includes a plurality of buffer register sets 230, and the plurality of buffer register sets 230 may be divided into fixed buffer register sets and dynamic buffer register sets. The fixed buffer register group is used for fixedly storing context data, specifically, context data corresponding to a preset interrupt signal can be stored, the dynamic buffer register group is used for dynamically storing the context data, and specifically, context data corresponding to a current interrupt signal can be stored. In addition, when the number of sets of the dynamic buffer register group is greater than 2 sets, the technical solution of the example embodiment can support nesting of fast interrupts.
Fig. 3 is a schematic structural diagram of a buffer register set according to an embodiment of the present application, and here, a specific example is illustrated, and optionally, in an embodiment of the present application, the buffer register set 230 includes a number configuration register 231; a number configuration register 231 for storing number configuration information, where the number configuration information is used to indicate an interrupt number of the buffer register group 230, and the interrupt number indicated by the number configuration information is a fixed number or a dynamic number; the core unit 210 is configured to store the context data in a buffer register having an interrupt number identical to a number indicated by the storage control signal.
Further optionally, as shown in fig. 3, in an embodiment of the present application, the buffer register set 230 includes a buffer configuration register 232; the buffer configuration register 232 is configured to configure the type of the buffer register group 230, where the type of the buffer register group 230 includes a fixed buffer register group and a dynamic buffer register group, a number indicated by the number configuration information of the fixed buffer register group is a fixed number, and a number indicated by the number configuration information of the dynamic buffer register group is a dynamic number.
The interrupt type indicated by the interrupt signal may be divided into a normal interrupt and a fast interrupt, and when the interrupt signal indicates that the current interrupt is a fast interrupt, the context data is stored in the buffer register group 230, and when the interrupt signal indicates that the current interrupt is a normal interrupt, the context data is stored in the random access memory.
For example, optionally, in an embodiment of the present application, the interrupt control unit 220 is further configured to determine the storage location of the context data as the buffer register set 230 when determining that the current interrupt is a fast interrupt according to the interrupt signal, and determine the storage location of the context data as the random access memory when determining that the current interrupt is a normal interrupt.
In a scenario where the interrupt signal indicates that the current interrupt is a fast interrupt, the structure of the microcontroller 200 corresponding to fig. 3 is described in detail by taking three specific examples:
optionally, in the first example, the interrupt control unit 220 is further configured to generate the storage control signal according to the number of the interrupt signal when it is determined that the interrupt type is the preset fixed interrupt according to the number of the interrupt signal.
When the number of the interrupt signal indicates that the interrupt type is the preset fixed interrupt, the preset fixed interrupt has a corresponding fixed buffer register group, the buffer configuration register 232 in the fixed buffer register group configures the fixed buffer register group as the fixed buffer register group, and the interrupt number indicated by the number configuration information stored in the number configuration register 231 is consistent with the number of the current interrupt signal, so that the storage control signal is generated according to the number of the interrupt signal, and the context data can be stored in the corresponding buffer register group according to the number of the interrupt signal.
Optionally, in the second example, the interrupt control unit 220 is further configured to configure the interrupt number of the idle buffer register group 230 as the number of the interrupt signal when it is determined that the interrupt type is not the preset fixed interrupt according to the number of the interrupt signal, and generate the storage control signal according to the number of the interrupt signal.
And the number of the interrupt signal indicates that the type of the current interrupt is not a preset fixed interrupt, and the current interrupt does not have a corresponding buffer register group, and the current interrupt is stored in any dynamic buffer register.
Optionally, in the third example, the interrupt control unit 220 is further configured to determine the random access memory as a storage location of the context data and generate the storage control signal when it is determined that the interrupt type is not the preset fixed interrupt according to the number of the interrupt signal and the free buffer register group 230 cannot exist.
If the current interrupt is not a preset fixed interrupt and there is no idle buffer register set 230, the context data corresponding to the current interrupt cannot be stored in the buffer register set 230, and the context data can be stored in the random access memory.
As shown in fig. 3, optionally, in one embodiment of the present application, buffer register set 230 includes clear register 233; a clear register 233, configured to store clear configuration information, where the clear configuration information is used to indicate whether to clear context data stored in the buffer register set 230; the kernel unit 210 is further configured to, when the flushing configuration information indicates to flush the context data stored in the buffer register set 230, store the context data into the random access memory, and flush the context data in the buffer register set 230.
Optionally, in an embodiment of the present application, as shown in fig. 3, the buffer register set 230 includes an address register 234; an address register 234 for storing address configuration information of the random access memory, the address configuration information indicating an address of an available space in the random access memory; the core unit 210 is further configured to store the context data in a location indicated by the address configuration information in the random access memory.
Optionally, in an embodiment of the present application, as shown in fig. 4, the microcontroller 200 further includes an interrupt priority management unit 240, and the interrupt priority management unit 240 is communicatively connected to the interrupt control unit 220; the interrupt priority management unit 240 is configured to transmit an interrupt signal with the highest priority in the at least one interrupt signal to the interrupt control unit 220.
The interrupt control unit 220 may receive a plurality of interrupt signals in the same time period, at this time, the interrupt signal with the highest priority is transmitted to the interrupt control unit 220, and then, the interrupt signal with the highest priority is determined from the rest of the interrupt signals and transmitted to the interrupt control unit 220, and the process is sequentially circulated until all the interrupt signals are processed.
Optionally, in an embodiment of the present application, the interrupt control unit 220 is further configured to suspend storing the context data corresponding to the previous interrupt signal and store the context data corresponding to the current interrupt signal when the priority of the current interrupt signal is higher than that of the previous interrupt signal.
If the control unit 220 and/or the core unit 210 in the interrupt process is storing the context data corresponding to the previous interrupt signal, the interrupt control unit receives the current interrupt signal again, if the priority of the current interrupt signal is greater than that of the previous interrupt signal, the storage of the context data corresponding to the previous interrupt signal is suspended, the context data corresponding to the current interrupt signal is stored first, and after the storage of the context data corresponding to the current interrupt signal is completed, the storage of the context data corresponding to the previous interrupt signal is resumed and continued.
Referring to fig. 5, the core unit 210 includes a context switching unit 211, and the context switching unit 211 is configured to store context data to the buffer register group 230 or the random access memory in parallel according to a storage control signal. It should be noted that, although in the example embodiment of fig. 5, the context switching unit is disposed in the core unit, in other embodiments of the present application, the context switching unit may also be disposed outside the core unit, which is also within the protection scope of the present application.
According to the technical scheme of the embodiment of the application, the storage position of the context data in the kernel unit is determined according to the interrupt signal, and a storage control signal is generated, wherein the storage position of the context data comprises a buffer register group and a random access memory; and when the storage control signal indicates that the storage position of the context data is a buffer register group, storing the context data into the buffer register group according to the storage control signal. Since the context data can be stored in the buffer register group, the number of system clocks consumed for storing the context data when an interrupt occurs is reduced, and the delay of interrupt response can be significantly reduced.
Example II,
Based on the microcontroller described in the first embodiment, a second embodiment of the present application provides a microcontroller, as shown in fig. 6, and fig. 6 is a schematic block diagram of the microcontroller provided in the second embodiment of the present application. Referring to fig. 6, a microcontroller 600 includes: a plurality of buffer register sets 610, a core unit 620, an interrupt control unit 630, and a register. Each buffer register group 610 is communicatively connected to the core unit 620, and the buffer register group 610 includes a plurality of buffer registers, the number of the buffer registers is determined by a specific core architecture, and the plurality of buffer registers are used for storing data in registers related to context data in the core unit when an interrupt occurs. The core unit 620 includes a general register GR 622 and a control and status register CSR 624, and context data of programs executed by the core unit 620 are stored in the general register GR 622 and the control and status register CSR 624. The interrupt control unit 630 is communicatively coupled to the core unit 620, and is configured to determine a storage location of context data of a program executed by the core unit 620 based on the received interrupt signal, so that the core unit 620 stores the context data of the program based on the storage location, wherein the storage location includes the buffer register set 610 or the random access memory 660, and the random access memory 660 is communicatively coupled to the core unit 620 via the bus 650.
Further, the plurality of buffer register groups 610 include a fixed buffer register group and a dynamic buffer register group, where the fixed buffer register group is used for fixedly storing context data corresponding to the target interrupt signal; and the dynamic buffer register group is used for dynamically storing context data corresponding to one interrupt signal in the plurality of interrupt signals. The fixed buffer register set and the dynamic buffer register set each include a control register set for storing configuration information configuring storage of context data of a program currently executed by the core unit 620 in the buffer register set 610.
The control register group includes a buffer configuration register 612 and a number configuration register 614, where the buffer configuration register 612 is used to store fixed buffer configuration information for configuring whether the buffer register group 610 is a fixed buffer register group; and a number configuration register 614 for storing number configuration information for configuring the number of the target interrupt signal. Further, the control register group further includes: an address register 616 and a clear register 618, wherein the address register 616 is used for storing address configuration information of an address storing context data in the random access memory 660; the clear register 618 is used to store clear configuration information for whether to clear context data stored in the buffer register set.
In an example embodiment, the interrupt control unit 630 is configured to generate a storage control signal based on the received interrupt signal and/or the configuration information stored by the control register set, the storage control signal containing information of a storage location of the context data, e.g., FIRQ _ group; the storage control signal is transmitted to the core unit 620 to cause the core unit 620 to store the context data based on the storage control signal.
Further, in an example embodiment, the configuration information stored in the control register set includes FLUSH configuration information, the storage control signal further includes a FLUSH control signal, i.e., FIRQ _ FLUSH _ REQ, and the interrupt control unit 630 is further configured to: if the storage position of the context data is determined to be a target buffer register group, namely, FIRQ _ group, determining whether to empty the context data stored in the target buffer register based on the empty configuration information of an empty register in the target buffer register group FIRQ _ group; if it is determined to be cleared, a clear control signal FIRQ _ FLUSH _ REQ, which is used to cause the core unit 620 to clear the context data stored in the target buffer register based on the clear control signal, is set to be active, for example, set to a high level.
Further, the microcontroller 600 further includes an interrupt priority management unit 640, where the interrupt priority management unit 640 is communicatively connected to the interrupt control unit 630, and is configured to determine a type and/or priority of the interrupt signal IRQ, and send the interrupt signal to the interrupt control unit 630 based on the type and/or priority of the interrupt signal, where the type of the interrupt signal includes a fast interrupt and a normal interrupt. For example, if the interrupt signal IRQx is a fast interrupt, the interrupt signal IRQx is sent to the interrupt control unit 630; or, if the priority of the interrupt signal IRQx is greater than the predetermined priority, the interrupt signal IRQx is sent to the interrupt control unit 630; alternatively, if all the interrupt signals are fast interrupts, the interrupt signal IRQx with the highest priority among the interrupt signals is determined, and the interrupt signal IRQx with the highest priority is sent to the interrupt control unit 630.
Further, in the exemplary embodiment, the store control signal further includes a store set signal, FIRQ _ REQ, and the interrupt control unit 630 is further configured to: determining whether there is a free buffer register group among the plurality of buffer register groups in response to an interrupt signal IRQx transmitted from the interrupt priority management unit 640; if an idle buffer register group exists, setting a storage setting signal FIRQ _ REQ to be effective, and simultaneously using the idle buffer register group as a storage position of context data, namely setting FIRQ _ GROUPx as the idle buffer register; if there is no free buffer register group, the store set signal FIRQ _ REQ is set to inactive, e.g., low.
Further, in an example embodiment, the core unit 620 further includes a context switching unit 625, and the context switching unit 625 is configured to store context data to a buffer register set or a random access memory according to the storage control signal. For example, if the FIRQ _ REQ signal is asserted in the store control signal, the context data is stored in the buffer register set indicated by the FIRQ _ group signal; if the FIRQ _ REQ signal is not asserted in the store control signal, the context data is stored in the SRAM 660.
Further, fast interrupt nesting can be supported when there are more than 2 dynamic buffer registers in the buffer register set. Thus, in an example embodiment, the interrupt control unit 630 is further configured to: determining whether another interrupt signal with higher priority than the interrupt signal exists when an interrupt processing function corresponding to the interrupt signal is executed; if another interrupt signal with higher priority exists, the other interrupt signal is processed preferentially, and after the context data of the other interrupt signal is stored, the context data corresponding to the current interrupt signal is processed continuously. By prioritizing another interrupt signal of higher priority, fast context storage for high priority interrupt requests can be achieved, thereby achieving fast interrupt nesting. The number of stages of the fast interrupt depends on the number of dynamic buffer register sets in the buffer register set.
Further, the address register in the buffer register indicated by the FIRQ _ group _ signal further includes address configuration information, and the context switch unit 625 is further configured to: determining whether a FLUSH control signal FIRQ _ FLUSH _ REQ in the storage control signal is active; if valid, the context data stored in the target buffer register is copied to the location in the SRAM 660 corresponding to the address configuration information before the context data stored in the buffer register indicated by the FIRQ _ group signal, which is the target buffer register, is emptied. In the example embodiment of the present application, after the key logic is processed in the interrupt processing function, the current buffer register set may be released by clearing the control signal, and the released buffer register set may be used for storing context data of other interrupt requests, so that the nesting capability of interrupt processing may be improved.
Furthermore, in the example embodiment, the interrupt control unit 630 is also used to recover context data from the set of buffer registers/random access registers.
Example III,
Based on the microcontroller described in the first embodiment, an interrupt control method is provided in the embodiments of the present application, and is applicable to the microcontrollers described in the first and second embodiments. Referring to fig. 7, the interrupt control method includes: step S710 and step S720. The interrupt control method in the exemplary embodiment of the present application is described in detail below with reference to fig. 7.
In step S710, a storage location of the context data in the core unit is determined according to the interrupt signal, and a storage control signal is generated.
The context data includes data buffered in the core unit when the interrupt signal is generated, the storage control signal is used for indicating a storage position of the context data, and the storage position of the context data includes a buffer register group and a random access memory.
In some embodiments, when the interrupt signal indicates that the current interrupt is a fast interrupt, storing the context data into a buffer register set, and when the interrupt signal indicates that the current interrupt is a normal interrupt, storing the context data into a random access memory;
in other embodiments, the storage location of the context data of the program executed by the kernel unit is determined based on the priority of the interrupt signal, for example, if the priority of the interrupt signal is greater than a predetermined priority, the storage location of the context data is a buffer register set; if the priority of the interrupt signal is less than or equal to the predetermined priority, the storage location of the context data is a random access memory, the predetermined priority may be determined according to a required response time of the interrupt signal, and the shorter the required response time, the higher the priority.
In step 720, when the storage control signal indicates that the storage location of the context data is a buffer register set, the context data is stored in the buffer register set according to the storage control signal.
In an example embodiment, if the determined storage location of the context data is a buffer register set, storing the context data of the program executed by the kernel unit to the buffer register set in parallel; if the determined storage location of the context data is a random access memory, the context data of the program executed by the kernel unit is serially stored to the random access memory.
Each step of the interrupt processing method in the embodiment of the present application corresponds to a processing procedure of each module or unit of the microcontroller in the above embodiment, and is not described herein again.
Example four,
Based on the microcontrollers described in the first embodiment and the second embodiment and the interrupt control method described in the third embodiment, fig. 8 is a schematic flow chart of an interrupt control method provided in the embodiments of the present application.
Referring to fig. 8, in step S805, a fixed buffer register GROUP in a plurality of buffer register GROUPs, i.e., FIRQ _ GROUP GROUPs, is configured, for example, by software, to configure configuration information of a fixed buffer configuration register in a target buffer register GROUP, i.e., whether a configuration target buffer register is the fixed buffer register GROUP or the dynamic buffer register GROUP.
In step S810, the routine is normally executed.
In step S815, it is determined whether an interrupt request is generated, and if an interrupt request is generated, the process proceeds to step S820; if no interrupt request is generated, the process returns to step S810.
In step S820, it is determined by the interrupt control unit whether the interrupt signal satisfies a fast interrupt condition, the fast interrupt condition including: if the interrupt signal is a fast interrupt or the priority of the interrupt signal is greater than the predetermined priority, the process proceeds to step S825 if the interrupt signal satisfies the fast interrupt condition.
In step S825, determining whether the interrupt signal is a preset fixed interrupt based on the number of the received interrupt signal, the fixed buffer configuration information, and the number configuration information; if the interrupt is a preset fixed interrupt, taking the buffer register group corresponding to the interrupt signal as the storage position of the context data, and proceeding to step S830; if the interrupt is not the preset fixed interrupt, determining whether an idle buffer register group exists in the buffer register group; if the idle buffer register group exists, taking the idle buffer register group as a storage position of the context data, and proceeding to step S830; if there is no free buffer register set, the random access memory is used as the storage location of the context data, and the process proceeds to step S835.
In step S830, the context switching unit stores the context data of the program executed by the kernel unit to the buffer register group.
In step S835, the context switching unit stores the context data of the program executed by the kernel unit into the stack of the SRAM.
In step S840, an interrupt handling function is executed.
In step S845, it is determined whether there is another interrupt request higher in priority than the interrupt request being processed, and if there is another interrupt request higher in priority, proceeding to step S820; if there is no other interrupt request with higher priority, the process proceeds to step S850.
In step S850, it is determined whether the current interrupt processing is completed, and if the processing is completed, the process proceeds to step S855; if not, processing proceeds to step S840.
In step S855, it is determined whether the interrupt signal is a fast interrupt or whether the priority of the interrupt signal is greater than a predetermined priority; if the interrupt is a fast interrupt or the priority of the interrupt signal is greater than the predetermined priority, go to step S860; and if the interrupt is not the quick interrupt or the priority of the interrupt signal is less than or equal to the preset priority, recovering the context data of the program executed by the kernel unit from the random access memory.
In step S860, the context switching unit restores the context data of the program executed by the kernel unit from the buffer register set, and then returns to step S810.
In step S865, the context switching unit restores the context data of the program executed by the kernel unit from the stack of the SRAM, and then returns to step S810.
Example V,
Based on the microcontrollers described in the first embodiment and the second embodiment, an embodiment of the present application provides an interrupt processing chip including the microcontroller described in the first embodiment or the second embodiment.
Example six,
Based on the microcontrollers described in the first embodiment and the second embodiment, an embodiment of the present application provides an interrupt processing device including the microcontroller described in the first embodiment or the second embodiment.
The interrupt processing chip or the interrupt processing device in the embodiment of the present application adopts the above microcontroller, so that all advantages corresponding to the microcontroller are provided.
The interrupt handling device of the embodiments of the present application exists in various forms, including but not limited to:
(1) a mobile communication device: such devices are characterized by mobile communications capabilities and are primarily targeted at providing voice, data communications. Such terminals include: smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.
(2) Ultra mobile personal computer device: the equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads.
(3) A portable entertainment device: such devices can display and play multimedia content. This type of device comprises: audio, video players (e.g., ipods), handheld game consoles, electronic books, and smart toys and portable car navigation devices.
(4) And other electronic equipment with data interaction function.
Thus, particular embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may be advantageous.
In the 90 s of the 20 th century, improvements in a technology could clearly distinguish between improvements in hardware (e.g., improvements in circuit structures such as diodes, transistors, switches, etc.) and improvements in software (improvements in process flow). However, as technology advances, many of today's process flow improvements have been seen as direct improvements in hardware circuit architecture. Designers almost always obtain the corresponding hardware circuit structure by programming an improved method flow into the hardware circuit. Thus, it cannot be said that an improvement in the process flow cannot be realized by hardware physical modules. For example, a Programmable Logic Device (PLD), such as a Field Programmable Gate Array (FPGA), is an integrated circuit whose Logic functions are determined by programming the Device by a user. A digital system is "integrated" on a PLD by the designer's own programming without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Furthermore, nowadays, instead of manually making an integrated Circuit chip, such Programming is often implemented by "logic compiler" software, which is similar to a software compiler used in program development and writing, but the original code before compiling is also written by a specific Programming Language, which is called Hardware Description Language (HDL), and HDL is not only one but many, such as abel (advanced Boolean Expression Language), ahdl (alternate Language Description Language), traffic, pl (core unified Programming Language), HDCal, JHDL (Java Hardware Description Language), langue, Lola, HDL, laspam, hardsradware (Hardware Description Language), vhjhd (Hardware Description Language), and vhigh-Language, which are currently used in most common. It will also be apparent to those skilled in the art that hardware circuitry that implements the logical method flows can be readily obtained by merely slightly programming the method flows into an integrated circuit using the hardware description languages described above.
The microcontroller may be implemented in any suitable manner, for example, the microcontroller may take the form of, for example, a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, an Application Specific Integrated Circuit (ASIC), a programmable logic controller, and an embedded microcontroller, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic for the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may thus be considered a hardware component, and the means included therein for performing the various functions may also be considered as a structure within the hardware component. Or even means for performing the functions may be regarded as being both a software module for performing the method and a structure within a hardware component.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular transactions or implement particular abstract data types. The application may also be practiced in distributed computing environments where transactions are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (14)
1. A microcontroller, characterized in that the microcontroller comprises: the system comprises a kernel unit, an interrupt control unit and at least one buffer register group; the kernel unit is in communication connection with the interrupt control unit, the kernel unit is in communication connection with the buffer register group, and the buffer register group comprises at least one register;
the interrupt control unit is configured to determine a storage location of context data in the core unit according to an interrupt signal, and generate a storage control signal, where the context data includes data cached in the core unit when the interrupt signal is generated, the storage control signal is used to indicate the storage location of the context data, and the storage location of the context data includes the buffer register set and a random access memory;
the kernel unit is configured to store the context data in a buffer register set according to the storage control signal when the storage control signal indicates that the storage location of the context data is the buffer register set.
2. The microcontroller of claim 1 wherein the set of buffer registers includes a number configuration register;
the number configuration register is used for storing number configuration information, the number configuration information is used for indicating the interrupt number of the buffer register group, and the interrupt number indicated by the number configuration information is a fixed number or a dynamic number;
the kernel unit is used for storing the context data into a buffer register with an interrupt number consistent with the number indicated by the storage control signal.
3. The microcontroller of claim 2 wherein the set of buffer registers includes a buffer configuration register;
the buffer configuration register is used for configuring the type of the buffer register group, the type of the buffer register group comprises a fixed buffer register group and a dynamic buffer register group, the serial number indicated by the serial number configuration information of the fixed buffer register group is a fixed serial number, and the serial number indicated by the serial number configuration information of the dynamic buffer register group is a dynamic serial number.
4. The microcontroller according to claim 2,
the interrupt control unit is further configured to determine the storage location of the context data as the buffer register set when determining that the current interrupt is a fast interrupt according to the interrupt signal, and determine the storage location of the context data as the random access memory when determining that the current interrupt is a normal interrupt.
5. The microcontroller according to claim 4,
and the interrupt control unit is further used for generating the storage control signal according to the number of the interrupt signal when the interrupt type is determined to be the preset fixed interrupt according to the number of the interrupt signal.
6. The microcontroller according to claim 4,
the interrupt control unit is further configured to configure the interrupt number of the idle buffer register set as the number of the interrupt signal when it is determined that the interrupt type is not the preset fixed interrupt according to the number of the interrupt signal, and generate the storage control signal according to the number of the interrupt signal.
7. The microcontroller according to claim 4,
the interrupt control unit is further configured to determine the random access memory as a storage location of the context data and generate the storage control signal when it is determined that the interrupt type is not a preset fixed interrupt and the buffer register set which is idle cannot exist according to the number of the interrupt signal.
8. The microcontroller of claim 1 wherein the set of buffer registers includes a clear register;
the clearing register is configured to store clearing configuration information, where the clearing configuration information is used to indicate whether to clear the context data stored in the buffer register set;
the kernel unit is further configured to store the context data in the random access memory and empty the context data in the buffer register set when the empty configuration information indicates to empty the context data stored in the buffer register set.
9. The microcontroller of claim 1 wherein the set of buffer registers includes an address register;
the address register is used for storing address configuration information of the random access memory, and the address configuration information is used for indicating an address of an available space in the random access memory;
the kernel unit is further configured to store the context data to a location in the random access memory indicated by the address configuration information.
10. The microcontroller of claim 1 further comprising an interrupt priority management unit communicatively coupled to the interrupt control unit;
the interrupt priority management unit is configured to transmit an interrupt signal with a highest priority in the at least one interrupt signal to the interrupt control unit.
11. The microcontroller according to claim 10,
the interrupt control unit is further configured to suspend storing the context data corresponding to the previous interrupt signal and store the context data corresponding to the current interrupt signal when the priority of the current interrupt signal is higher than that of the previous interrupt signal.
12. An interrupt handling chip comprising a microcontroller according to any one of claims 1-11.
13. An interrupt handling device comprising a microcontroller as claimed in any one of claims 1 to 11.
14. An interrupt processing method applied to the microcontroller according to any one of claims 1 to 11, the method comprising:
determining a storage location of context data in the core unit according to an interrupt signal, and generating a storage control signal, where the context data includes data cached in the core unit when the interrupt signal is generated, the storage control signal is used to indicate the storage location of the context data, and the storage location of the context data includes the buffer register set and a random access memory;
when the store control signal indicates that the storage location of the context data is a buffer register set,
storing the context data into the set of buffer registers according to the storage control signal.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114328323A (en) * | 2021-12-01 | 2022-04-12 | 北京三快在线科技有限公司 | Data transfer unit and data transmission method based on data transfer unit |
| CN114978965A (en) * | 2022-05-25 | 2022-08-30 | 中国第一汽车股份有限公司 | CAN diagnosis message and network message processing method and system under high-load condition of chip, electronic device and storage medium |
| CN117555599A (en) * | 2024-01-10 | 2024-02-13 | 睿思芯科(成都)科技有限公司 | Chip design method, system and related equipment for accelerating key data access speed |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996008948A2 (en) * | 1994-09-19 | 1996-03-28 | Philips Electronics N.V. | Method and apparatus for fast microcontroller context switching |
| US5987495A (en) * | 1997-11-07 | 1999-11-16 | International Business Machines Corporation | Method and apparatus for fully restoring a program context following an interrupt |
| US6128728A (en) * | 1997-08-01 | 2000-10-03 | Micron Technology, Inc. | Virtual shadow registers and virtual register windows |
| CN1856770A (en) * | 2002-05-31 | 2006-11-01 | 飞思卡尔半导体公司 | Data processing system having multiple register contexts and method therefor |
| US20120030392A1 (en) * | 2010-07-30 | 2012-02-02 | Mips Technologies, Inc. | System and Method for Automatic Hardware Interrupt Handling |
| JP2013164791A (en) * | 2012-02-13 | 2013-08-22 | Denso Corp | Data processor |
| CN105144100A (en) * | 2013-03-12 | 2015-12-09 | 密克罗奇普技术公司 | Programmable CPU register hardware context swap mechanism |
| CN106020017A (en) * | 2016-05-16 | 2016-10-12 | 深圳清华大学研究院 | Microcontroller and control method thereof |
-
2019
- 2019-11-20 CN CN201911140297.0A patent/CN110928574A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996008948A2 (en) * | 1994-09-19 | 1996-03-28 | Philips Electronics N.V. | Method and apparatus for fast microcontroller context switching |
| US6128728A (en) * | 1997-08-01 | 2000-10-03 | Micron Technology, Inc. | Virtual shadow registers and virtual register windows |
| US5987495A (en) * | 1997-11-07 | 1999-11-16 | International Business Machines Corporation | Method and apparatus for fully restoring a program context following an interrupt |
| CN1856770A (en) * | 2002-05-31 | 2006-11-01 | 飞思卡尔半导体公司 | Data processing system having multiple register contexts and method therefor |
| US20120030392A1 (en) * | 2010-07-30 | 2012-02-02 | Mips Technologies, Inc. | System and Method for Automatic Hardware Interrupt Handling |
| JP2013164791A (en) * | 2012-02-13 | 2013-08-22 | Denso Corp | Data processor |
| CN105144100A (en) * | 2013-03-12 | 2015-12-09 | 密克罗奇普技术公司 | Programmable CPU register hardware context swap mechanism |
| CN106020017A (en) * | 2016-05-16 | 2016-10-12 | 深圳清华大学研究院 | Microcontroller and control method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 孙康;沈海斌;王继民;潘雪增;: "基于映像寄存器构建的实时操作系统内核", 清华大学学报(自然科学版), no. 2, pages 1899 - 1902 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114328323A (en) * | 2021-12-01 | 2022-04-12 | 北京三快在线科技有限公司 | Data transfer unit and data transmission method based on data transfer unit |
| CN114978965A (en) * | 2022-05-25 | 2022-08-30 | 中国第一汽车股份有限公司 | CAN diagnosis message and network message processing method and system under high-load condition of chip, electronic device and storage medium |
| CN117555599A (en) * | 2024-01-10 | 2024-02-13 | 睿思芯科(成都)科技有限公司 | Chip design method, system and related equipment for accelerating key data access speed |
| CN117555599B (en) * | 2024-01-10 | 2024-04-05 | 睿思芯科(成都)科技有限公司 | Chip design method, system and related equipment for accelerating key data access speed |
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