CN117331762A

CN117331762A - Test method, device, equipment and medium for link training of PCIe equipment

Info

Publication number: CN117331762A
Application number: CN202311264883.2A
Authority: CN
Inventors: 刘青松; 聂华; 王马俊
Original assignee: Zhongke Controllable Information Industry Co Ltd
Current assignee: Zhongke Controllable Information Industry Co Ltd
Priority date: 2023-09-27
Filing date: 2023-09-27
Publication date: 2024-01-02

Abstract

The invention discloses a test method, a test device, test equipment and test media for link training of PCIe equipment. The method comprises the following steps: acquiring a configuration file, wherein the configuration file comprises test time, equipment type to be tested and the number of equipment to be tested, and the test equipment comprises PCIe equipment; obtaining addresses of the devices to be tested according to the number of the devices to be tested and the types of the devices to be tested, and obtaining slot positions of the devices to be tested according to the addresses of the devices to be tested; modifying the power supply state of the slot of the device to be tested to circularly execute link training of the PCIe device, and generating a test report according to the link information of the PCIe device. According to the embodiment of the invention, the automatic test of the link training of the PCIe equipment can be realized, and the manpower and material resources required by the test are saved; meanwhile, single/multiple PCIe devices can be controlled to train simultaneously, the test cost is saved, the test efficiency and the accuracy are improved, and further, the technical scheme of the invention can automatically generate the test report after training is finished, so that the staff can conveniently know the test process.

Description

Test method, device, equipment and medium for link training of PCIe equipment

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a medium for testing link training of PCIe devices.

Background

PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard, PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and connected devices allocate exclusive channel bandwidths and do not share bus bandwidths, and mainly support functions such as active power management, error reporting, end-to-end reliability transmission, hot plug, quality of service and the like. With the rapid development of PCIe technology application, PCIe terminal devices of various specifications are coming along, which makes the requirements on the stability of PCIe links higher and higher, and because the server needs to provide high-speed CPU operation capability, long-time reliable operation, strong I/O external data throughput capability, and better expandability, the necessary test is required for the link stability of PCIe devices of OCP 3.0 (Open Compute Project, open computing project) protocol connected to the server.

The link stability test of PCIe devices can be generally performed in two manners, the first is a violent hot plug manner, specifically: the working personnel directly carries out hot plug on PCIe equipment on the server, namely the equipment is pulled out of the server, then the equipment is inserted into the original position, and the power-on or power-off operation of the equipment is realized in continuous plug, so that the training process of the PCIe link is finished; the second mode is to perform power-down and power-up operations on a server where the PCIe equipment is located, so that the PCIe link training process is completed, and meanwhile, after the training process is finished, recording and summarizing of the training process are performed manually.

Both the two test modes need manual power-on and power-off operation on equipment or a server, a large amount of time is consumed, the efficiency is not improved, meanwhile, due to uncertainty of manual operation, the two test modes have large test errors, the accuracy of a final test result is low, and further, a large amount of manpower and material resources are consumed in the manual recording training process.

Disclosure of Invention

The invention provides a test method, a device, equipment and a medium for link training of PCIe equipment, which can automatically test the link training of one or more OCP3.0PCIe equipment, improve the test speed and accuracy, and simultaneously, the method can automatically generate a test report according to the training process of the PCIe equipment, thereby saving manpower and material resources.

In a first aspect, an embodiment of the present invention provides a method for testing link training of a PCIe device, including:

acquiring a configuration file, wherein the configuration file comprises test time, equipment type to be tested and the number of equipment to be tested, and the equipment to be tested comprises PCIe equipment;

obtaining addresses of the devices to be tested according to the number of the devices to be tested and the types of the devices to be tested, and obtaining slot positions of the devices to be tested according to the addresses of the devices to be tested;

Modifying the power supply state of the slot of the device to be tested to circularly execute link training of the PCIe device, and generating a test report according to the link information of the PCIe device.

Optionally, the obtaining the address of the device to be tested according to the number of the devices to be tested and the type of the device to be tested includes:

starting a corresponding number of threads according to the number of the devices to be tested, and distributing the threads to each device to be tested;

and addressing PCIe equipment according to the type of the equipment to be tested by the thread to obtain the address of the equipment to be tested.

By the scheme, the parallel execution of PCIe device addressing by simultaneously starting a plurality of threads is realized, the device address to be tested is obtained, and the addressing efficiency is improved.

Optionally, before obtaining the slot position of the device to be tested according to the address of the device to be tested, the method further includes:

acquiring initial link information of PCIe equipment according to the address of the equipment to be tested;

comparing the initial link information with system performance evaluation test parameters, and judging whether the link information meets the system performance evaluation test standard according to a comparison result;

if yes, the power supply state of the slot position of the equipment to be tested is modified to circularly execute the PCIe equipment link training step.

Through the scheme, when the initial link information meets the system performance evaluation test standard, the link training test of the PCIe equipment is executed, so that the waste of computing resources caused by the link training test under the condition of link errors is avoided.

Optionally, the modifying the power supply state of the slot of the device to be tested to perform PCIe device link training in a circulating manner includes:

the power state of the slot position of the equipment to be tested is rewritten, so that the link of the PCIe equipment circularly executes the step of powering down and powering up again;

and executing the link training of the PCIe device once through a link training state machine under the condition that the link of the PCIe device is powered down and powered up every time.

Through the scheme, the link of the PCIe device is circularly electrified after the power-down is circularly executed so as to trigger the link training, the link training of the PCIe device is automatically triggered, and a convenient and efficient mode for triggering the link training of the PCIe device is provided.

Optionally, the generating the test report according to the link information of the PCIe device includes:

and under the condition that the test time is met, stopping modifying the power supply state of the slot of the equipment to be tested, and generating a test report according to the link information corresponding to each PCIe equipment link training.

Through the scheme, the link training test is stopped by stopping modifying the power supply state of the slot of the equipment to be tested, so that the link training of the PCIe equipment is finished conveniently and efficiently.

when the link of the PCIe device is powered down, if the link information of the PCIe device is acquired, determining that the test fails;

judging whether to finish the test according to the current test failure times;

if yes, generating a test report according to link information corresponding to each PCIe device link training.

Through the scheme, the link training test mode of stopping the link training test by the test failure times is adopted, so that the link training of the PCIe equipment is finished conveniently and efficiently.

Optionally, the generating the test report according to the link information corresponding to each PCIe device link training includes:

for each PCIe device link training, if the link of the PCIe device is electrified, link information of the PCIe device is not acquired, and a link training result is determined to be a training failure;

if the link information of the PCIe device is acquired and does not meet the system performance evaluation test standard when the link of the PCIe device is electrified, determining that the link training result is a training failure;

If the link information of the PCIe device is acquired and meets the system performance evaluation test standard when the link of the PCIe device is electrified, determining that the link training result is successful;

and generating a test report according to the link training result.

By the scheme, the test report is automatically generated according to the link training result of each link training, and the generation efficiency and accuracy of the test report are improved.

In a second aspect, an embodiment of the present invention provides a test apparatus for link training of a PCIe device, including:

the device comprises a configuration file acquisition module, a configuration file generation module and a configuration file generation module, wherein the configuration file comprises test time, device types to be tested and the number of devices to be tested, and the devices to be tested of the test devices comprise PCIe devices;

the device address acquisition module acquires the device address to be tested according to the number of the devices to be tested and the types of the devices to be tested, and acquires the slot position of the devices to be tested according to the device address to be tested;

and the device link training module is used for modifying the power supply state of the device slot to be tested to circularly execute the link training of the PCIe device and generating a test report according to the link information of the PCIe device.

Optionally, the device address acquisition module is specifically configured to:

Optionally, the apparatus further includes a link information comparing module configured to:

before the slot position of the equipment to be tested is obtained according to the address of the equipment to be tested, obtaining initial link information of PCIe equipment according to the address of the equipment to be tested;

Optionally, the device link training module is specifically configured to:

Optionally, the device link training module is further specifically configured to:

judging whether to finish the test according to the current test failure times;

And generating a test report according to the link training result.

In a third aspect, an embodiment of the present invention provides an electronic device, including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the test method of PCIe device link training of any of the embodiments of the present invention.

In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium comprising:

the computer readable storage medium stores computer instructions for causing the processor to implement the test method for PCIe device link training of any one of the embodiments of the present invention when executed.

The embodiment of the invention provides a test method, a device, equipment and a medium for training a link of PCIe equipment, which are used for acquiring the address and link information of the equipment to be tested by acquiring the configuration file of the equipment to be tested, determining the specific slot position of the equipment to be tested on a main board, further automatically testing the training process of the PCIe equipment, automatically generating a test report after the training is finished, improving the accuracy of the training test of the link of the PCIe equipment, improving the test efficiency, further automatically generating the test report after the training is finished, and reducing the consumption of manpower and material resources.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flowchart of a test method for training a link of a PCIe device according to an embodiment of the present invention;

FIG. 2 is a flowchart of a test method for training a link of a PCIe device according to an embodiment of the present invention;

FIG. 3 is a flowchart of a test method for training a link of a PCIe device according to an embodiment of the present invention;

FIG. 4 is a flowchart of a testing method for link training of PCIe devices according to an embodiment of the present invention;

FIG. 5 is a flowchart of a test method for PCIe device link training provided by an embodiment of the present invention;

FIG. 6 is a flowchart of a test method for PCIe device link training provided by an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a test device for PCIe device link training according to an embodiment of the present invention;

Fig. 8 shows a schematic diagram of the structure of an electronic device that may be used to implement an embodiment of the invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a flowchart of a testing method for link training of PCIe devices, which is provided by the embodiment of the present invention, where the embodiment mode may be suitable for implementing an automatic testing situation of link training of PCIe devices, so as to help staff to improve accuracy and efficiency of testing of link training of PCIe devices. The method may be performed by a test device for link training of PCIe devices, where the device may be implemented in hardware and/or software, and the test device for link training of PCIe devices may be configured in various servers, communication and data transmission devices, which is not limited in this embodiment.

As shown in fig. 1, the method includes:

step 110, acquiring a configuration file, wherein the configuration file comprises test time, device types to be tested and the number of devices to be tested, and the devices to be tested of the test device comprise PCIe devices.

The configuration file is a necessary file required before testing the PCIe device, and includes necessary information required for testing, such as testing time, type of device to be tested, and number of devices to be tested.

Specifically, the test time may be a total duration of single/multiple tests, and multiple specific tests may be included in the test time; the type of the device to be tested can be understood as PCIe devices which can be installed on a server through a slot of a server main board, network card devices, other input/output devices and the like; the number of devices to be tested is understood to be the total number of devices that are simultaneously involved in the test. If multiple types of devices to be tested are tested simultaneously, the number of the devices to be tested is the sum of the number of the devices to be tested.

Alternatively, the test may be performed simultaneously by calling a specific function so that the plurality of devices to be tested do not affect each other.

And 120, acquiring an address of the equipment to be tested according to the number of the equipment to be tested and the type of the equipment to be tested, and acquiring a slot position of the equipment to be tested according to the address of the equipment to be tested.

The device address to be tested can be understood as unique characteristic information of each PCIe device to be tested, and the device address to be tested can be obtained through a hardware query instruction. The slot position of the device to be tested is the specific position of the corresponding slot of the device to be tested on the server main board.

Specifically, the number of the devices to be tested and the types of the devices to be tested can be obtained through the configuration file, and then the corresponding addresses of the devices to be tested can be obtained according to the types of the devices to be tested of each device to be tested and the protocol standards corresponding to the types, and the specific slot positions of the devices to be tested on the main board can be finally obtained by adopting the setting instruction based on the addresses of the devices to be tested. If a plurality of devices to be tested exist according to the number of the devices to be tested, the addresses of the devices to be tested corresponding to the devices to be tested are obtained in parallel by referring to the specific function, and then the operation of determining the slot positions of the devices to be tested according to the addresses of the devices to be tested is executed in parallel.

And 130, modifying the power supply state of the slot of the device to be tested to circularly execute link training of the PCIe device, and generating a test report according to the link information of the PCIe device.

The power supply state can be understood as the power-on condition of the slot position of the equipment to be tested, such as power-on or power-off. Because the link training is automatically completed by the link training state machine, the functions of bit locking, character locking, block locking, link width determination, channel position inversion, signal polarity inversion, data rate of the link, channel alignment and the like are completed in the process of executing the link training each time. The link information may characterize relevant information of the PCIe device link, and stability of the PCIe device link is characterized by the link information. Furthermore, the training process and the result of the PCIe device can be obtained by analyzing the link information.

Optionally, the link training of the PCIe device is a link training method, by initializing a physical layer, port configuration information, a transmitting and receiving module, and a related link state of the PCIe link, and knowing a topology structure of an opposite end of the link, so as to achieve functions of bit locking, character locking, block locking, determining a link width, channel position inversion, signal polarity inversion, determining a data rate and channel alignment of the link, and finally, letting devices at two ends of the PCIe link perform a data communication process. The test report is a report document generated by the end of the test, and the process information of each training in each test is recorded.

In the embodiment of the invention, the test can be ended when the test time is reached. Alternatively, the test may be ended when the number of test failures satisfies the test ending condition, and the present invention is not limited to the test ending condition.

Specifically, through automatic modification of the power supply state of the slot of the device to be tested, the link training of the PCIe device can be circularly executed through the link training state machine, the training process and information of each training can be written into the test report, and the test report is sent to the staff when the test time is over.

According to the technical scheme, by acquiring the configuration file of the equipment to be tested, the automatic test of a single equipment through a test tool is realized, and the automatic test of a plurality of equipment can be realized at the same time; the link information is determined through the address of the equipment to be tested, and the cyclic test is automatically performed, so that the accuracy and the speed of the test are improved, and the test time is saved; finally, when the test is completed, a test report is generated, so that a worker can accurately acquire details and test results in each test process, the test flow is normalized, and the acquisition of the test process and the results is simplified.

Fig. 2 is a flowchart of a testing method for PCIe device link training provided by an embodiment of the present invention, where the method for obtaining an address of a device to be tested and the specific method for obtaining a slot of the device to be tested are further defined based on the above embodiments, and may be combined with the above embodiments.

As shown in fig. 2, includes:

step 210, acquiring a configuration file, wherein the configuration file comprises test time, device types to be tested and the number of devices to be tested, and the devices to be tested of the test device comprise PCIe devices.

And 220, starting a corresponding number of threads according to the number of the devices to be tested, and distributing the threads to each device to be tested.

The thread is the minimum unit for operation scheduling, and it can be understood that when multiple devices are tested simultaneously, the tests on different devices to be tested are realized through different threads, so that each device needs to be independently allocated with a thread to execute the test, and the test of link training is performed without mutual influence among the multiple devices.

Optionally, after different devices to be tested are inserted into the server motherboard, corresponding required threads are started according to the number of the devices to be tested, and link training tests of the devices to be tested are executed in parallel through the threads so as to meet test requirements.

And 230, addressing PCIe equipment by the thread according to the type of the equipment to be tested to obtain the address of the equipment to be tested.

It can be understood that, because the different types of devices to be tested have different addressing modes due to different protocol contents, PCIe device addressing is required to be performed by threads according to the corresponding protocols according to the specific types of the devices to be tested, so as to obtain addresses of the devices to be tested.

Step 240, obtaining initial link information of the PCIe device according to the device address to be tested.

Specifically, after determining the address of the device to be tested and the corresponding protocol, the test tool addresses the corresponding PCIe address according to the type of the device to be tested, so as to obtain the PCIe address, and further, the specific instruction function may process the obtained address character, intercept key information in the address, and use the key information as required link information. Initial link information is determined from the intercepted link information and the PCIe device address.

Step 250, comparing the initial link information with the system performance evaluation test parameters, and judging whether the link information meets the system performance evaluation test standard according to the comparison result, if yes, executing step 260, otherwise, executing step 270.

The system performance evaluation test parameters are standard parameters for evaluating the performance of the server system, for example, the system performance evaluation test parameters include standard parameters corresponding to PCIe link information.

Specifically, before the device to be tested is tested, the initial link information is compared with the system performance evaluation test parameters, when the initial link information meets the system performance evaluation test parameters, the initial link information meets the requirements of the test, the device to be tested can be tested, and otherwise, the device to be tested cannot be tested.

And 260, modifying the power supply state of the slot of the device to be tested to circularly execute link training of the PCIe device, and generating a test report according to the link information of the PCIe device.

The cyclic execution may be understood as repeatedly modifying the power supply state of the device to be tested, and may include cyclically powering down and powering up the slot of the device to be tested. And triggering a link training state machine to automatically perform link training by electrifying the end points of the slot positions of the equipment to be tested.

Specifically, when the link information meets the system performance evaluation test parameters, the power supply state of the slot of the equipment to be tested is changed in a cyclic manner by the link training state machine, so that the power supply state of the equipment to be tested is controlled, the link training state machine is triggered in a cyclic manner to automatically perform link training, and PCIe link information is acquired in each link training process.

Optionally, after the training reaches the preset test time, the training is ended.

Step 270, end.

According to the embodiment of the invention, the configuration files are obtained, the corresponding number of threads are started according to the number of the devices to be tested, the threads are distributed to each device to be tested, PCIe device addressing is further carried out through the types of the devices to be tested, and the addresses of the devices to be tested are obtained, so that the specific positions of the devices to be tested on a server main board can be quickly and accurately determined by the addressing mode, and the addressing efficiency is improved; furthermore, link information of the PCIe device is obtained through the address of the device to be tested, the initial link information is compared with system performance evaluation test parameters, if the initial link information meets the system performance evaluation test parameters, repeated automatic test can be started, a link training state machine can circularly execute link training steps of the PCIe device, the automatic test mode of the link training of the PCIe device is beneficial to saving manpower and material resources required by the test, the test accuracy is improved, the test efficiency is improved, and finally, when the test is finished, a test report is automatically generated according to the link information of the PCIe device in each test, and the automatic generation mode is beneficial to standardizing the test flow and improving the acquisition efficiency of test results by testers.

Fig. 3 is a flowchart of a test method for PCIe device link training provided by an embodiment of the present invention. The present embodiment further defines a PCIe device link training method based on the above embodiments, and may be combined with the above embodiments.

As shown in fig. 3, the method includes:

step 310, a configuration file is obtained, wherein the configuration file comprises test time, device types to be tested and the number of devices to be tested, and the devices to be tested of the test device comprise PCIe devices.

Step 320, starting a corresponding number of threads according to the number of the devices to be tested, and distributing the threads to each device to be tested.

And 330, performing PCIe device addressing according to the type of the device to be tested through the thread to obtain the address of the device to be tested.

And 340, acquiring initial link information of the PCIe device according to the address of the device to be tested.

Before the power supply state of the slot position of the equipment to be tested is modified, setting information in the address of the equipment to be tested is obtained, and the obtained setting information and the address of the equipment to be tested are used as initial link information.

And step 350, comparing the initial link information with the system performance evaluation test parameters, judging whether the link information meets the system performance evaluation test standard according to the comparison result, if so, executing step 360, otherwise, executing step 390.

Step 360, the power state of the slot of the device to be tested is rewritten, so that the link of the PCIe device is circularly powered down and then powered up.

The method comprises the steps that each equipment slot to be tested has an independent power state, the power state of each equipment slot to be tested can be powered on or powered off through a rewriting operation, and then the power-off step is performed on a link of PCIe equipment in a circulating mode through a circulating rewriting operation.

Step 370, performing PCIe device link training once through a link training state machine under the condition that the PCIe device link is powered down and powered up each time.

The link training state machine is used for carrying out link training on the PCIe device, and the link training state machine is used for carrying out link power-down and power-up operation on the PCIe device.

And 380, under the condition that the test time is met, stopping modifying the power supply state of the slot of the equipment to be tested, and generating a test report according to the link information corresponding to each PCIe equipment link training.

The satisfaction of the test time is understood to mean that the set test time must not be exceeded within a prescribed test time range.

Specifically, under the condition that the test time is met, the power supply state of the slot of the device to be tested is stopped being modified, and in the stop time, a test report is generated according to link information corresponding to link training of the PCIe device, wherein the test report comprises all detail contents of the training.

Optionally, for each link training of the PCIe device, if the link of the PCIe device is powered on, link information of the PCIe device is not obtained, and a link training result is determined to be a training failure; if the link information of the PCIe device is acquired and does not meet the system performance evaluation test standard when the link of the PCIe device is electrified, determining that the link training result is a training failure; if the link information of the PCIe device is acquired and meets the system performance evaluation test standard when the link of the PCIe device is electrified, determining that the link training result is successful; and generating a test report according to the link training result.

The test tool generates a test report according to link information corresponding to each PCIe device link training under the condition that the test time is met, automatically trains the PCIe devices by changing power supply states in an automatic cycle after the test report is generated, automatically generates a corresponding test report for each training, finishes all the training after the test time is reached, sorts all training processes and result details in the test time into the test report, and sends the test report to a tester.

Step 390, end.

According to the embodiment of the invention, the configuration file is obtained, the address of the equipment to be tested is obtained according to the configuration file, and the slot position of the equipment to be tested is obtained according to the address of the equipment to be tested, so that the specific position of the equipment to be tested on the server can be rapidly determined; the power state of the slot position of the equipment to be tested is rewritten through the link training state machine, the step of powering up after powering down is circularly executed by the link of the PCIe equipment is controlled, and the training step is circularly executed through the equipment to be tested, so that a quick and efficient training process is realized, and manpower and material resources are saved. Specifically, under the condition that the test time is met, the power supply state of the slot position of the equipment to be tested is stopped being modified, and a test report is automatically generated according to link information corresponding to link training of PCIe equipment each time, so that the test efficiency can be improved, the test work can be standardized, and the test staff can be helped to reduce the reading burden.

Fig. 4 is a flowchart of a test method for link training of a PCIe device according to an embodiment of the present invention, where the embodiment further defines a specific manner of generating a test report according to link information of the PCIe device based on the foregoing embodiments, and may be combined with the foregoing embodiments.

As shown in fig. 4, includes:

step 410, obtaining a configuration file, wherein the configuration file comprises test time, device type to be tested and number of devices to be tested, and the devices to be tested of the test device comprise PCIe devices.

And step 420, obtaining the addresses of the devices to be tested according to the number of the devices to be tested and the types of the devices to be tested, and obtaining the slot positions of the devices to be tested according to the addresses of the devices to be tested.

And 430, circularly executing the step of powering down and powering up the link of the PCIe device by rewriting the power state of the slot of the device to be tested.

Step 440, performing PCIe device link training once through a link training state machine each time the PCIe device link is powered down and powered up.

And 450, when the link of the PCIe device is powered down, if the link information of the PCIe device is acquired, determining that the test fails.

Specifically, when the link of the PCIe device is powered down, the PCIe device is disconnected from the server, if the link information of the PCIe device is obtained, it is proved that a link failure may occur, and the test failure is determined.

Step 460, judging whether to end the test according to the current test failure times, if yes, executing step 470, otherwise executing step 430.

The test failure times are the sum of the test failure times in the test time.

Specifically, whether to end the test can be determined by judging a preset test failure threshold, and the test failure threshold can be understood as that if the number of test failures is greater than the test failure threshold in the prediction time, the test is ended, that is, the test tool has a certain fault tolerance, and all the tests cannot be directly ended due to the failure of a single test.

And 470, generating a test report according to the link information corresponding to each PCIe device link training.

Specifically, when the number of test failures is greater than the test failure threshold, the test is ended, a test report is generated according to link information corresponding to each PCIe device link training, and the test report is sent to staff

According to the embodiment of the invention, when the link of the PCIe device is powered down, if the link information of the PCIe device is acquired, the test is determined to fail, and when the number of times of the test failure is larger than the test failure threshold value, the test is ended, and the method for ending the test is convenient for ending the test in time when the test fails for a plurality of times, so that the link training of the PCIe device is ended conveniently and efficiently.

Fig. 5 is a flowchart of a test method for link training of a PCIe device according to an embodiment of the present invention, where the method may be combined with the foregoing embodiments and implemented as a separate solution.

As shown in fig. 5, includes:

step 510, installing required test software and hardware on the server.

The hardware required by the test comprises equipment to be tested, such as various hardware required by the test, and the like, and the equipment to be tested comprises PCIe equipment.

Illustratively, before the tester performs PCIe device testing, it is necessary to configure the environment required for testing on the server, and install necessary software applications required for the testing, such as installing a corresponding Python version; meanwhile, PCIe devices of OCP3.0 specification required for testing need to be installed outside the server. The software and hardware requirements for testing are met through the installation of necessary software inside the server and the installation of necessary hardware outside the server.

Step 520, specific parameters of the configuration file are set.

Optionally, due to the number of devices to be tested, the types of devices to be tested, and the testing time are different, specific parameters in the configuration file need to be determined before testing.

Optionally, the testing tool may provide a configuration file before testing, and the tester needs to configure testing parameters in the configuration file, and through setting the testing parameters, specific information such as the testing time, the type of the device to be tested, and the number of the devices to be tested at this time will be determined.

Step 530, the server runs the link training state machine.

Optionally, the PCIe link training is in the physical layer of the PCIe link, and by initializing the physical layer of the PCIe link, port configuration information, a sending and receiving module, and a state of a related link, the whole process of data communication is finally performed by devices at two ends of the PCIe link, and the whole process can be automatically completed by a test tool. Specifically, before the PCIe link can communicate normally, the PCIe device is trained by the link training state machine, so as to achieve functions of bit locking, character locking, block locking, determining a link width, channel position inversion, signal polarity inversion, determining a data rate of the link, channel alignment, and the like.

And step 540, after the test is completed, a test report is generated and sent to staff.

According to the embodiment of the invention, the quantity and the type of the equipment to be tested can be set by installing software and hardware required by the test and setting the parameters of the configuration file, and the PCIe address of the equipment to be tested can be rapidly determined by analyzing the configuration file; furthermore, the test tool is operated, and through the cyclic power-on and power-off operation of the equipment slot position, the equipment to be tested can be subjected to automatic test training through the test tool, so that manpower and material resources required by the test are saved, and the test accuracy and efficiency are improved; when the test time is reached, the test is finished, a test report is generated and sent to the staff, so that the staff can quickly know the test result, the test process is normalized, and the time for the staff to acquire the test process is saved.

Fig. 6 is a flowchart of a testing method for PCIe device link training according to an embodiment of the present invention, where the method specifically defines a manner according to the number of devices to be tested and a manner for PCIe device link training, and may be combined with the foregoing embodiments.

As shown in fig. 6, includes:

step 601, acquiring a configuration file.

Optionally, the configuration file includes a test time, a type of a device to be tested, and a number of devices to be tested, where the device to be tested includes a PCIe device.

Step 602, determining whether the device to be tested is tested simultaneously according to the configuration file, if so, executing step 603, otherwise, executing step 604.

If multiple devices to be tested are tested simultaneously, step 603 is executed, where multiple devices to be tested are tested simultaneously; otherwise, step 604 is performed, where the single device under test is tested individually.

Step 603, obtaining PCIe addresses of each device in the plurality of devices to be tested, and executing step 605.

Step 604, obtaining the PCIe address of the single device to be tested, and executing step 606.

Specifically, PCIe device address addressing may be performed through specific instructions in the test tool script, and exemplary PCIe address related information may be obtained through an operation instruction lspci|grep-ixxx. Furthermore, the specific slot of the PCIe device on the server can be obtained according to the PCIe address and the lspci-s PCIe Addr-vvv|grep-i slot.

Step 605, determining whether the initial link information of the plurality of devices to be tested accords with the system performance evaluation test parameters, if yes, executing step 607, otherwise, executing step 611.

Step 606, determining whether the link information of the single device to be tested accords with the system performance evaluation test parameters, if yes, executing step 607, otherwise, executing step 611.

Specifically, the initial link information is compared with the system performance evaluation test parameters, and if the system performance evaluation test parameter conditions are met, the initial link information is indicated to meet the test requirements, and the test can be performed.

In step 607, the test tool sets a power state of the slot of the device to be tested corresponding to the PCIe address of the device to be tested.

Illustratively, the power state of the device slot to be tested may be checked by a corresponding instruction of the test tool, such as by over-instruction cat/sys/bus/pcb/slots/< The physical slot of xxxx Device >/power.

Step 608, performing link training of the PCIe device through the link training state machine.

Specifically, the power state of the corresponding slot of the device to be tested can be changed through the link training state machine, for example, the power-on state and the power-off state of the slot can be respectively corresponding to 1 and 0, when the power state of the slot is equal to 0, the power-on state is indicated to be the power-off state, if the link information of the PCIe device can be acquired in the server operating system at the moment, the link is indicated to be possibly faulty, the test fails, when the power state of the slot is equal to 1, the power-on state is indicated to be the power-on state at the moment, and if the link information of the PCIe device cannot be acquired in the server operating system at the moment, the link is indicated to be possibly faulty, and the training fails.

Step 609, judging whether the test time is exceeded, if yes, executing step 610, otherwise, returning to execute step 607.

If the test time is not exceeded, returning to step 607, where the test tool sets a power state of the slot of the device to be tested corresponding to the PCIe address of the device to be tested; if the test time is exceeded, step 610 is performed.

Step 610, a test report is generated and sent to the staff.

When the training time exceeds the preset test time parameter in the configuration file, the test is stopped at the moment when the test time reaches the preset upper limit, the power supply state of the slot of the equipment to be tested is stopped, all test results are integrated into a test report, and the test report is sent to a mailbox of a tester.

Step 611, end.

According to the embodiment of the invention, the configuration file is obtained, the number of the devices to be tested is obtained according to the configuration file, then the device address is obtained in an addressing mode, and finally the slot position of the devices to be tested on the main board is obtained, so that the specific position of the devices to be tested on the server can be rapidly determined in the mode; meanwhile, after the PCIe address of the device is obtained, whether the link information of the device to be tested accords with the system performance evaluation test parameters is judged, and if so, a test tool is started to start the test. Specifically, the test tool controls the link of the PCIe device to circularly execute the step of powering down and then powering up by rewriting the power state of the slot of the device to be tested, and circularly execute the training step by the device to be tested, thereby realizing a rapid and efficient automatic training process and saving manpower and material resources. Under the condition that the test time is met, the power supply state of the slot position of the equipment to be tested is stopped being modified, and a test report is automatically generated according to link information corresponding to link training of PCIe equipment each time, so that test work can be standardized, and the test staff can be helped to reduce reading burden.

Fig. 7 is a schematic structural diagram of a test apparatus for PCIe device link training according to an embodiment of the present invention, which may be used to execute a test method for PCIe device link training according to each embodiment of the present invention, where the apparatus specifically includes: a profile acquisition module 710, a device address acquisition module 720, and a device link training module 730.

The profile acquisition module 710 is configured to: and acquiring a configuration file, wherein the configuration file comprises test time, equipment type to be tested and the number of the equipment to be tested, and the equipment to be tested comprises PCIe equipment.

Optionally, the file obtaining module 710 includes a read-write unit, which is configured to set parameters in the configuration file.

The device address acquisition module 720 is configured to: and obtaining the addresses of the devices to be tested according to the number of the devices to be tested and the types of the devices to be tested, and obtaining the slot positions of the devices to be tested according to the addresses of the devices to be tested.

Optionally, the device address obtaining module 720 includes: thread allocation unit, PCIe device addressing unit.

Wherein the thread allocation unit is configured to: and starting a corresponding number of threads according to the number of the devices to be tested, and distributing the threads to each device to be tested.

The PCIe device addressing unit is configured to: and addressing PCIe equipment by the thread according to the type of the equipment to be tested to obtain the address of the equipment to be tested.

Further, the device address obtaining module 720 may further include: the system comprises a link information acquisition unit, a standard comparison unit and a training execution unit.

Wherein, the link information acquisition unit is used for: and acquiring initial link information of the PCIe device according to the address of the device to be tested.

The standard comparison unit is used for: and comparing the initial link information with the system performance evaluation test parameters, and judging whether the link information meets the system performance evaluation test standard according to the comparison result.

The training execution unit is used for: and if the comparison result judges that the link information meets the system performance evaluation test standard, executing the power supply state of the slot of the equipment to be tested so as to circularly execute the link training step of the PCIe equipment.

The device link training module 730 is configured to: modifying the power supply state of the slot of the device to be tested to circularly execute link training of the PCIe device, and generating a test report according to the link information of the PCIe device.

Optionally, the device link training module 730 includes: and the cyclic training unit is used for generating a test report.

Wherein, the cyclic training unit is used for: modifying the power state of the device slot to be tested to cycle through PCIe device link training.

The cyclic training unit may include: and the power state control subunit trains the execution subunit.

The power state control subunit is configured to: and (3) circularly executing the step of powering down and powering up the link of the PCIe device by rewriting the power state of the slot of the device to be tested.

The training execution subunit is configured to: and performing link training of the PCIe device once through a link training state machine under the condition that the link of the PCIe device is powered down and powered up every time.

The test report generating unit is used for: and under the condition that the test time is met, stopping modifying the power supply state of the slot of the equipment to be tested, and generating a test report according to the link information corresponding to each PCIe equipment link training.

Optionally, the test report generating unit includes: the test failure determining subunit, the judging subunit and the test failure test reporting subunit.

The test failure determination subunit is configured to: when the link of the PCIe device is powered down, if the link information of the PCIe device is acquired, determining that the test fails.

The judging subunit is used for: and judging whether to finish the test according to the current test failure times.

The test failure test report subunit is configured to: if the current test failure times are greater than the preset test failure threshold, generating a test report according to link information corresponding to each PCIe device link training.

Further, the test report generating unit further includes a training failure judging unit.

The training failure judging unit is used for judging whether training fails to generate a corresponding test report.

For each PCIe device link training, if the link of the PCIe device is powered on, link information of the PCIe device is not acquired, and a link training result is determined to be a training failure;

if the link information of the PCIe device is acquired and does not meet the system performance evaluation test standard when the link of the PCIe device is powered on, determining that the link training result is training failure;

and generating a test report according to the link training result.

The device to be tested for the link training of the PCIe device provided by the embodiment of the invention can execute any test method for the link training of the PCIe device in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Fig. 8 shows a schematic structural diagram of an electronic device 800 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 8, the electronic device 800 includes at least one processor 801, and a memory such as a Read Only Memory (ROM) 802, a Random Access Memory (RAM) 803, etc., communicatively connected to the at least one processor 801, wherein the memory stores a computer program executable by the at least one processor, and the processor 801 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 802 or the computer program loaded from the storage unit 808 into the Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The processor 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

Various components in electronic device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the electronic device 800 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The processor 801 may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples of processor 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 801 performs the various methods and processes described above, such as a test method for PCIe device link training.

In some embodiments, a method of testing link training of a PCIe device may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 800 via the ROM 802 and/or the communication unit 809. When the computer program is loaded into RAM 803 and executed by processor 801, one or more steps of a test method for PCIe device link training described above may be performed. Alternatively, in other embodiments, processor 801 may be configured by any other suitable means (e.g., by means of firmware) to perform a test method of PCIe device link training.

Various implementations of the systems and techniques described here above can be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A method for testing link training of PCIe devices, comprising:

obtaining addresses of equipment to be tested according to the number of the equipment to be tested and the type of the equipment to be tested, and obtaining slot positions of the equipment to be tested according to the addresses of the equipment to be tested;

Modifying the power supply state of the slot position of the device to be tested to circularly execute link training of the PCIe device, and generating a test report according to the link information of the PCIe device.

2. The method of claim 1, wherein the obtaining the device address to be tested according to the number of devices to be tested and the type of devices to be tested comprises:

3. The method of claim 1, further comprising, prior to obtaining the device slot to be tested from the device address to be tested:

4. The method of claim 1, wherein modifying the power state of the device slot under test to cycle through PCIe device link training comprises:

5. The method of claim 4, wherein generating the test report from link information of the PCIe device comprises:

6. The method of claim 4, wherein generating the test report from link information of the PCIe device comprises:

judging whether to finish the test according to the current test failure times;

7. The method of claim 5 or 6, wherein generating the test report based on the link information corresponding to each PCIe device link training comprises:

and generating a test report according to the link training result.

8. A test apparatus for link training of a PCIe device, comprising:

9. An electronic device, characterized in that the electronic device comprises:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the test method of PCIe device link training of any one of claims 1-7.

10. A computer readable storage medium having stored thereon computer instructions for causing a processor to perform the test method of PCIe device link training of any one of claims 1-7 when executed.