CN117234820A - An automated testing method for SoC array server and SoC array server - Google Patents

Abstract

The embodiment of the invention discloses an automatic test method of an SoC array server, which is applied to a BMC main board in the SoC array server, wherein the SoC array server also comprises a back plate, a blade plate and a switching plate, the back plate comprises a back plate controller and a fan controller, and the fan controller is connected with a plurality of fans; the blade board comprises a blade board controller, an SoC board card and a serial port controller. The method specifically comprises the following steps: and enabling the backboard controller, the fan, the blade board controller, the SoC board card, the serial port controller and the exchange board to work normally respectively, setting preset duration and preset range to verify the backboard controller, the fan, the blade board controller, the SoC board card, the serial port controller and the exchange board respectively, finally obtaining a verification result and generating a corresponding test report. According to the invention, each part in the automatic test system of the SoC array server is subjected to different verification methods to obtain an accurate test result, and a complete test report is generated based on the test result, so that the comprehensive, accurate and efficient test of the SoC array server is realized.

Description

An automated testing method for SoC array server and SoC array server

Technical field

The invention relates to the technical field of equipment testing, and in particular to an automated testing method for an SoC array server and an SoC array server.

Background technique

With the continuous advancement of science and technology and the advent of the information age, the demand for data processing and computing continues to grow. SoC (System on Chip) array server is a high-performance server that integrates multiple functions such as processor, memory and I/O interface. Its high density and high computing power can meet the growing needs of data processing. , is of great significance to large-scale data centers, cloud computing, artificial intelligence and other fields, and has been widely used in these fields. Further, the testing of SoC array servers has also begun to receive widespread attention. Due to the complexity and large scale of SoC array servers, traditional manual testing and inspection methods face many challenges, including being time-consuming and labor-intensive, and prone to human errors. Increased system deployment and maintenance costs and other issues.

Therefore, there is an urgent need for a reliable and automated SoC array server testing solution that can conduct comprehensive and efficient testing of various components within the server.

Contents of the invention

Based on this, it is necessary to propose an automated testing method and SoC array server for the SoC array server in response to the above problems, which can achieve comprehensive and efficient testing of various internal components of the SoC array server.

In a first aspect, the present invention provides an automated testing method for an SoC array server. The method is applied to the BMC motherboard of the SoC array server. The SoC array server also includes a backplane, a blade board, and a switching board. The backplane It includes a backplane controller and a fan controller, and the fan controller is connected to multiple fans; the blade board includes a blade board controller, an SoC board card, and a serial port controller; the method includes:

Send a first serial port command to the backplane controller, and generate a first test result based on whether a successful command returned by the backplane controller is received within a first preset time period;

Adjust the fan speed based on the fan controller within a first preset range, and generate a second test result based on whether the adjusted actual speed of the fan meets a speed threshold;

Receive the startup duration of the switching board, and generate a third test result based on whether the startup duration meets the preset duration range;

Send a second serial port command to the blade board controller, and generate a fourth test result based on whether a successful command returned by the blade board controller is received within the first preset time period;

Monitor the continuous output of serial port data by the serial port controller, and generate a fifth test result according to whether the serial port data output by the serial port controller is received within the first preset time period;

Obtain at least one of the startup time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results of the SoC array server, and based on the startup time, network speed, USB detection results, and deep recovery mode detection results , whether the serial port test results all meet the preset standards and generate the sixth test result;

Perform an aging test with a preset aging time on each component of the SoC board, and generate a seventh test result based on the operation of the system during the aging test;

Restart the system multiple times, obtain the restart duration of each system, and generate an eighth test result based on the multiple restart durations;

Based on the first test result, the second test result, the third test result, the fourth test result, the fifth test result, the sixth test result, the seventh test result, The eighth test result generates and outputs a test report.

Optionally, sending the first serial port command to the backplane controller, and generating a first test result based on whether a successful command returned by the backplane controller is received within a first preset time period includes:

Send a serial port command to the backplane controller and wait for a first preset time period. If a successful command returned by the backplane controller is received within the first preset time period, the first test result will be is normal;

If the successful command is not received within the first preset time period, repeat the step of issuing the serial port command to the backplane controller n times and the subsequent steps. If the successful command is not received n times, If the instruction is successful, the first test result is an error, and the test is terminated at this time.

Optionally, the fan speed is adjusted based on the fan controller within a first preset range, and a second test result is generated based on whether the adjusted actual speed of the fan meets a speed threshold, including:

The fan speed is adjusted based on the fan controller within a first preset range. Each value in the first preset range corresponds to a speed threshold. If a certain value is selected within the first preset range Adjust the fan speed, and the actual speed of the fan after adjustment meets the speed threshold, then the second test result is normal;

If the actual speed of the fan after adjustment does not meet the speed threshold, repeat the step of selecting a value within the first preset range to adjust the fan speed and the subsequent steps n times. If n times, If none of the actual fan speeds meets the speed threshold, the second test result is an error, and the test is terminated.

Optionally, receiving the startup duration of the switching board, and generating a third test result based on whether the startup duration complies with a preset duration range, including:

Restart the switching board and receive the startup duration of the switching board. If the startup duration meets the preset duration range, the third test result is normal;

If the startup duration does not meet the preset duration range, repeat the step of restarting the switch board and subsequent steps n times. If the startup duration obtained n times does not comply with the preset duration range, then the The third test result is an error, and the test is terminated at this time.

Optionally, the second serial port command is sent to the blade board controller, and a fourth test result is generated based on whether a successful command returned by the blade board controller is received within the first preset time period, include:

Send a serial port command to the blade board controller and wait for a first preset time period. If a successful command returned by the blade board controller is received within the first preset time period, the fourth test result will be is normal;

If the successful command is not received within the first preset time period, repeat the step of issuing the serial port command to the blade board controller n times and the subsequent steps. If the successful command is not received n times, If the instruction is successful, the fourth test result is an error, and the test is terminated at this time.

Optionally, monitor the continuous output of serial port data of the serial port controller, and generate a fifth test result according to whether the serial port data output by the serial port controller is received within the first preset time period, include:

Monitor the continuous output of serial port data of the serial port controller. If the serial port data output by the serial port controller is not received within the first preset time period, wait for the second preset time period. If within the first preset time period, If the serial port data is not received within the second preset time period, the fifth test result is an error, and the test is terminated at this time.

Optionally, obtain at least one of the startup duration, network speed, USB detection results, deep recovery mode detection results, and serial port detection results of the SoC array server. According to the startup duration, network speed, and USB detection results, , whether the deep recovery mode detection results and the serial port detection results all meet the preset standards, generate the sixth test result, including:

Restart the SoC array server and obtain the startup time; obtain at least one of the network speed, USB detection results, deep recovery mode detection results, and serial port detection results. If the startup time, network speed, USB detection results, and deep recovery mode If the test results and serial port test results both meet the preset standards, then the sixth test result is normal;

If at least one of the boot time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results does not meet the preset standard, repeat the steps of restarting the SoC array server n times and thereafter. step, if at least one of the n test results does not meet the preset standard, the sixth test result is an error, and the test is terminated at this time.

Optionally, each component of the SoC board is subjected to an aging test with a preset aging time, and a seventh test result is generated based on the operation of the system during the aging test, including:

An aging test is performed on each component of the SoC board. The aging test is a preset aging time. If the system restarts and/or crashes during the aging test, the seventh The test result is an error and the test is terminated at this time.

Optionally, restart the system multiple times, obtain the restart duration of each system, and generate an eighth test result based on the restart duration, including:

Imitate user usage scenarios, restart the system multiple times, and obtain the restart time of each system. If the restart time of each system meets the preset restart time standard, the eighth test result is normal. ;

If the restart duration of at least one system does not meet the preset restart duration standard, the eighth test result is an error, and the test is terminated.

In a second aspect, the present invention provides a SoC array server. The SoC array server includes a BMC motherboard, a backplane, a blade board, and a switching board that are connected to each other. The backplane includes a backplane controller and a fan controller. The fan controller is connected to multiple fans; the blade board includes a blade board controller, SoC board card, and serial port controller;

The BMC mainboard is used to manage and monitor the running status of the entire SoC array server; the BMC mainboard is also used to monitor the health status of the SoC array server in real time and perform remote management and maintenance;

The backplane controller is connected to the BMC mainboard. The backplane controller is used to connect and coordinate the various hardware components on the backplane, ensure the normal operation and communication of the various hardware components, and manage and control the entire Each sub-module on the backplane;

The blade board controller is connected to the backplane controller, and the blade board controller is used to communicate with each component in the blade board, and manage and monitor the operating status of each component in the blade board;

The serial port controller is connected to the BMC motherboard, the blade board controller, the SoC board card, and the switching board, and is used to configure and control the serial port devices in the SoC array server, while supporting various Serial communication and providing status monitoring function of the SoC array server;

The switching board is used to establish high-speed and stable data channels between various components inside the SoC array server; the switching board is also used to support rapid data exchange between various components inside the SoC array server, and Support flexible network configuration to meet the needs of different business scenarios;

The fan controller is used to control the fan speed and monitor the fan status;

The SoC board includes an SoC chip, and the SoC board is used to perform various computing tasks and data processing operations on the SoC array server;

Wherein, the BMC motherboard is used to execute the automated testing method of the SoC array server as described in any one of the first aspects.

Adopting the embodiments of the present invention has the following beneficial effects:

The invention provides an automated testing method for an SoC array server. The method is applied to a BMC mainboard of an SoC array server. The SoC array server also includes a backplane, a blade board, and a switching board. The backplane includes a backplane. board controller and fan controller, the fan controller is connected to multiple fans; the blade board includes a blade board controller, an SoC board card, and a serial port controller; the method is specifically: let the backplane controller, fans, The blade board controller, SoC board, serial port controller, and switching board work normally, and the preset time length and preset range are set to verify them respectively. Finally, the verification results are obtained and a test report is generated. The present invention specifically conducts different verification methods on each part of the automated test system of the SoC array server to obtain accurate test results, and generates a complete test report based on the test results, thereby realizing comprehensive and comprehensive testing of the SoC array server. Efficient testing.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

in:

Figure 1 is a schematic flow chart of an automated testing method for an SoC array server provided by an embodiment of the present application;

Figure 2 is a schematic diagram showing an example of an automated testing method for an SoC array server provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of an SoC array server provided in an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

The embodiment of this application proposes an automated testing method for an SoC array server. This method uses an intelligent automated testing system to test various components such as the backplane MCU, blade MCU, serial port MCU, switching board, and SoC board card of the SoC array server. Comprehensive and efficient automated testing to improve server reliability and performance and reduce system deployment and maintenance costs. This method can accurately detect whether the components are working properly and generate corresponding detection reports, so that potential problems can be discovered in a timely manner based on the detection reports. Further implementation can bring important technical support to the deployment and maintenance of large-scale SoC array servers.

Please refer to Figure 1, which is a schematic flow chart of an automated testing method for an SoC array server provided by an embodiment of the present application. The method is applied to the BMC motherboard of the SoC array server. The SoC array server also includes a backplane, a blade board, and a switching board; the backplane The board includes a backplane controller and a fan controller; the fan controller is connected to multiple fans; the blade board includes a blade board controller, an SoC board card, and a serial port controller; the method specifically includes:

Step 101: Send a first serial port command to the backplane controller, and generate a first test result based on whether a successful command returned by the backplane controller is received within a first preset time period.

In the embodiment of this application, the BMC motherboard issues serial port commands to the backplane controller and waits for the first preset time period. If a successful command is received from the backplane controller within the first preset time period, the first test The result is normal; if no successful command is received within the first preset time period, repeat the steps of issuing serial port commands to the backplane controller n times and the subsequent steps. If no successful command is received n times, , then the first test result is an error, and the test is terminated at this time.

The first preset duration may be preferably 3 seconds, and n may be preferably 3 times. It should be noted that the first preset duration and the value of n here are only a preferred example, and other values that meet the standards can be applied to the embodiments of the present application, and there are no excessive restrictions here.

Let’s give an example of step 101: The BMC motherboard issues serial port commands to the backplane controller and waits for 3 seconds. If the backplane controller returns a successful command within 3 seconds, it means that the backplane controller is normal. At this time, return to the first step. The test result is normal; if no successful command is received from the backplane controller within 3 seconds, it means that the backplane controller may be abnormal. At this time, retry the above steps 3 times. If the successful command is not received in 3 times, Or if other abnormal signals unrelated to the successful command are received, it is confirmed that the backplane controller is abnormal. At this time, the first test result is returned as an error, reminding the user that there is an abnormality in the backplane controller, and terminating the test process.

Step 102: Adjust the fan speed based on the fan controller within the first preset range, and generate a second test result based on whether the adjusted actual fan speed meets the speed threshold.

In a feasible implementation, the fan speed is adjusted based on the fan controller within the first preset range. Each value in the first preset range corresponds to a speed threshold. If the fan speed is selected within the first preset range, Adjust the fan speed to a certain value. If the actual fan speed after adjustment meets the speed threshold, the second test result is normal; if the actual fan speed after adjustment does not meet the speed threshold, repeat n times to select a certain value within the first preset range. In the steps of adjusting the fan speed by n values and subsequent steps, if the actual fan speed obtained n times does not meet the speed threshold, the second test result is an error, and the test is terminated at this time.

Among them, the full load speed of the fan is 15,000 rpm, and the first preset range is preset to be 10% to 100%. At this time, the number of revolutions corresponding to 10% of the fan's full load speed is 1,500 rpm, and the speed threshold corresponding to 10% is set to 1500±10% (where 1500 is 15000*10%); and by analogy, the rotation speed threshold corresponding to each value within the first preset range of 10% to 100% is obtained. As mentioned above, the first preset duration may be preferably 3 seconds, and n may be preferably 3 times. It should be noted that the first preset duration and the value of n here are only a preferred example, and other values that meet the standards can be applied to the embodiments of the present application, and there are no excessive restrictions here.

An example of step 102: The BMC motherboard selects a value from 10% to 100% to adjust the fan speed. Assume that 25% is selected, then the corresponding speed threshold is 3750±25% (where 3750 is 15000*25%). If adjusted If the actual speed after adjustment does not exceed the speed threshold of 3750±25%, it means that the fan is normal, and the second test result is returned as normal; if the actual speed after adjustment exceeds the speed threshold of 3750±25%, it means that the fan may be abnormal, and this If the results of the three times show that the fan is abnormal, that is, the actual speed of the fan exceeds the speed threshold of 3750±25% in all three times, it is determined that the fan is abnormal, and then return to the second test. The result is an error, which reminds the user that there is an abnormality in the fan and terminates the test process.

It should be noted that in step 102, in addition to adjusting the fan speed by selecting any value within the first preset range, the fan speed may also be adjusted gradually from 10% to 100%.

Step 103: Receive the startup duration of the switching board, and generate a third test result based on whether the startup duration meets the preset duration range.

In the embodiment of this application, the switching board is restarted and the startup time of the switch board is received. If the startup time meets the preset time range, the third test result is normal; if the startup time does not meet the preset time range, the restart is repeated n times. In the step of exchanging the board and the subsequent steps, if the startup duration obtained n times does not meet the preset duration range, the third test result is an error, and the test is terminated at this time.

It can be understood that step 103 is mainly a power-on and power-off test of the switching board, and is used to test whether the restart circuit of the switching board is normal and whether the network path is normal. Among them, the switching board startup time is generally 30s, and the longest does not exceed 40s, so the preset time range is preferably 30s to 40s, and n is preferably 3 times.

Give an example of step 103: restart the switching board and receive the startup time of the switching board. If the startup time is between 30s and 40s, it means that the switching board is normal, and the third test result is returned as normal; if the startup time exceeds 40s, Or the network access is abnormal, it means that there may be an abnormality in the switch board. Repeat the above steps three times. If the boot time obtained in the three times exceeds 40s, the third test result will be returned as an error at this time to remind the user that the switch board is abnormal. situation and terminate the test process.

Step 104: Send a second serial port command to the blade board controller, and generate a fourth test result based on whether a successful command returned by the blade board controller is received within the first preset time period.

In the embodiment of the present application, a serial port command is sent to the blade board controller and the wait time is the first preset time. If a successful command returned by the blade board controller is received within the first preset time, the fourth test result is Normal; if no successful command is received within the first preset time period, repeat the steps of issuing the serial port command to the blade board controller n times and the subsequent steps. If no successful command is received n times, the fourth The test result is an error and the test is terminated at this time.

Wherein, as mentioned above, the first preset duration is preferably 3s, and n is preferably 3 times.

Take an example to illustrate step 104: The BMC motherboard issues a serial port command to the blade board controller and waits for 3 seconds. If a successful command returned by the blade board controller is received within 3 seconds, it means that the blade board controller is normal. At this time, return to the fourth step. The test result is normal; if the BMC mainboard fails to receive the successful command returned by the blade board controller within 3 seconds or receives other abnormal signals, it means that the blade board controller may be abnormal. At this time, retry the above steps three times. If 3 If no successful command is received from the blade board controller, it is confirmed that the blade board controller is abnormal. At this time, the fourth test result is returned as an error, reminding the user that an abnormality has occurred in the blade board controller, and terminating the test process.

Step 105: Monitor the continuous output of serial port data by the serial port controller, and generate a fifth test result based on whether the serial port data output by the serial port controller is received within the first preset time period.

In the embodiment of the present application, the continuous output of serial port data of the serial port controller is monitored. If the serial port data output by the serial port controller is not received within the first preset time period, wait for the second preset time. Assuming a time length, if the serial port data is not received within the second preset time period, the fifth test result is an error, and the test is terminated at this time.

It is understandable that the serial port MCU is a real-time serial port output party, and the BMC motherboard only needs to monitor whether the serial port data is continuously output to obtain the operation status of the serial port controller. Wherein, as mentioned above, the first preset time length is preferably 3s, and the second preset time length is preferably 30s.

Give an example of step 105: The BMC motherboard monitors whether the serial port data of the serial port controller is continuously output. If the serial port data output by the serial port controller is not received within 3s, it means that the serial port controller may be abnormal. At this time, wait for 30s. If If no serial port data is received during the waiting 30s, it is confirmed that there is an abnormality in the serial port controller. At this time, the fifth test result is returned as an error, reminding the serial port controller that there is an abnormality, and the test process is terminated; if within 3s If the serial port data transmitted by the serial port controller is received, it means that the serial port controller is normal, and the fifth test result is returned as normal.

Step 106: Obtain at least one of the startup time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results of the SoC array server. Based on the startup time, network speed, USB detection results, and deep recovery mode detection results, Whether the serial port test results all meet the preset standards, the sixth test result is generated.

In the embodiment of this application, restart the SoC array server and obtain the startup time; obtain at least one of the network speed, USB detection results, deep recovery mode detection results, and serial port detection results. If the startup time, network speed, USB detection results, If the deep recovery mode detection results and serial port detection results both meet the preset standards, the sixth test result is normal; if at least one of the startup time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results does not meet the If the preset standard is set, repeat the steps of restarting the SoC array server n times and the following steps. If at least one of the n test results does not meet the preset standard, the sixth test result is an error, and the test is terminated at this time. .

It can be understood that step 106 is to test and verify the SoC function in the SoC array server. Among them, the preset standard for the startup time of restarting the SoC array server is to complete the startup within 2 minutes; the preset standard for the network speed is 2500W speed; the preset standard for the USB detection result is ADB (Android Debug Bridge, Android debug bridge is a kind of A command line tool with various functions that enables devices to communicate with each other.) Whether the connection is normal; the preset standard for the deep recovery mode detection result is whether the deep flash mode is started normally; the preset standard for the serial port detection result is whether the serial port transmission data is normal.

Take an example to illustrate step 106: Restart the SoC array server and obtain the startup time; obtain at least one of the network speed, USB detection results, deep recovery mode detection results, and serial port detection results. If the startup time is within 2 minutes, The network speed is 2500M, the USB test result shows that ADB is connected normally, the deep recovery mode test result shows that the deep flash mode starts normally, and the serial port test result shows that the serial port data transmission is normal, then it is confirmed that the SoC function is normal, and the sixth test result is returned as normal; If any of the startup time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results do not meet the aforementioned preset standards, it means that the SoC function may be abnormal. At this time, repeat the above steps three times. If 3 If at least one of the test results does not meet the preset standard, it is confirmed that the SoC function is abnormal. At this time, the sixth test result needs to be returned as an error to remind the user that the SoC function is abnormal and the test process is terminated.

Step 107: Perform an aging test with a preset aging time on each component of the SoC board, and generate a seventh test result based on the operation of the system during the aging test.

In the embodiment of this application, an aging test is performed on each component of the SoC board. The aging tests are all for a preset aging time. If the system restarts and/or crashes during the aging test, the seventh test result is Error, the test is terminated at this time.

Among them, the default aging time is 3*24 hours. The burn-in test mainly targets various components of the SoC board, such as CPU, GPU, network card, etc.

Let’s give an example of step 107: perform an aging test of 3*24 hours on each component of the SoC board. If the system restarts and/or crashes during the aging test, confirm that the system’s aging test is not correct. Successfully, the seventh test result is returned as an error, reminding the user that there is an abnormality in the aging test, and terminating the test process; if during the aging test, the system has been running normally without restarting and/or downtime, the system's aging test Successfully, the seventh test result returned is normal.

Step 108: Restart the system multiple times, obtain the restart duration of each system, and generate an eighth test result based on the multiple restart durations.

In the embodiment of this application, the user usage scenario is simulated, the system is restarted multiple times, and the restart duration of each system is obtained. If the restart duration of each system meets the preset restart duration standard, the eighth test result is normal; If the system restart time at least once does not meet the preset restart time standard, the eighth test result is an error, and the test is terminated at this time.

It can be understood that the purpose of step 108 is to imitate the frequent restart verification operations used by users and test whether frequent restarts will cause damage to the SoC array server. Among them, the default restart time is 2 minutes.

Give an example of step 108: imitate the user usage scenario and restart the system multiple times frequently. Assume that the system is restarted 100 times and obtain the restart time of each system. If the system completes the restart within 2 minutes each time, the eighth test The result is normal; if the system restart time at least once is not within 2 minutes, it means that the system's anti-frequent restart performance is not good enough. At this time, the eighth test result returned is an error, reminding the user that the restart operation test is abnormal, and the test is terminated. process.

Step 109: Generate and output a test report based on the first test result, the second test result, the third test result, the fourth test result, the fifth test result, the sixth test result, the seventh test result, and the eighth test result.

It can be understood that please refer to Figure 2, which is a schematic diagram of an automated testing method for an SoC array server provided by an embodiment of the present application. After all test verifications are completed, the first test result, the second test result, and the third test result are The test results, the fourth test result, the fifth test result, the sixth test result, the seventh test result, and the eighth test result generate a complete test report and automatically output and display it to the user terminal.

In the embodiment of this application, each part of the automated test system of the SoC array server is specifically verified using different verification methods to obtain accurate test results, and a complete test report is generated based on the test results, thereby realizing the verification of the SoC array server. Comprehensive and efficient testing of array servers.

Please refer to Figure 3, which is a schematic structural diagram of an SoC array server provided in an embodiment of the present application. The SoC array server includes a BMC mainboard 310, a backplane 320, a blade board 330, and a switching board 340 that are connected to each other. The backplane 320 includes a backplane. The controller 321 and the fan controller 322 are connected to multiple fans; the blade board 330 includes a blade board controller 331, an SoC board 332, and a serial port controller 333. specific:

The BMC (Baseboard Management Controller) mainboard 310 can be connected to the switch board 340 through at least one of Ethernet, UART (Universal Asynchronous Receiver-Transmitter, Universal Asynchronous Receiver-Transmitter) serial port, and Console. The BMC mainboard 310 is also connected to the back panel through the UART serial port. The board controller 321 and the serial port controller 333 are connected; the backplane controller 321 is connected to the switching board 340 and the blade board controller 331 respectively by controlling I/O. The backplane controller 321 is connected to the switch board 340 and the blade board controller 331 through PM BUS (Power Management Bus, power supply) Management bus) is connected to the fan controller 322. The backplane controller 321 can also be connected to the blade board controller 331 through the UART serial port; the blade board controller 331 is connected to the serial port controller 333 and the SoC board by controlling I/O. 332 connection; the SoC board 332 is connected to the serial port controller 333 through the UART serial port, and the SoC board 332 is connected to the switch board 340 through Ethernet; the serial port controller 333 can also be connected to the switch board 340 through Ethernet.

BMC motherboard 310 is the core control board of the SoC array server and is responsible for managing and monitoring the running status of the entire server. It integrates a series of management functions, such as remote monitoring, fault diagnosis, power control, fan control, etc. Through the BMC motherboard 310, administrators can monitor the health status of the server in real time and perform remote management and maintenance.

The backplane controller 321 and fan controller 322 are integrated on the backplane 320 .

Among them, the backplane controller 321 is a control module on the SoC array server backplane 320 and is used to manage and control each sub-module on the entire backplane 320. It is responsible for connecting and coordinating the various hardware components on the backplane 320 to ensure that they can operate and communicate properly. There is data exchange between the backplane controller 321 and the BMC mainboard 310. Through this communication, the BMC mainboard 310 can monitor and manage all sub-modules on the backplane 320.

The fan controller 322 is responsible for controlling the plurality of fan speeds and monitoring fan status. It can be understood that the preferred number of fans in Figure 2 here is four, but this does not mean that only four fans can be connected to this SoC array server. This is only a preferred example and does not impose too many restrictions.

The blade board 330 integrates a blade board controller 331, an SoC board 332, and a serial port controller 333. Among them, the number of blade boards 330 is preferably 4, the number of SoC boards 332 is preferably 10, and the number of serial port controllers 333 is preferably 2. It should be noted that this is only a preferred situation and does not impose excessive restrictions on the quantity.

Among them, the blade board controller 331 is a control module on the SoC array server blade board 330 and is used to manage and monitor the operating status of the blade board 330 . It is responsible for communicating with the various components within the blade board 330. There is data exchange between the blade board controller 331 and the backplane controller 321. Through this communication, the backplane controller 321 can perform unified management and monitoring of the blade board 330.

The SoC board 332 is the core computing unit of the SoC array server. Each SoC board integrates a SoC chip, including a processor, memory, I/O interface, etc. The SoC board 332 is the computing and data processing core of the SoC array server, and they are responsible for performing various computing tasks and data processing operations on the SoC array server. In the SoC array server, multiple SoC boards 332 form an array, which are connected and work together through the switching board 340 and the backplane controller 321 to achieve high-performance data processing and computing capabilities.

The serial port controller 333 is connected to the BMC mainboard 310, the blade board controller 331, the SoC board 332, and the switching board 340. It is a control module in the SoC array server and is responsible for managing and controlling each serial port in the SoC array server. It can realize the configuration and control of each serial port device in the SoC array server, support serial port communication, and provide status monitoring functions of the SoC devices in the SoC array server.

The switching board 340 is an important component in the SoC array server and is responsible for processing network communications within the SoC array server. It integrates a high-performance switching chip to establish high-speed and stable data channels between various components within the SoC array server. The switching board 340 allows rapid exchange of data between various components and supports flexible network configuration to meet the needs of different business scenarios. Among them, the switching board can preferably be a 25G switching board. Similarly, this is only a preferred situation without too many restrictions.

It can be understood that the above-mentioned automated testing method of the SoC array server described in Figure 1 is performed on the BMC mainboard 310 in the SoC array server.

In the embodiment of the present application, the above-mentioned BMC motherboard 310 performs any automated test method of the SoC array server as shown in Figure 1. Please refer to the content of the embodiment shown in Figure 1, and will not be described again here.

In an embodiment of the present application, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, it causes the processor to execute the method of any one of the above method embodiments.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through computer programs. The programs can be stored in a non-volatile computer-readable storage medium. , when the program is executed, it may include the processes of the above-mentioned method embodiments. Any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and/or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Synchlink DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present application, and their descriptions are relatively specific and detailed, but should not be construed as limiting the patent scope of the present application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all fall within the protection scope of the present application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims (10)

1. An automated testing method for an SoC array server, characterized in that the method is applied to the BMC motherboard of the SoC array server. The SoC array server also includes a backplane, a blade board, and a switching board. The backplane includes a backplane. A board controller and a fan controller, the fan controller is connected to multiple fans; the blade board includes a blade board controller, an SoC board card, and a serial port controller; the method includes: Send a first serial port command to the backplane controller, and generate a first test result based on whether a successful command returned by the backplane controller is received within a first preset time period; Adjust the fan speed based on the fan controller within a first preset range, and generate a second test result based on whether the adjusted actual speed of the fan meets a speed threshold; Receive the startup duration of the switching board, and generate a third test result based on whether the startup duration meets the preset duration range; Send a second serial port command to the blade board controller, and generate a fourth test result based on whether a successful command returned by the blade board controller is received within the first preset time period; Monitor the continuous output of serial port data by the serial port controller, and generate a fifth test result according to whether the serial port data output by the serial port controller is received within the first preset time period; Obtain at least one of the startup time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results of the SoC array server, and based on the startup time, network speed, USB detection results, and deep recovery mode detection results , whether the serial port test results all meet the preset standards and generate the sixth test result; Perform an aging test with a preset aging time on each component of the SoC board, and generate a seventh test result based on the operation of the system during the aging test; Restart the system multiple times, obtain the restart duration of each system, and generate an eighth test result based on the multiple restart durations; Based on the first test result, the second test result, the third test result, the fourth test result, the fifth test result, the sixth test result, the seventh test result, The eighth test result generates and outputs a test report. 2. The method according to claim 1, characterized in that the sending of the first serial port command to the backplane controller is based on whether the backplane controller is received within a first preset time period. A successful command generates the first test result, including: Send a serial port command to the backplane controller and wait for a first preset time period. If a successful command returned by the backplane controller is received within the first preset time period, the first test result will be is normal; If the successful command is not received within the first preset time period, repeat the step of issuing the serial port command to the backplane controller n times and the subsequent steps. If the successful command is not received n times, If the instruction is successful, the first test result is an error, and the test is terminated at this time. 3. The method of claim 1, wherein the fan speed is adjusted based on the fan controller within a first preset range based on whether the adjusted actual speed of the fan meets a speed threshold, Generate second test results, including: The fan speed is adjusted based on the fan controller within a first preset range. Each value in the first preset range corresponds to a speed threshold. If a certain value is selected within the first preset range Adjust the fan speed, and the actual speed of the fan after adjustment meets the speed threshold, then the second test result is normal; If the actual speed of the fan after adjustment does not meet the speed threshold, repeat the step of selecting a value within the first preset range to adjust the fan speed and the subsequent steps n times. If n times, If none of the actual fan speeds meets the speed threshold, the second test result is an error, and the test is terminated. 4. The method according to claim 1, characterized in that, receiving the startup duration of the switching board, and generating a third test result according to whether the startup duration complies with a preset duration range, including: Restart the switching board and receive the startup duration of the switching board. If the startup duration meets the preset duration range, the third test result is normal; If the startup duration does not meet the preset duration range, repeat the step of restarting the switch board and subsequent steps n times. If the startup duration obtained n times does not comply with the preset duration range, then the The third test result is an error, and the test is terminated at this time. 5. The method according to claim 1, wherein the sending of the second serial port command to the blade board controller is based on whether a transmission from the blade board controller is received within the first preset time period. The successful command returned generates the fourth test result, including: Send a serial port command to the blade board controller and wait for a first preset time period. If a successful command returned by the blade board controller is received within the first preset time period, the fourth test result will be is normal; If the successful command is not received within the first preset time period, repeat the step of issuing the serial port command to the blade board controller n times and the subsequent steps. If the successful command is not received n times, If the instruction is successful, the fourth test result is an error, and the test is terminated at this time. 6. The method according to claim 1, wherein the monitoring of the continuous output of serial port data of the serial port controller is based on whether the serial port data output by the serial port controller is received within the first preset time period. The serial port data generates the fifth test result, including: Monitor the continuous output of serial port data of the serial port controller. If the serial port data output by the serial port controller is not received within the first preset time period, wait for the second preset time period. If within the first preset time period, If the serial port data is not received within the second preset time period, the fifth test result is an error, and the test is terminated at this time. 7. The method according to claim 1, characterized in that, obtaining at least one of the startup time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results of the SoC array server, the method is based on Whether the startup time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results all meet the preset standards, a sixth test result is generated, including: Restart the SoC array server and obtain the startup time; obtain at least one of the network speed, USB detection results, deep recovery mode detection results, and serial port detection results. If the startup time, network speed, USB detection results, and deep recovery mode If the test results and serial port test results both meet the preset standards, then the sixth test result is normal; If at least one of the boot time, network speed, USB detection results, deep recovery mode detection results, and serial port detection results does not meet the preset standard, repeat the steps of restarting the SoC array server n times and thereafter. step, if at least one of the n test results does not meet the preset standard, the sixth test result is an error, and the test is terminated at this time. 8. The method according to claim 1, characterized in that, each component of the SoC board is subjected to an aging test with a preset aging time, and based on the operation status of the system during the aging test, a generated The seventh test results include: An aging test is performed on each component of the SoC board. The aging test is a preset aging time. If the system restarts and/or crashes during the aging test, the seventh The test result is an error and the test is terminated at this time. 9. The method according to claim 1, wherein the system is restarted multiple times, the restart duration of each system is obtained, and an eighth test result is generated based on the restart duration, including: Imitate user usage scenarios, restart the system multiple times, and obtain the restart time of each system. If the restart time of each system meets the preset restart time standard, the eighth test result is normal. ; If the restart duration of at least one system does not meet the preset restart duration standard, the eighth test result is an error, and the test is terminated. 10. A SoC array server, characterized in that the SoC array server includes a BMC motherboard, a backplane, a blade board, and a switching board that are connected to each other. The backplane includes a backplane controller and a fan controller. The fan The controller is connected to multiple fans; the blade board includes a blade board controller, SoC board card, and serial port controller; The BMC mainboard is used to manage and monitor the running status of the entire SoC array server; the BMC mainboard is also used to monitor the health status of the SoC array server in real time and perform remote management and maintenance; The backplane controller is connected to the BMC mainboard. The backplane controller is used to connect and coordinate the various hardware components on the backplane, ensure the normal operation and communication of the various hardware components, and manage and control the entire Each sub-module on the backplane; The blade board controller is connected to the backplane controller, and the blade board controller is used to communicate with each component in the blade board, and manage and monitor the operating status of each component in the blade board; The serial port controller is connected to the BMC motherboard, the blade board controller, the SoC board card, and the switching board, and is used to configure and control the serial port devices in the SoC array server, while supporting various Serial communication and providing status monitoring function of the SoC array server; The switching board is used to establish high-speed and stable data channels between various components inside the SoC array server; the switching board is also used to support rapid data exchange between various components inside the SoC array server, and Support flexible network configuration to meet the needs of different business scenarios; The fan controller is used to control the fan speed and monitor the fan status; The SoC board includes an SoC chip, and the SoC board is used to perform various computing tasks and data processing operations on the SoC array server; Wherein, the BMC motherboard is used to execute the automated testing method of the SoC array server according to any one of claims 1 to 9.