CN1173280C - Adaptive information processing system and with network topology - Google Patents

Abstract

The present invention relates to an information processing system with a network topological structure. The present invention is composed of units such as a system service subnetwork, an application-oriented processing subnetwork, a multilayer bus, etc. which are connected, wherein a system service layer is composed of a central processing unit, a microcontroller and a synchronous controller which are arranged in the system service subnetwork; the system service layer is combined with an information bus and hard real-time synchronizing signal lines among modules to form a service channel, and is in the implementation service for each module in the information processing system; the information processing system has the multibus topological structure through a plurality of buses with different velocities; a network distributed cooperation operational mechanism in the system is formed by a multiprocessor, a shared memory and corresponding input and output equipment.

Description

Adaptive information processing system with network topology structure

The present invention relates generally to information handling system, relate in particular to a kind of adaptive information processing system with network topology structure.

When multimedia application and internet began to come in people's life, computing machine had also entered the Pentium age.The process object of computing machine no longer is simple relatively non real-time data processing, and bigger challenge is the processing with data stream of real-time requirement.Done the certain structure adjustment with regard to central processing unit (CPU) itself at its newly-increased process object and heavier Processing tasks.Increased multimedia newly and strengthened the instruction of instruction set MMX (Multi-Media extension) cell processing media stream, improved CPU multimedia processing power.Moreover, early stage computing machine all is complex instruction set computer (CISC) CISC (ComplexInstruction Set Computer), process object is complicated and (from 8 to 120 s') different in size instruction set, in fact frequent instruction only accounts for about 20% in sophisticated vocabulary, and because instruct the inconsistent of length, so processing speed is slow relatively.And the instruction set of Reduced Instruction Set Computer RISC (ReducedInstruction Set Computer) is briefly practical and have equal length, so processing speed is faster much than CISC.Owing to the numerous instructions with sophisticated vocabulary change into reduced instruction is impossible realize, so just adopted reduced instruction kernel (RISC core) unit in CPU inside, the instruction of sophisticated vocabulary is formed class reduced instruction (RISC Like) after deciphering, and operation is seen Fig. 1 with speed up processing on the reduced instruction kernel.

External unit bus (IO BUS) has also had significant progress after entering multimedia and network, carry office to the IO access speed from 8 initial ISA (industrial standard architectures Industry Standard Architecture) bus to 16 PCI (the interconnected Peripheral Component of external unit Interconnection) bus, supported plug and play (Plug ﹠amp comprehensively; Play).Occur the coprocessor of figure accelerate bus AGP (Acceleration Graphic Port) connection processing figure again in 2 generations of Pentium, share the Processing tasks of CPU, the accelerated graphics processing speed.In Pentium age CPU frequency no matter, memory capacity and cache memory (Cache) size etc. has all had very fast raising.

CPU is responsible for controlling the operation of whole computer system, and its basic control function is exactly sequential control and carries out control.CPU finishes its system service operation and mainly is made up of four parts.At first, CPU carries out timing by the clock signal that clock circuit produces, and is undertaken by the sequential of appointment to control various operations.Secondly, CPU will finish the operation of instruction fetch, analysis instruction and steering logic arithmetic unit ALU execution command.Once more, CPU provides and interrupts the synchro control logic, improves the treatment effeciency of CPU, makes CPU and input-output device 1/0 concurrent working, makes CPU can in time respond various anomalous events of not knowing in advance simultaneously, can also realize time-sharing operation.At last, CPU provides bus control logic, coordinates each parts application and uses bus.

Fig. 2 represents the break in service flow process that CPU provided in the existing personal computer framework.

1) hardware produces and interrupts activating corresponding module in the OS kernel by interruptable controller INTC (Interrupt Controller).

2) the OS kernel is checked interrupting.

3) call corresponding Interrupt Service Routine (ISR).

4) Interrupt Service Routine ISR handles interrupting.

5) return interrupt identification (Interrupt ID).

6) interior nuclear inspection interrupt identification (Interrupt ID).

7) call the corresponding break in service thread (IST) of interrupt identification (Interrupt ID) therewith.

8) break in service thread IST is by the driver handles hardware interrupts.

If interrupt service routine is comparatively simple, then the 6th to the 8th step can omit in the said process, and that is to say no longer needs break in service thread IST to handle this interruption.

The principal element that influences interrupt response time is the response time of Interrupt Service Routine ISR and the response time of break in service thread IST.The Interrupt Service Routine ISR response time mainly sees if there is priority and is higher than the Interrupt Service Routine ISR of current interrupt request in execution.The factor that influences break in service thread IST is then complicated more, comprises the scheduling of system to thread, and critical section (Critical Section), semaphore (Semaphores), mutex (Mutex) and incident (event) are also handled etc.In traditional personal computer framework, synchronous and the service of interrupting of data stream all is the (see figure 2) of being born by CPU, CPU also will undertake the response that reaches interruption synchronously of data stream when finishing calculating, increase the complicacy of operating system design on the one hand, still can not satisfy the demand of the response of hard real-time interruption on the other hand.

CPU provides synchronous service for system, and except safeguarding normal data sync, the while is also accepted abnormal conditions and handles, and interrupts, overflows interruption, power fail interrupt, clock interruption, controller interruption (disable instruction, privileged instruction) etc. as the division mistake.CPU keeps the handling capacity of balance must carry out data sync for input source and the output source that guarantees signal when executing the task.Data from input source finish write store through the CPU processing, and operating system OS produces synchronizing signal and provides address data memory space notice output source, and output source is finished synchronization action one time to corresponding address space sense data.Receive the request of abnormality processing as CPU after, activate host Interrupt Service Routine ISR thereon, when running into complex situations, will do higher level strategy scheduling by CPU to Message Processing.

Fig. 3 gives from the whole angle of macroscopic view and has the system service that personal computer framework and CPU are provided.Wherein central processing unit kernel (CPU Core) comprises that arithmetic logic unit ALU, Float Point Unit FPU, multimedia strengthen unit such as instruction set MMX.

Existing personal computer system's structure can adapt to the application of number of different types as a general system framework.But also exist many inevitable weakness.Especially enter the first half nineties in 20th century, because the growth requirement of multimedia, internet, personal computer and high speed data transfer equipment, electronics industry has experienced huge leap, in order to win the coml competitive edge, manufacturer's product presses for pursues high function, quality product matter, low cost, little power consumption and microsize.So existing personal computer system's structure seems but that in the today that faces numerous challenges like this quite some is unable to do what one wants very much to do.

Make a general survey of existing personal computer system, roughly have following defectives:

1. power consumption and processing speed can't satisfy current rate request.When we are that the dominant frequency of 1.5GHZ is surprised the time, but worry for the new standard of MPEG VII (active images that a kind of compression ratio is bigger and the compression standard of sound), can software be realized? algorithm becomes increasingly complex, in order to satisfy the endless demand of people, what Wintel can do is exactly the dominant frequency that improves CPU.The increase of clock upset number of times, the increase of power consumption is inevitable, processor heat hot.Notebook still can adopt this class CPU reluctantly, how to allow the mobile device of hand-held accept this scheme?

2. multimedia demand makes can't be at the multimedia application optimal design.At specific algorithm, we can design special digital signal processor DSP or application-specific integrated circuit ASIC goes to realize in fact.And general processor can only satisfy demands of applications in the mode of patch installing.Multimedia strengthens instruction set unit MMX and special flow instruction expanding element SSE (II) (Streaming SIMD single instructionmultiple data Extensions) is exactly an example.

3. the real-time interrupt response (hard real-time) that can not realize.Memory Management Unit MMU that increases and virtual address map have been expanded the space of using.But also because make the hard real-time Interrupt Process be difficult for realizing like this.The Microsoft of Microsoft constantly improves its system, but owing to be subjected to the restriction of hardware platform, effect is always barely satisfactory.

4. the choice aspect of intelligence or performance can't improve performance and also can't really accomplish intelligence.Increasing application-specific waits processing in face of will being presented on computing machine, and some are wherein arranged is that we are known, as multimedia, network, communication etc.; Yet but be unknown more.In order to satisfy demands of applications, existing structure has adopted the mode of patch installing.CPU will provide service, at least also need to handle a small amount of real-time data (performance) for system, how many non real-times does the Processing tasks that it can also finish provide the intelligence service? improve frequency, light maintenance is also of no avail.

5. the challenge of Distributed Calculation.It at first is bottleneck problem.The raising of CPU frequency also will improve the requirement of bandwidth of memory.Increased cache memory Cache, from synchronous DRAM SDRAM (Synchronous Dynamic Random Access Memory) to ram bus RAMBUS (Direct RAMBUS System is an accumulator system), from PC100 to PC133 (clocked memory), from PCI (the interconnected Peripheral Component of external unit Interconnection) bus to AGP figure accelerate bus, whole industry member is changeed round Wintel all the time, yet bottleneck exists all the time.

Next is synchronous complicacy.Most realizations are finished by single CPU, by mechanism such as shared storage Share Memory and semaphore Semaphore (synchronous mark), rely on the synchronous of the inadequate maintenance data stream of processing power at a high speed.And we will face more complicated distributed calculating.

Be that design lacks opening in addition.For the realization of the solution (algorithm) of problem, the leeway of optimization is arranged all the time, and one man's opinion by no means.Wintle wants to create single system and satisfies all application demands, but system only can be too fat to move day by day.Open design is not only input-output device IO, also should comprise central processing unit kernel CPU Core and operating system OS.

6. the extensibility aspect of system no longer has enough extendabilities.In order to improve graphics process speed, increase figure accelerate bus AGP, the expansion means that hang up graphics acceleration card explanation patch installing formula are that available frame is unique adoptable, hard real-time interrupts still being difficult for realizing, can only place hope on and improve CPU frequency once more.Can what aspect application transaction card what but can also have open hang on the existing systems? the scaling problem of system can become more sharp-pointed along with the further in-depth of cybertimes.

Therefore, the object of the present invention is to provide and a kind ofly have network topology structure, make system have powerful self-adaptation adjustable function and adaptive information processing system with expandability.

Another object of the present invention is to provide a kind of system services layer that constitutes by CPU, microcontroller, isochronous controller in conjunction with the service channel of forming with the hard interruption synchronous signal line of messaging bus, intermodule etc., run through each module VC (virtual component) in the system of serving and the adaptive information processing system of formation system service sub-network, make system have powerful self-adaptation adjustable function.

Another object of the present invention is to provide a kind of adaptive information processing system with network distribution type computing structure.By multiprocessor.Reusable intellecture property IP (intellectual property) and input-output device are able to the system service sub-network and the bus-structured comprehensive support of multilayer forms the internal system network and can effectively carry out the cooperation computing that distributes.

Another object of the present invention is to provide a kind of is provided break in service, provides service for the abnormal conditions in the data sync for system by micro controller module (Micro Controller).Can coordinate the adaptive information processing system of the work of each processing unit simultaneously by messaging bus with the form of incident.

Another month of the present invention be that providing a kind of safeguards circular buffer (annular buffer) by the isochronous controller module by look-at-me, the adaptive information processing system of real time data stream between synchronization module and module exchange.

Another object of the present invention is to provide a kind of adaptive information processing system with power management and electricity-saving function.

According to an aspect of the present invention, provide a kind of information handling system, comprising with network topology structure:

A. system service sub-network, it comprises:

The CPU (central processing unit) that is used for system management, coordination and Intelligent treatment;

For system provides interrupt response and break in service, and in order to the microcontroller of each processor cell operation in the coherent system;

Be connected to described microcontroller, in order to the isochronous controller of the exchange of the real time data stream between module in the synchro system and the module;

Hard real-time synchronous signal line by messaging bus and intermodule is formed, and comprises the system service channel of interruption, synchronous system service message in order to transmission:

Described microcontroller comprises that the risc chip be made up of general-purpose register and arithmetic logical operation unit, interruptable controller, acceptance are from first interface of the abnormality processing message of isochronous controller, send to second interface of isochronous controller and the 3rd interface of the abnormality processing forwards being given CPU (central processing unit) with control information;

Described isochronous controller is realized at interior special IC by comprising turnout counter and consumption figure counter;

Described CPU (central processing unit), microcontroller and isochronous controller constitute a system services layer and pass through

Described service channel is connected,

B. at least one application oriented processing sub-network, it comprises:

Handle the processor of redistribute resources and the high-level analysis of data stream, it accepts the command process data from isochronous controller, and notifies microcontroller with abnormality processing message via isochronous controller;

Shared storage in order to swap data between microcontroller and processor;

The data source device of data input is provided;

The datum target device of data output is provided,

Described processor, shared storage, data source device and datum target device are connected to described messaging bus via each bar bus respectively,

C. in order to the system bus of transmission data, wherein, described system service sub-network and application are handled sub-network and are connected to system bus by the data bus of different rates respectively.

According to adaptive information processing system of the present invention, make system set up real distributed collaborative computing environment.Distributed parallel computation environment has been taken into account towards intelligence and demands of applications towards performance.The angle that distributed parallel computation environment stands in system framework has fundamentally solved the problem of running efficiency of system.Rather than improve the frequency of CPU simply.The raising of system effectiveness is that the improvement by system framework realizes, so the purpose of low-power consumption also is readily solved.Network is opened up the benefit structure can open and close some processing unit according to the different demands of using, even whole sub-network Subnet.Also described for algorithm, for optimization provides bigger space with the form of network.By system layer System Layer it is mapped on the system architecture with network topology structure.The control function that also will belong to simultaneously CPU is specifically transferred to each processor, as the control of sequential control, order register and bus control logic etc.

System services layer (Service Stack) makes system have adaptive characteristic on three different levels, and it provides synchronously for each processing unit in the system effectively, resources allocation and system monitoring (NetAdministrator).System under different applied environments, is easy to reach self-adaptation and balance under the help of four different levels services.The structure of network makes system have plug and play Plug ﹠amp in addition; The characteristic of Play (in the design).

The present invention provides an omnibearing solution for the SOC epoch.Not only effectively overcome the bottleneck problem in the existing system structure, also laid a good foundation simultaneously for the good development of SOC system.No matter be the demand of multimedia and cybertimes, also or more application in future, overcritical the present invention of higher Intelligent treatment provides enough extending spaces, the support and the efficient system service of hardware and software platform for this reason.The present invention effectively reduces overcritical to power consumption of processing unit and processing speed, and system performance and intelligence all obtain considerable raising and leave enough extending spaces for following, realize that the network distribution type computing improves treatment effeciency, the adaptive ability of simultaneously real realization system.

Below with reference to drawings and Examples information handling system of the present invention is described in further detail.It is clearer that further purpose of the present invention, feature and advantage will become in the following description.

Fig. 1 is the framework synoptic diagram of the personal computer of expression prior art;

Fig. 2 is the synoptic diagram of the break in service flow process that CPU provided in the existing personal computer framework of expression;

Fig. 3 gives the synoptic diagram have the system service that personal computer framework and CPU provided from the whole angle of macroscopic view;

Fig. 4 is the system block diagram of expression according to information handling system of the present invention;

Fig. 5 be an expression system service sub-network of the present invention open up the benefit structural representation;

Fig. 6 A is the operational block diagram of expression isochronous controller of the present invention;

Fig. 6 B is the synoptic diagram of expression isochronous controller inner structure and function thereof;

Fig. 7 A is the inner structure and the functional schematic thereof of expression microcontroller;

Fig. 7 B is the interface synoptic diagram of expression microcontroller;

Fig. 7 C is the working state schematic representation of expression microcontroller;

Fig. 8 is that the processor of expression in the system of the present invention is to resources allocation and the operation chart that data stream is analyzed;

Fig. 9 represents a system service process flow diagram according to information handling system of the present invention;

Figure 10 represents the constitutional diagram of the break in service thread IST that realizes on the processor;

Figure 11 is the synoptic diagram of the parallel co-design of expression software and hardware, checking;

Figure 12 is the synoptic diagram that expression utilizes the heterogeneous system platform that virtual machine technique provides;

Figure 13 is the synoptic diagram that expression utilizes the heterogeneous system platform that code conversion provides;

Figure 14 is the synoptic diagram of expression system resource allocation;

Figure 15 is the synoptic diagram of expression shared storage technique;

Figure 16 is the synoptic diagram of the multistage interconnected multicomputer system data transfer protocol of expression;

Figure 17 is the power management synoptic diagram of the processing unit in each subnet of expression;

Figure 18 is the power management synoptic diagram of expression microcontroller to processing unit;

Figure 19 is the synoptic diagram of the power management of expression services sub-network;

Figure 20 is the synoptic diagram that expression is applied to 3 steps of MP3 decoding flow process of the present invention;

Figure 21 shows the flow process of MP3 audio data download;

Figure 22 is the synoptic diagram of a voice data decoding algorithm of expression;

Figure 23 is the synoptic diagram of an audio data playback of expression;

Figure 24 is the synoptic diagram that expression system of the present invention connects with internet;

Figure 25 is the synoptic diagram of the realization of expression MP3 voice playing function in native system;

Figure 26 is the synoptic diagram of the operation of expression synchronization caching;

Figure 27 is expression realizes the video conference function with JPEG a process flow diagram;

Figure 28 is the synoptic diagram of expression ccd image acquisition module;

Figure 29 is the synoptic diagram of expression JPEG compression process;

Figure 30 is the synoptic diagram of expression USB (universal serial bus) (USB) transfer process;

Figure 31 is the synoptic diagram of the realization of expression video conference in system of the present invention.

Next referring to Fig. 4, its expression is according to a system block diagram of information handling system of the present invention.This information handling system comprises: a. system service sub-network, and it comprises the CPU (central processing unit) 41 that is used for system management, coordination and Intelligent treatment; For system provides interrupt response and break in service, and in order to the microcontroller 42 of each processor cell operation in the coherent system; Be connected to described microcontroller 42, in order to the isochronous controller 43 of the exchange of the real time data stream between module in the synchro system and the module; The system service channel of forming by the hard real-time synchronous signal line (not shown) of messaging bus 44 and intermodule, comprise interruption, synchronous system service message in order to transmission, described CPU (central processing unit) 41, microcontroller 42 and isochronous controller 43 are connected by described service channel; B. at least one application oriented processing sub-network, it comprises: the processor 45 of handling redistribute resources and the high-level analysis of data stream; Shared storage 46 in order to swap data between microcontroller 42 and processor 45; The data source device 47 of data input is provided; The datum target device 48 of data output is provided, and described processor 45, shared storage 46, data source device 47 and datum target device 48 are connected to described messaging bus 44 via each bar bus respectively.Be used to transmit the system bus 49 of data, wherein, described system service sub-network and application are handled sub-network and are connected to system bus 49 by the data bus of different rates respectively.

System adopts the network topology structure of single-chip.Wherein, by CPU41, microcontroller 42 and isochronous controller 43 construction system service layers, form topology of networks by the structure of multiprocessor and multibus.Topology of networks is with node (node), and edge (edge) describes.Processing unit is corresponding to node, and bus and channel constitute the edge.This is distributed to be applied on the algorithm also that the form with network realizes that it sets up mapping relations by the system layer between, and this is the cyberrelationship of the superiors of system, has set up the required basic framework of distributed arithmetic environment simultaneously.

System framework is taken into account performance and intelligence.CPU41 and Memory Management Unit MMU411 provide hardware platform, and traditional operating system manufacturer can make up virtual platform (Virtual Platform) on this basis, can realize all kinds of application towards intelligence on the virtual platform.

The design of digital signal processor DSP is optimized at different multimedia data streams, to satisfy performance demands.For the higher application of real-time response,, finally implement with application-specific integrated circuit ASIC through further analysis and optimization to algorithm.CPU, DSP, ASIC have constituted an asymmetrical processor system, with the shared storage swap data, form the computing main body of distributed arithmetic.

Connect as for bus, because there are many equipment need get involved bus, and the process object of these equipment and message transmission rate differ greatly, and use single bus can't satisfy performance requirement.So adopt multi-level data bus structure, according to of the different requirements of each equipment to data transmission rate, carry out with the bus of different levels interconnected, to adapt to characteristic and demand separately.Bus between different levels is relatively independent, allow to use different signals and with different speed operations, and can not influence the bus structure of other levels to the bus-structured modification of some levels, makes system have extendability.Link to each other with bridge Bridge between bus and the bus and satisfy requirement for different bandwidth.Provide service channel (Service Channel) to be used for the transmission system service message simultaneously with the compositions such as hard interruption synchronous signal line between messaging bus, the module, as interrupt, synchronous etc., guarantee that system's running nature is smooth and easy.The multilayer bus structure provide the support of strong hardware configuration layout for the concurrency of distributed arithmetic.

Topology of networks

Be different from Intranet/Internet, system is owing to exist shared drive, and the control of data and stream separates from packet (IP Packet), and network is made of two different topological structures:

1. be used for bus topology is also adopted in the message transmission of current control, but all in realization nodes are all in different pieces of information processing domain (being sub-network).The services sub-network network that is made of isochronous controller 43, microcontroller 42, CPU41 and messaging bus 44 is the body of system, for system provides basic service.Service comprises: synchronization of data streams; Interrupt response; Abnormality processing; Control stream is handled; System resource allocation and scheduling.

2. data transmit and adopt bus topology, and with bridge (Bridge) 40 different territories (being sub-network) are linked.For example comprise the subnet that three orientations are used in the system: towards the subnet of Intelligent treatment; Subnet towards the multimedia processing; Subnet towards communication.Wherein, be core towards the subnet of Intelligent treatment with the general processor of band MMU411, on this, make up the non-real time operating system of software.The subnet of handling towards multimedia is made of DSP and ASIC, coordinates synchronous between the VC by microcontroller, and the real time operating system on microcontroller (RTOS) provides support for data sync.

Node in the network

Node in the network not only comprises data processing unit, and (ASIC), message processing unit (message channel, microcontroller) is also included within the process of carrying out on the processor for DSP, processor, and different processes can be regarded different nodes as.

Connection in the network

Be different from Intranet/Internet, the sharing problem of bus prevents to share conflict with the procedures of arbitration device (Arbiter) of bus, and it can adopt different algorithms to realize according to different demands during design.

The system service sub-network

Exchanges data is by shared storage 46, and data sync realizes by the system service sub-network.The system service sub-network is made of following tri-layer.Isochronous controller 43 is safeguarded impact damper (annular buffer), the exchanges data between synchronization module and the module by look-at-me.Microcontroller 42 provides interrupt response and break in service (the differentiation interrupt priority level is also handled) for system, interruption can be divided into that external unit interrupts and internal interrupt (trap), and wherein internal interrupt comprises again and overflows interruption, software interruption, power fail interrupt, clock interruption, single step interruption, controller interruption etc.And by the work of messaging bus with the form coordination each processing unit of incident (Event).More than two levels handle for the smoothness operation of data stream effective interruption and synchronous service be provided.And CPU41 stands in the coordination of taking on total system on the highest level and the scheduling of resource as system management (System administrator).Form the system service sub-network by these three layers of service mechanisms in conjunction with service channel (Service Channel), flexible coordinated allocation task, system can reach adaptive equalization, really sets up the friendly cooperation relation in the distributed arithmetic.

The topological structure of system service sub-network

Fig. 5 represents the topological structure synoptic diagram of a system service sub-network of the present invention.With isochronous controller 43, microcontroller 42, CPU41 organizes together to constitute and is similar to neural network structure this system service sub-network by messaging bus 44.Isochronous controller 43, microcontroller 42 are the maincenters in the network structure, and CPU41 is the brain in the network structure.

Isochronous controller

In order to support the processing of real time data stream effectively,, be the isochronous controller 43 that ASIC realizes in the lowermost layer of system services layer.Compare with event driven microcontroller, maximum difference is to realize that mechanism synchronous between the VC has still kept the mode of interrupting.But different with the conventional process mode, the look-at-me line directly links to each other with isochronous controller 43.The look-at-me line is as the signal wire triggering synchronous controller module of frame synchronization.Come the real time data stream between synchronization module to exchange by isochronous controller 43 and annular buffer 61.Isochronous controller 43 activates corresponding break in service thread IST in the mode of interrupting, or notify coordinator with incident equally.

Fig. 6 A and 6B illustrate the operational block diagram of isochronous controller 43 of the present invention.Isochronous controller 43 is finished data sync work by annular buffer 61 is write the mode of counting with read address data,, claims that writing data is turnout here, and sense data is a consumption figure.The start address that isochronous controller 43 1 frame data begin to transmit is set to the start address of annular buffer 61, and when writing the next frame data, the turnout address counter adds one.If buffer 61 is write full, will provide " expiring " signal; And when data were read out, then the consumption figure address counter added one.If the data of buffer 61 run through, then provide " sky " signal.Isochronous controller 43 safeguards that in this way real time data is synchronous.

Microcontroller

Fig. 7 A represents the inner structure and the functional schematic thereof of microcontroller 42.Microcontroller 42 is made up of RISC core 71 and interruptable controller (INTC) 72.And RISC core 71 is made up of one group of general register and arithmetic logical operation unit (ALU).RISC core 71 provides one group of instruction set, utilizes this group instruction set, and software can be realized a series of functions.These functions comprise the break support of service routine (ISR) of centering, the synchro control between the break in service thread (IST), the control of annular buffer and power management or the like.Wherein, the support to Interrupt Service Routine comprises:

1) (Processor ASIC) 45 produces message to processing unit, passes to the interruptable controller 72 of microcontroller 42 through messaging bus 44;

2) interruptable controller 72 changes into look-at-me with message

3) activate corresponding interrupt service routines module in the OS kernel by interruptable controller 72;

4) Interrupt Service Routine is handled interrupting.

5) Interrupt Service Routine is read and write the register of processing unit 45, the state of controlled processing unit 45 by the register interface of microcontroller 42.

Synchronous support comprises to task (Task):

6) processing unit 45 produces message, passes to the interruptable controller 72 of microcontroller 42 through messaging bus 44;

7) microcontroller 42 reads message, is two parts with this message interpretation: source address and message itself;

8) microcontroller 42 is according to the source address and the corresponding output message of the middle inquiry of content place message table (Message Table) of message;

9) microcontroller 42 sends to corresponding ISC 2526 according to the destination address in the output message by messaging bus 44;

10) ISC 2526 that waits for certain message obtains continuing to execute the task after the message.Control to annular buffer 61:

Fig. 6 B represents the synoptic diagram of isochronous controller inner structure and function thereof.Wherein, the treatment mechanism of message is the same.Turnout 75 is equivalent to message source with consumption figure 76, and isochronous controller 43 is equivalent to the message purpose.Turnout 75 is read and write the turnout counter in the isochronous controller 43 (Producer Counter) 435 and the value of consumption figure counter (Consumer Counter) 436 by message mechanism with consumption figure 76.

The more special message of a class is used for the power supply control to processing unit 45 in the message of output, though the target definite object processing unit of message, the actual energy supply control module that sends to of message.

Microcontroller 42 provides service for the abnormality processing in the data stream, and its effect is equivalent to the Interrupt Service Routine (ISR) in the original system.But, realizing on the controller independently that microcontroller 42 can be handled complicated more unusual owing to from original C PU, separate, and the message interface that can be provided by isochronous controller 43, realize configuration to data stream.

Fig. 7 B represents the interface synoptic diagram of microcontroller 42.As shown in the figure, microcontroller 42 has three interface 77-79.The abnormality processing message that interface 77 is accepted from isochronous controller 43; Interface 78 sends to isochronous controller 43 modules with control information; When interface 79 can not be handled complicated abnormal conditions when microcontroller 42, give CPU41 with forwards.Three kinds of processing modes are arranged here, one, the CPU outer at chip can keep the mode of interruption, and status register is provided, and message conversion become to interrupt compatible mutually with the description and the traditional structure of status word; Its two, for the CPU core 412 that embeds, in its periphery with the conversion of the packaged message of packing (Wrapper) to interrupt request (IRQ); Its three, the support that the processor unit 45 that provides for oneself directly gives information.

Fig. 7 C is the working state schematic representation of expression microcontroller 42.That microcontroller 42 is accepted is message bag (Message Packet), safeguards two tables, message table and trigger table (Trigger Table), and the maintenance of responsible turnout and consumption figure pointer (Pointer) to annular buffer 61.Mainly contain two duty configurations (Configuration) and search (Lockup).When isochronous controller 43 was in configuration, CPU41 can be configured microcontroller 42 by collocation channel (Config Channel).

During init state, microcontroller 42 initial message table, trigger table and counters.After the built-in variable initialization finished, microcontroller 42 changed wait (Wait) state over to.When intercepting and capturing configuration messages, microcontroller 42 is transferred to the state of configuration, and waiting system is to the configuration of its table with trigger table.Configuration file in system's reading database by the interface of isochronous controller 43, is adjusted look-up table.After layoutprocedure finished, system sent end, microcontroller 42 synchronous switchback waiting statuss.

Change the state of searching over to after system receives message, searching state, microcontroller 42 query messages are made corresponding processing, if to the operation of annular buffer, are safeguarded by trigger table and counter, if common message is transmitted message by table.

Processor

Fig. 8 represents the 45 pairs of resources allocations of processor and the operation chart that data stream is analyzed in the system of the present invention.Service layer realizes the reallocation of the resource in the network topology structure and high-level analysis to data stream with processor at top layer.In database, realize with two kinds of forms by database with the record of the form of database for 42 pairs of processing that make mistakes of microcontroller: during operation with form swap data between microcontroller 42 and processor 45 of shared storage 46.When system closing, with the data storage in the shared storage 46 in file system 80.In the time of system initialization, the data F in the file system (File System) 80 is downloaded in the storer.Processor 45 is analyzed according to the data in the shared storage 46, and by the configuration distributing system resource.

The service procedure that new framework provides

Compare with the conventional personal computer framework, Interrupt Process makes message-driven (Event Driven) into.Virtual component VC (Virtual Component) provide the unified interface that is used for Message Processing, and message changes the state of internal state machine as the excitation of outside, finishes the function of appointment.VC not only accepts message, and VC produces message equally.Message is placed in to be delivered on the messaging bus 44 in the microcontroller 42, and microcontroller 42 is searched corresponding action according to predefined look-up table, or transmits message, or handles impact damper (FIFO).Message mainly provides the service of two kinds of character, and the first kind is safeguard normal data stream synchronous, and second class is to send unusual request.After microcontroller 42 is received the request of abnormality processing, activate host Interrupt Service Routine ISR thereon to Message Processing.When microcontroller 42 runs into complicated situation more, in the time of can not disposable, microcontroller 42 be submitted to CPU41 with message, and CPU41 does the scheduling of tactic on higher level.In sum, system provides the service of four different levels to finish synchro control to real time data stream.

Fig. 9 represents a system service flow process.As shown in Figure 9, system will be realized in different modules by the unaided task distribution of CPU4I.VC has substituted the role of break in service thread IST, microcontroller 42 has been finished the message propagation function that original kernel program provides, and the Interrupt Service Routine ISR that has strengthened (can handle unusual) also carries out on microcontroller 42.Simplified the design of the OS of host on traditional C PU.

The realization of break in service thread IST

Realize the DSP that is not only of break in service thread IST, finish specific function ASIC also be a break in service thread IST, break in service thread IST just uses the noun of software here.Figure 10 represents the constitutional diagram of the break in service thread IST that realizes on the processor.

The variation of state is by message-driven, and processing unit self also produces message and gives isochronous controller 43 modules.Processing unit is in the order of init state acceptance from isochronous controller 43.After system provided " beginning data stream ", processing unit entered " wait " state, and " wait " state is accepted the message from " source ".When having data to handle among the buffer FIFO, " source " sends " beginning data stream ", by isochronous controller 43 notifier processes unit, processing unit enters " work " state processing data, when data need write among the FIFO, processing unit is checked fifo status, and when FIFO was " expiring ", processing unit can adopt two kinds of strategies.One, the action that generation writes makes FIFO produce the unusual of " overflowing ", unusual message and then by isochronous controller 43 notice microcontrollers 42,42 pairs of microcontrollers are made corresponding processing unusually, when processing can not be dealt with problems, reinform the break in service thread IST module on the CPU41, CPU41 coordinates on higher level.Its two, processing unit is not taked any reflection, makes data stream enter blocked state, is acted accordingly by other modules." stop " (Stall) state table and manage the unit in the open and take place unusually, after abnormal conditions were excluded, processing unit recovered " work " state.Can accept " stopping data stream " order when being in " wait " with " stopping " state at processing unit, the processing unit free system resources is returned " initially " state.

The treatment scheme of distributed multi-processor system

On system, this is the realization of parallel distributed system on system operation platform (SOC) of a multiple-instruction-stream multiple-data stream (MIMD); From the coupling angle of storer, this is a tightly coupled design, because system's shared storage.System is on another angle, and it is an asymmetrical parallel computation structure.Asymmetry is embodied in two aspects, one, processing unit provides system service in different levels, VC, processor provides processing power at the bottom, isochronous controller 43 has the synchronization of data streams between the module of processing power synchronously, and microcontroller 42 provides the network service of abnormality processing, and CPU41 finishes the distribution of system resource and high-level decision-making.Its two, at different algorithms, the design of DSP can be different; Because the characteristics of isomery (asymmetric), system design will be considered following a series of problems:

A) (Transparency, its implication is that twice developer (programming personnel) of system takeed for is the system of a uniprocessor to system designer to the transparency.In system design process, consider the design of development environment and the foundation of system platform simultaneously.

Software and hardware combined design, comprehensive verification instrument will be integrated in the development environment aspect, and provide complete compiling solution for the programming personnel.Figure 11 is the synoptic diagram of the parallel co-design of expression software and hardware, checking.

System platform will provide two kinds of solutions:

The first, utilize Java VM (virtual machine) to solve the isomery problem, Figure 12 is the synoptic diagram that expression utilizes the heterogeneous system platform that virtual machine technique provides.

The second, utilize Code Morph (code form) technology to solve the isomery problem, Figure 13 is the synoptic diagram that expression utilizes the heterogeneous system platform that code conversion provides.

B) reliability, its implication be system under the situation of section processes unit exception, still can operate as normal.Be different from the design of Intranet or Internet for the design of a SOC, reliability no longer is a problem.

C) performance because the design of SOC does not relate to the restriction of bandwidth and fault-tolerant cost, can realize good performance requirement equally.

D) scalability is the system architecture of basic framework with the network, and very strong extensibility is arranged in design, along with the maturation of multiplex technique, is that the advantage of basic framework is more obvious with the network.

E) concurrency

F) validity

During initialization, the distribution of system resource

Figure 14 is the synoptic diagram of expression system resource allocation.The resource of system comprises input-output device (IO), storer and processor.In general, IO is not a kind of sharable resource, but we also consider the characteristic that it is shared for the design of USB or 1394.They are the extension of bus in fact, and same network interface card is all the more so; The data bus of system also is a resources shared.

When system is written into certain application, CPU reads the demand schedule of application to system from storer, the content of demand schedule comprises, IO, the processing unit that data stream is required, the size of the annular buffer that processing unit needs, and relevant software module (Interrupt Service Routine ISR, break in service thread IST) and message table.

System is by collocation channel initialization IO, FIFO, and the message table of microcontroller 42, and Interrupt Service Routine ISR downloaded on the corresponding microcontroller and DSP with the code of break in service thread IST.

System discharges resource under following two kinds of situations

The first, during the system resource wretched insufficiency, system cancels unessential application, discharges the corresponding system resource of this application.

The second, use the end process process, when logging off, the request of resource is proposed to discharge to system.

During operation, the dynamic dispatching of system resource

The static allocation resource has many deficiencies concerning the system that supports the multiclass application.When system resource was not enough, system was if support dynamically to adjust resource, and the system of can be brings greater flexibility.Can be from the resource of two aspect Adjustment System.

The first, when memory resource was not enough, system's release portion was used shared internal memory, still can normally carry out but guarantee to use.

The second, when the processing unit processes ability can not satisfy the multitask support, idle processing unit will be inquired about by system, and code and environment are moved on on this processing unit.By the seamless link of system to Internet, system can submit to processing unit among the Internet to task, and Distributed Calculation is expanded among the Internet.

System is to the support of the framework of multiprocessor

Be in the structure of basic framework with the network, because the existence of shared drive, the exchange between the data no longer needs the notion of router (router), but system has kept bridge (Bridge), with different territories (domain) separately.

The communication of each processing unit is coordinated each processing units 45 by unique service channel (Service Channel) with compositions such as the hard interruption synchronous signal lines between messaging bus, the node by isochronous controller 43.

The agreement of messaging bus

The messaging bus agreement has stipulated to be used between the VC frame format and the transmission mode of synchronous incident, and the agreement of messaging bus also comprises the command format that is used to control.

The definition of data type

When certain VC produced certain incident and needs other modules of reporting system, this VC filled in the message and the address entries of incoming event (InEvent), then InEvent is reached microcontroller 42 by messaging bus 44.Microcontroller 42 is searched corresponding outgoing event (OutEvent) according to InEvent in message table, and according to the destination address among the OutEvent OutEvent is sent to corresponding VC.Corresponding VC reads the message content of OutEvent, takes corresponding action according to content.InEvent, outEvent and message table are defined as follows:

The definition of source address event data structure

TypelnEvent

Byte?SourceAddress

Byte?Message

End?of?Type

The definition of destination address event data structure

Type?OutEvent

Byte?DestinationAddress

Byte?Message

End?of?Type

The definition of message table data structure

Type?EventCoordinatorTableItem

InEvent?in

OutEvent?out

End?of?Type

The definition of address

VC on messaging bus 44 has corresponding address corresponding with it, according to dissimilar four classes that are divided into of VC:

Event microcontroller self.

The common processing unit of normal node (Normal Node) (ASIC, DSP)

Interrupt generator IO controller

Counter annular buffer

The geocoding of this four class is as follows, and geocoding has taken into full account the extensibility of system.

Address (Address)	VC
		b’00000000	Incident microcontroller state
b’00000001 b’01111110	Normal node
		b’01111111	Interrupt generator
b’11111000	Counter b ' 000～b ' 111

b’11111111

The definition of message

The message of event coordination program (Event Coordinator) input

The message of input is divided into two classes by its effect: a class is self-defining message, and VC can define the message of oneself as required; One class is the message that is used for annular buffer control, comprising the control of annular buffer head and the tail pointer plus-minus and the setting of trigger (Trigger).

The message scope	Message definition
		B’00000000	No message
B’00000001 ～ b’00011111	Normal messages (user definition) 31 every node messages
		b’001--XXX	Counter b ' XXX++*
b’010--XXX	Counter b ' XXX-
		B’011--XXx	Counter b ' XXX to b ' 0000 is set
B’101vvxxx	Trigger b ' the XXX to b ' 00VV of one counter is set
		b’11VVVXXX	Be provided with ++ trigger b ' the XXX to b ' 0VVV of counter

The message of event coordination program output

The message of output is divided into four classes according to effect:

Self-defining message (normal messages);

To the message of vc state machine control, as continuing (Hold on), recover (Resume), power supply closes/opens (Power Off/On);

The transmission of parameter is used for microcontroller and transmits parameter to VC.

Abnormality processing is handled for the unusual request upper level CPU41 that can not handle.

The message scope	Message definition
		b’00000000	No message
b’00000001 ～ b’00011111	Normal messages (user definition) 31 every node messages
		b’001----- b’010----- b’100----- b’101-----	Continuing to recover power supply pass power supply opens
b’110XXXXX	Parameter X XXXX
		b’11111111	For will producing, abnormality processing interrupts to CPU

Shared storage

Figure 15 is the synoptic diagram of expression shared storage technique.In conjunction with reference to Fig. 4, the data transmission between storer is adjacent is to carry out with different units like that by Figure 15: the data between CPU41 (register of CPU41 only is shown among Figure 15) and the cache memory 413 are pressed word (4 bytes); Data connect piece (32 bytes) transmission between cache memory 413 and the system storage 414; Connect a page swap data between system storage 414 and the disc (Disk).

The consistance of high-speed cache

Consistance is meant that same data item should be consistent with the copy on the follow-up memory hierarchy.Because multiprocessor is mutual operation asynchronously, therefore the copy of the same cache line in a plurality of cache memories may be different.Cause the inconsistent reason of cache memory to derive from: 1) but by sharing inconsistent that write data causes; 2) by process migration cause inconsistent; 3) operate cause inconsistent by the I/O that walks around cache memory.

The employing of agreement

Monitoring protocols is used by the multicomputer system that bus connects, and native system belongs to multistage interconnected multicomputer system, adopts the agreement (Directory Based Protocol) based on catalogue.Figure 16 shows the synoptic diagram of this multistage interconnected multicomputer system data transfer protocol.DI is given in the request of disappearance (Read-Miss) generation of reading of cache memory CZ (representing with fine rule among the figure), and the DI indication has available copies in CI, and memory controller is sent to CI with request again, and it returns an available copies and gives M1 and C2; (represent with thick line among the figure) in the time of in the C1 write order that it just sends an order to memory controller, memory controller is sent out an invalid order again and is given markd all cache memories (C2) in DI.In a word, the cache coherent protocol that need not broadcast must store the address of each the shared data piece copy in all high-speed caches.

About MMU

A simple thread scheduler host is on DSP.Microcontroller 42 also only needs an interrupt service routine (Interrupt Service Routine ISR).For the algorithm that great majority are handled in real time, the address space size of data occupancy can accurately be estimated.So the design for DSP and RISC does not need to consider that memory management unit provides the support to the virtual address.The storer of sharing is mainly used in the exchanges data of real time data stream, and in order to guarantee real-time, processing unit does not adopt the MMU unit as far as possible yet, has simplified the design of processing unit and OS.

Services sub-network is to the support of power management

The function opposite independent of each subnet

In the design of system, taken into full account the relative independentability of each subnetwork functionality.The normal operation that has independently guaranteed when certain processing unit in certain subnet or the subnet quits work, not influence miscellaneous part on the function.Independence on the function also require when design each submodule relatively independent for clock (Clock) with the input of power supply (Power).The network topology structure of system and hierarchical structure (hierarchy) provide structural support for the encapsulation of function.The principle of dividing subnet is different according to the difference of function.

Processing unit in each subnet is to the support of power management

Figure 17 shows the power management synoptic diagram of the processing unit in each subnet, and it comprises sleep state (Sleeping); Duty (Running); Wait for (ready) state (Waiting); Blocked state (Blocking).After processing unit is finished certain task, transfer to waiting status, or processing unit transfers to blocked state from duty under the situation that executive condition does not have to satisfy, after condition satisfies, enter waiting status from duty.Processing unit does not change sleep state over to after waiting status is handled request for a long time.

Processing unit enters the preceding state of wanting reservation process unit self of sleep state, if processor, these states mainly are the registers of processor.Notification service subnet then.Processing unit is activated (Active) from sleep state need be by external request (generally being interrupt response, be synchronizing signal or message in native system).Figure 18 shows the power management synoptic diagram of microcontroller to processing unit.

Services sub-network provides the control to power management

Figure 19 shows the management synoptic diagram of the power supply of services sub-network.Services sub-network is received when some processing unit in other subnet enters sleep state and can be offered the clock frequency (Clock) of subnet or not provide clock to overturn to this subnet or this processing unit by switching after the message; Also can reduce the operating voltage of this subnet or processing unit or operating voltage is not provided.

More than two kinds of means all need services sub-network to perform an analysis in conjunction with demands of applications from the angle of total system, take measures afterwards.Switching offers the clock frequency (Clock) of subnet or the clock upset is not provided is topmost means.

Below will be respectively be example with the dynamic application of MP3 voice playing and jpeg image compression function, specifically describe this realization of two kinds of functions in adaptive information processing system of the present invention (hereinafter to be referred as system).

MP3 algorithm (decoding) is analyzed

MP3 is the 3rd layer (LayerIII) of MPEG sound intermediate frequency coding, and it is based on the psychoacoustic model voice data code decode algorithm of a more complicated.It has higher compressibility (can reach 12: 1) and better tonequality than the ground floor (LayerI) and the second layer (LayerII).So because it has higher compressibility and better tone quality is fit to (Internet) propagation on the internet very much.Downloading also from internet, the real-time play voice data will satisfy following two conditions: one, because the bandwidth constraints of internet, a large amount of voice datas need be through overcompression, in order to improve the algorithm that compressibility generally adopts lossy compression method, but will guarantee lower degree of distortion.Its two, decoding algorithm (compression back reduction) can be had the processing capability in real time arithmetic element to be realized, decoding algorithm can not be too complicated in other words, algorithm is easy to be realized by software or hardware-accelerated (ASIC).MP3 is exactly a reasonable algorithm, can satisfy above 2 points simultaneously.

MP3 supports three kinds of sampling rate: 32KHZ, 44.IKHZ, 48KZ.The frame length of MP3 decoding algorithm is: 1152/ sample frequency (millisecond).Every frame comprises the 1152PCM sampling point.Decoding is output as 16 bit linear PCM sampling points.

The analysis (discretize) of MP3 data stream (decoding algorithm)

Downloading also from internet, the flow process of real-time play voice data comprises three parts: data are downloaded, data decode and audio data playback.Figure 20 is the synoptic diagram of 3 steps of expression MP3 decoding flow process.Referring to Figure 20, in the data download module, system inserts internet Internet by network interface card or modulator-demodular unit (Modem) in wired or wireless mode, downloads the voice data of MP3 format by procotol.Wherein, step S201 downloads voice data; Step S202 decodes to voice data; Step S203, the plays back audio data.

Figure 21 shows the flow process of audio data download step S201.According to Network Transmission and control protocol (TCP/IP), data download module need be divided into three steps the data in the network are changed into voice data: step S211 belongs to physics realization, accept raw data with the physical address (MAC) corresponding (consistent) of system in shared drive by network interface card or modulator-demodular unit (Modem), remove frame head information and give step S212 continuation processing the IP bag; Step S212, different IP bags need form the TCP section with the rearrangement of IP bag at step S212 and give step S213 through the order difference of different network path arrival systems; Step S213 finally takes out voice data and gives corresponding handling procedure according to corresponding ports number.Step S212 and step S213 belong to logic realization.

Figure 22 represents the synoptic diagram of a voice data decoding step S202, and it comprises four steps: bit stream unpacks and Huffman decoding (S221); Send quantification and reset preface (S222); Joint stereo is handled (S223); Composite filter (S224).

Bit stream unpacks and decodes with Huffman is that demoder unpacks quantized value and some sidebands letter think of of decoding and can obtain 576 frequency row (each sound channel) with Huffman by bit stream, if the Huffman code bit of decoding more than the code bit number that must decode, so just has more the position to these and abandons as filling up the position.

Re-quantization is that 576 frequency row that obtain are sent into inverse quantizer with resetting preface, has used informal quantizer in MP3.Informal quantizer has adopted the power rule, and even the Huffman decoding is output as is, needs when carrying out re-quantization to calculate | is| ^4/3, in software is realized, finish by tabling look-up.If use short block, then need to reset preface.

It is at re-quantization (resetting preface) afterwards that joint stereo is handled, and handle the reconstruction value under MS stereo mode and the intensity stereo pattern (being learnt the relation of MS stereo mode and intensity stereo pattern in side information by the sign indicating number type of mode_extension).

Composite filter comprises that IMDCT is synthetic and heterogeneous synthetic.

Figure 23 represents an audio data playback synoptic diagram, and it is that voice data is exported to D/A converter through serial, outputs analog signal to playback system at last.

The realization (mapping) of MP3 voice playing function in system

Figure 24 represents the connection diagram of native system and internet.System is as the handheld terminal (mobile computing platform) on the internet, and it is the extension of internet.Because system and internet (Internet) adopt same network topology structure, system has formed seamless being connected with internet.

Chip internal has been realized a distributed computing environment with topology of networks.Each processing unit in the above-described MP3 decoding algorithm will be mapped to respectively in the different subnets, and Figure 25 is the synoptic diagram of the realization of expression MP3 voice playing function in native system.

Figure 25 is divided into two parts: the first half is the description of MP3 decoding algorithm, and it is certain specifically one of application that system will realize.It comprises that network connects three parts of MP3 decoding and audio data playback; The latter half is the concrete scheme that system realizes.It is to be core with services sub-network and shared storage 46, and by data bus and messaging bus 44 communication subnet 402, multimedia subnet 401 being serially connected with input and output subnet 403 constitutes the distributed computing environment with network topology structure.System realizes (SOC) in single-chip.

The mapping relations of two parts up and down also have been described among Figure 25, and these mapping relations have shown that the MP3 decoding algorithm is (is in the system framework which processing unit realized which function in the algorithm) that how to be distributed on the system framework.Error-detecting and correction and framing 2511 are realized that by hardware asics 2521 major function is the mistake that adopts in parity checking detection and the correction data transmission, physical signalling is changed into Frame be stored in the internal memory; The TCP/IP header packet information is analyzed with translation data form 2512 and is realized by the DSP2522 in communication subnet, and major function is to extract the header packet information of TCP/IP, and header packet information is used for determining the intended application of MP3 data stream correspondence.If data maybe need be authorized when could visit through encrypting, need through Data Format Transform; Bitstream decoding, the Huffman decoding, existing sequencing of re-quantization and frequency spectrum and joint stereo handle 2513 by the processing unit in the multimedia subnet (being DSP) 2523 realizations here, and major function is to the decoding of MP3 voice data; Synthetic filtering 2517 realizes it being because comprise a large amount of parallel datas in the algorithm by a DSP2524 separately, need to support the processor of SIMD instruction set to finish, SIMD (SingleInstruction, Multi Data) is meant that individual instructions can handle the data of multichannel same nature; Serial output 2518 and D/A (digital-to-analog conversion) 2519 are realized finishing the playback of voice data by the hardware asics in the input and output subnet 403 2525.

Each parts effect of services sub-network among the figure is as follows:

Three isochronous controllers are controlled the synchronization of data streams of processing unit in the subnet separately respectively.The corresponding one or more synchronization cachings (annular buffer) of each isochronous controller.Synchronization caching (annular buffer) is a zone of shared storage 46, writes synchronization caching when data source produces data, and the data source pointer adds one, and when datum target will be consumed frame data, from the synchronization caching reading of data, the datum target pointer added one.The explanation synchronization caching living overflow (Overflow) of having produced at full capacity when the data source pointer catch up with the datum target pointer, overflow explanation data source produces the speed of the speed of data greater than the datum target consumption data.The empty underflow (Underflow) that produces of explanation synchronization caching when the datum target pointer catch up with the data source pointer, the speed of underflow explanation datum target consumption data produces the speed of data greater than data source.Underflow and overflow all are abnormal conditions.Figure 26 shows the operation chart of synchronization caching.

Three isochronous controllers are used for accepting to the synchronizing signal of data source (Source) with datum target (Sink), receive that data source pointer and datum target pointer add one respectively after the synchronizing signal;

Three isochronous controllers are used for the synchronous of coordination data source (Source) and datum target (Sink);

The abnormal conditions (overflow and underflow) that three isochronous controllers are used for handling report microcontroller 42;

Microcontroller is used to accept the abnormal conditions (overflow and underflow) that isochronous controller provides; And be used for these abnormal conditions (overflow and underflow) are handled;

Microcontroller is used for the processing unit of each subnet or input/output control unit (IOController) are controlled; And be used for abnormal conditions are recorded in database (Data base), analysis provides foundation to abnormal conditions for CPU;

The abnormal conditions that microcontroller is used for handling report CPU, and the abnormal conditions that can not handle are because the unusual reason of generation is to be produced by the processing unit of being separated by far away in the data stream.

CPU is used to accept the abnormal conditions that microcontroller can not be handled, and is used to handle these abnormal conditions;

CPU is used to accept to be used for the input and output request of man-machine interface;

CPU is used for the abnormal conditions record of reading database;

CPU is used for the abnormal conditions record of analytical database, according to the Adjustment System of analyzing as a result;

CPU is used for the reallocation to system resource, and system resource comprises processing unit, internal memory etc.;

CPU is used for the data cutout of data stream and carries out the analysis of intelligence, and is used for data cutout and storage to data stream.

The processing procedure of MP3 decoding is as follows: the signal that the hardware handles unit (ASIC) 2521 in the communication subnet is accepted to internet, and physical signalling changed into Frame, Frame is stored in the shared drive, send synchronizing signal to isochronous controller 43A, isochronous controller produces synchronizing signal and gives the DSP2522 that is used for the TCP/IP processing; After this DSP2522 receives synchronizing signal, reading of data from shared drive, and, the needs decrypted data is carried out format conversion to the analysis of TCP/IP packet header; Data storage that will be relevant with audio frequency after the process format conversion is at shared drive, and this shared drive to total system as seen.Produce synchronizing signal afterwards and give isochronous controller 43A, isochronous controller 43A is transmitted to isochronous controller 43B with synchronizing signal, isochronous controller 43B notifies the bitstream decoding that is used in the multimedia subnet 401, the Huffman decoding, the DSP2523 module that existing sequencing of re-quantization and frequency spectrum and joint stereo are handled, bitstream decoding, the Huffman decoding, re-quantization is handled corresponding different task (Task) respectively with the existing sequencing of frequency spectrum with joint stereo.Several tasks are carried out on same DSP, and the task dispatch on the DSP is arranged, and call and coordinate switching between the different task.The data of 576 sampled points are divided into 32 the tunnel, by supporting that (Single Instruction, DSP MultiData) finishes synthetic SIMD.Finishing by isochronous controller 43B synchronously between two DSP.Divide left and right acoustic channels to be stored in the visible shared storage of total system through synthetic data.Isochronous controller 43B produces synchronizing signal and gives codec (Codec) chip that is used for serial conversion and D/A conversion in the input and output subnet 403.The voice data output of the PCM form of the standard that the Codec chip obtains after receiving and will decoding after the synchronizing signal.

When abnormal conditions occur, isochronous controller will report microcontroller unusually, and microcontroller can (ASIC, the control register that DSP) provides be controlled each processing unit, get rid of abnormal conditions by being distributed in processing unit in each subnet.Have several modes to adopt: one stops or delay process parts faster: its two, adjust the size of synchronization caching (annular buffer); Its three, make the slower processing unit of processing skip some Frame.Microcontroller is recorded in abnormal conditions in the system database, submits to CPU unusually and microcontroller still can't be handled.

CPU to being analyzed unusually that system produces, by to the redistributing of system resource, gets rid of abnormal conditions from higher level.The strategy of taking can be to distribute idle processor resource to reach the balance of system.Also can be angle, reduce the computational accuracy of part algorithm component, improve the real-time respective capabilities of system from algorithm.CPU can read and write processing unit (ASIC, the control that the control register that DSP) provides is indirect and the work of coherent system that is distributed in each subnet by microcontroller.

The realization in the present invention of jpeg image compression function

The realization of dynamic application in adaptive information processing system of the present invention (hereinafter to be referred as system) of Figure 27 to 31 expression jpeg image compression function.

The JPEG compression algorithm is analyzed

JPEG is a kind of compression standard of static coloured image journey ash trial image, and it is that compression for continuous-tone image provides public standard to design.This standard can produce by various multimedia storages and the employed gray level image of communications applications, photographs and static video compress file.JPEG is a kind of symmetry algorithm, is the inverse process of compression fully because decompress.Being input as source image data and showing explanation of scrambler is output as compressing image data; Being input as compressing image data and showing explanation of demoder is output as the reconstructed image data.Source images and reconstructed image all are continuous tone, and they are made up of a plurality of components, and (coloured image is made up of a plurality of components, as RGB; Gray image only is made up of one-component).Joint Photographic Experts Group designs at many component images, and it comes image data processing with a kind of method that is independent of application flexibly.We adopt the image of YUV color space as source images and reconstructed image.

The analysis (discretize) of video conference (Netmeeting) data stream

Figure 27 is the process flow diagram of expression with JPEG realization video conference function, and it comprises three parts: ccd data gathers 271, JPEG compression 272, data transmission 273.

The data that I in the ccd data acquisition module 271, CCD sample are that the component of a RGB is represented a point, through each point three representation in components of RGB after interpolation (Interpolation) module; By extracting pixel wherein, can reach the effect (Scaling) of changing image size.In look conversion (ColorConversion) module, as shown in figure 28, data are transformed into yuv format from RGB by matrix computations.

Figure 29 is the synoptic diagram of expression JPEG compression process 272.Referring to Figure 29, produce the DCT coefficient through cosine transform; Behind the DCT coefficient quantization, significant value (nonzero value) all concentrates on the upper left corner of matrix.Sequence (Zigzag) can make the length of null value in the distance of swimming increase by the rearrangement distance of swimming in a zigzag, further improves compressibility with this; After the output of Huffman coding.

Figure 30 is the synoptic diagram of the USB transfer process of expression data output 273.Referring to Figure 30, data output is that the data after the compression are uploaded to PC through USB.Because USB data in transmission course may be lost or be wrong, system need carry out again the synchronous and recovery (Error Recover) that makes mistakes to data stream.The synchronization means of two different phases is provided here: the firstth, with every frame picture synchronization; The secondth, synchronous with the decoding unit MCU bag of JPEG minimum.

Figure 31 is the synoptic diagram of the realization of expression video conference in system of the present invention.Wherein, chip internal has been realized a distributed computing environment with topology of networks.Each processing unit in the above-described JPEG compression algorithm will be mapped to respectively in the different subnet (Subnet).

Figure 31 is divided into two parts: the first half is the description of JPEG compression algorithm, and it is certain specifically one of application that system will realize.It comprises ccd data collection 271, and JPEG compression 272 is exported 273 3 parts with data; The latter half is the concrete scheme that system realizes.It is to be core with services sub-network and shared storage 46, and by data bus and messaging bus 44 multimedia subnet 401 and input and output subnet 403 being serially connected constitutes the distributed computing environment with network topology structure.System realizes (SOC) in single-chip.

The mapping relations of two parts up and down also have been described among the figure, and these mapping relations have shown that the JPEG compression algorithm is (is in the system framework which processing unit realized which function in the algorithm) that how to be distributed on the system framework.Ccd data collecting part 271 is by CCD controller image data, interpolation (Interpolation), scaling (Scaling), look conversion (Color Conversion) are to be realized by the ISC module, because inlet flow do not need to equate synchronization module with output stream speed.The JPEG compression is realized by the DSP of multimedia subnet 401, owing to big registers group is adopted in the design that needs a large amount of matrix operation DSP, and provides the support of multimedia instruction.After one frame data have been compressed, produce synchronizing signal and give isochronous controller 43B; Isochronous controller 43B is divided into data the bag (long 1023 bytes of bag) of USB with another DSP of signal triggering multimedia subnet 401, this DSP.Trigger USB controller in the input and output subnet 403 by isochronous controller 43B, the DMA of USB controller with data upload to the usb data bus.

Each parts effect of serving net 404 among the figure is as follows:

Three isochronous controllers are controlled the synchronization of data streams of processing unit in the subnet separately respectively.The corresponding one or more synchronization cachings (annular buffer) of each isochronous controller.Synchronization caching (annular buffer) is a zone of shared storage 46, writes synchronization caching when data source produces data, and the data source pointer adds one, and when datum target will be consumed frame data, from the synchronization caching reading of data, the datum target pointer added one.The explanation synchronization caching living overflow (Overflow) of having produced at full capacity when the data source pointer catch up with the datum target pointer, overflow explanation data source produces the speed of the speed of data greater than the datum target consumption data.The empty underflow (Underflow) that produces of explanation synchronization caching when the datum target pointer catch up with the data source pointer, the speed of underflow explanation datum target consumption data produces the speed of data greater than data source.Underflow and overflow all are abnormal conditions.The operation chart of representing synchronization caching referring to Figure 26.

Three isochronous controllers are used for accepting from the synchronizing signal of data source (Source) with datum target (Sink), receive that data source pointer and datum target pointer add one respectively after the synchronizing signal;

Three isochronous controllers are used for the synchronous of coordination data source (Source) and datum target (Sink), and the abnormal conditions (overflow and underflow) that are used for handling report microcontroller 42.

Microcontroller is used to accept the abnormal conditions (overflow and underflow) that isochronous controller provides, and the abnormal conditions (overflow and underflow) that are used for isochronous controller is provided are handled;

Microcontroller is used for the processing unit of each subnet or input/output control unit are controlled;

Microcontroller is used for abnormal conditions are recorded in database, analysis provides foundation to abnormal conditions for CPU, and the abnormal conditions that are used for handling report CPU, and the abnormal conditions that can not handle are to be to be produced by the processing unit of being separated by far away in the data stream because produce unusual reason.

CPU is used to accept the abnormal conditions that microcontroller can not be handled, and is used to handle the abnormal conditions that microcontroller can not be handled;

CPU is used to accept to be used for the input and output request of man-machine interface;

CPU is used for the abnormal conditions record of reading database;

CPU is used for the abnormal conditions record of analytical database, according to the Adjustment System of analyzing as a result;

CPU is used for the reallocation to system resource, and system resource comprises processing unit, internal memory etc.:

CPU is used for the data cutout of data stream and carries out the analysis of intelligence, and is used for data cutout and storage to data stream.

When abnormal conditions occur, isochronous controller will report microcontroller unusually, and microcontroller can (ASIC, the control register that DSP) provides be controlled each processing unit, get rid of abnormal conditions by being distributed in processing unit in each subnet.Have several modes to adopt: one stops or delay process parts faster; Its two, adjust the size of synchronization caching (annular buffer); Its three, make the slower processing unit of processing skip some Frame.Microcontroller is recorded in abnormal conditions in the system database, submits to CPU unusually and microcontroller still can't be handled.

CPU to being analyzed unusually that system produces, by to the redistributing of system resource, gets rid of abnormal conditions from higher level.The strategy of taking can be to distribute idle processor resource to reach the balance of system.Also can be angle, reduce the computational accuracy of part algorithm component, improve the real-time respective capabilities of system from algorithm.CPU can read and write processing unit (ASIC, the control that the control register that DSP) provides is indirect and the work of coherent system that is distributed in each subnet by microcontroller.

Below described the principle of adaptive information processing system of the present invention and the realization of dynamic application in adaptive information processing system of the present invention of formation and MP3 voice playing function and jpeg image compression function respectively, it is to be noted that these use the special case of the concrete application that only is adaptive information processing system of the present invention.According to foregoing of the present invention, those skilled in the art can also and should be used as further conversion to the present invention, but these conversion all belong to scope of the present invention.

Claims (7)

1. information handling system with network topology structure comprises:

A. system service sub-network, it comprises:

The CPU (central processing unit) that is used for system management, coordination and Intelligent treatment;

For system provides interrupt response and break in service, and in order to the microcontroller of each processor cell operation in the coherent system;

Be connected to described microcontroller, in order to the isochronous controller of the exchange of the real time data stream between module in the synchro system and the module;

Hard real-time synchronous signal line by messaging bus and intermodule is formed, and comprises the system service channel of interruption, synchronous system service message in order to transmission:

Described microcontroller comprises that the risc chip be made up of general-purpose register and arithmetic logical operation unit, interruptable controller, acceptance are from first interface of the abnormality processing message of isochronous controller, send to second interface of isochronous controller and the 3rd interface of the abnormality processing forwards being given CPU (central processing unit) with control information;

Described isochronous controller is realized at interior special IC by comprising turnout counter and consumption figure counter;

Described CPU (central processing unit), microcontroller and isochronous controller constitute a system services layer and are connected by described service channel,

B. at least one application oriented processing sub-network, it comprises:

Handle the processor of redistribute resources and the high-level analysis of data stream, it accepts the command process data from isochronous controller, and notifies microcontroller with abnormality processing message via isochronous controller;

Shared storage in order to swap data between microcontroller and processor;

The data source device of data input is provided;

The datum target device of data output is provided,

Described processor, shared storage, data source device and datum target device are connected to described messaging bus via each bar bus respectively,

C. in order to the system bus of transmission data, wherein, described system service sub-network and application are handled sub-network and are connected to system bus by the data bus of different rates respectively.

2. information handling system as claimed in claim 1 is characterized in that, described messaging bus is followed the system information transportation protocol and is connected with each correlation module in the system, transmits interrupting information and associated packet with the incident form.

3. information handling system as claimed in claim 1 is characterized in that, described shared storage entity is distributed in each and uses in the processing sub-network, and allows the cross-domain visit of associative processor.

4. information handling system as claimed in claim 1 is characterized in that, described application is handled sub-network and comprised the Intelligent treatment sub-network that is made of CPU (central processing unit) and system storage.

5. information handling system as claimed in claim 1 is characterized in that, described application is handled sub-network and comprised the communicator network.

6. information handling system as claimed in claim 1 is characterized in that, described application is handled sub-network and comprised the multimedia sub-network.

7. information handling system as claimed in claim 1 is characterized in that, described application is handled sub-network and comprised the input and output sub-network.

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