CN1173271C - High speed buffer storage system with double high speed buffer mapping storage - Google Patents
High speed buffer storage system with double high speed buffer mapping storage Download PDFInfo
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- CN1173271C CN1173271C CNB991270541A CN99127054A CN1173271C CN 1173271 C CN1173271 C CN 1173271C CN B991270541 A CNB991270541 A CN B991270541A CN 99127054 A CN99127054 A CN 99127054A CN 1173271 C CN1173271 C CN 1173271C
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Abstract
The present invention relates to a cache system of a comptuer. Data addresses of the cache system comprise a lower-order cache wire address and a high-order interval address. The cache system comprises a data cache, two mapping caches and a cache controller; when data is to be read or written into the cache system, a processor transmits the data address of the data in a main memory to the cache system; a cache wire address in the data address makes a second interval address and a secondary interval address which are correspondingly stored in the primary mapping cache and the secondary mapping cache output to the cache controller so as to compare an interval address in the data address with the primary interval address and the secondary interval address.
Description
The present invention refers to a kind of computer cache memory system that includes two speed buffering mapping memories especially relevant for a kind of computer cache memory system.
See also Fig. 1, Fig. 1 is the functional-block diagram that becomes known for the cache memory system 12 of a computer 10.Computer 10 includes a central processing unit 14, one first address bus 16, be electrically connected on processor 14, be used for transmitting and can read the data address (data address) 22 that respectively stores address 20 in (access) primary memory 18, and one first data bus 24, be electrically connected between processor 14 and the primary memory 18, be used for Data transmission.Data address 22 includes the cache line address (cache line address) of a low order and the interval address (blockaddress) of a high significance bit.
Cache memory system 12 includes a cache data memory (cache datamemory) 26, one speed buffering mapping memories 34, and a director cache 36 is used for controlling the operation of cache memory system 12.Cache data memory 26 is to be electrically connected on one second address bus 28 and one second data bus 30, and it includes the data that a plurality of storages address 32 is used for temporarily depositing in the primary memory 18 and uses for processor 14.The data that respectively store in the address 32 of cache data memory 26 can be read by the cache line address of second address bus 28.
Speed buffering mapping memory (cache tag memory) the 34th is electrically connected on second address bus 28, it includes a plurality of storages address 38, a plurality of storages address 38 of speed buffering mapping memory 34 is corresponding with a plurality of storages address 32 of cache data memory 26, is used for temporarily depositing the interval address of corresponding storage address 32 interior data of being deposited in the cache data memory 26.
When processor 14 desires are read data or are write cache memory system 12, processor 14 can reach cache memory system 12 via second address bus 28 with the data address 22 of these data in primary memory 18, cache line address in the data address 22 can make the interval address of being deposited in the corresponding storage address 38 in the speed buffering mapping memory 34 export director cache 36 to, and director cache 36 then can compare interval address in the data address 22 and the interval address that stores in the address 38.When if the interval address interior with storing address 38, the interval address in the data address 22 conforms to, the data that director cache 36 can transmit processor 14 via second data bus 30 write in the cache data memory 26 with the corresponding storage of the cache line address of data address 22 address 32 in, or will store address 32 interior data of being deposited reaches processor 14 via second data bus 30.If the interval address in the data address 22 is during with the interval mail returned on ground of incorrect address that stores in the address 38, director cache 36 can start exchange (swap) program with in the cache data memory 26 with data address 22 in the corresponding storage of cache line address address 32 in the Data Update of being deposited be in the primary memory 18 in data address 22 stored data, and upgrade the interval addresses of being deposited in the corresponding storage addresses 38 in the speed buffering mapping memory 34.
Interval address in data address 22 is during with the interval mail returned on ground of incorrect address that stores in the address 38, director cache 36 can upgrade the storage address 32 interior data of being deposited in the cache data memory 26, and can upgrade the interval addresses of being deposited in the corresponding storage addresses 38 in the speed buffering mapping memory 34.If processor 14 desires to read a certain data of seldom using, director cache 36 still can start this exchanger with making or have much ado and upgrade the data that store in the address 32,38, so wastes very much the time of computer 10 computings.
Therefore, fundamental purpose of the present invention is to provide a kind of computer cache memory system that includes two speed buffering mapping memories to solve the problems referred to above.
A kind of cache memory (cache memory) system that is used for a computer provided by the invention, this computer package contains a central processing unit, one address bus (address bus), be electrically connected on this processor, be used for transmitting and can read the data address (dataaddress) that respectively stores the address in (access) primary memory, an and data bus (data bus), be electrically connected on this processor, be used for Data transmission, this data address includes the cache line address (cache line address) of a low order and the interval address (block address) of a high significance bit, this cache memory system includes: a cache data memory (cache data memory), be electrically connected on this address bus and data bus, it includes the data that a plurality of storages address is used for temporarily depositing in this primary memory and uses for this processor, and wherein the data that respectively store in the address of this cache data memory can be read by the cache line address of this address bus; One first speed buffering mapping memory (firstcache tag memory), be electrically connected on this address bus, it includes a plurality of storages address, a plurality of storages address of this first speed buffering mapping memory is corresponding with a plurality of storages address of this cache data memory, is used for temporarily depositing the interval address of the data of being deposited in the corresponding storage address in this cache data memory; One second speed buffering mapping memory (second cachetag memory), be electrically connected on this address bus, it includes a plurality of storages address, a plurality of storages address of this second speed buffering mapping memory is corresponding with a plurality of storages address of this cache data memory, and each that is used for temporarily depositing this cache data memory that this address bus transmits stores the up-to-date interval address of address; And a director cache (cache controller), be used for controlling the operation of this cache memory system; It comprises: one first comparator circuit, its input end is output terminal and this address bus that is electrically connected on this first speed buffering mapping memory, and whether the interval address that is used in this data address that comparison transmitted by this address bus conforms to the first interval address of this first speed buffering mapping memory output; One second comparator circuit, its input end is output terminal and this address bus that is electrically connected on this second speed buffering mapping memory, and whether the interval address that is used in this data address that comparison transmitted by this address bus conforms to the second interval address of this second speed buffering mapping memory output; Wherein when this cache memory system is read or write to this processor desire with data, this processor can reach this cache memory system via this address bus with the data address of these data in this primary memory, cache line address in this data address can make the one first interval address and the one second interval address of being deposited in the corresponding storage address in this first and second speed buffering mapping memory export this director cache to, this director cache then can compare the interval address in this data address respectively with this first and second interval address, when if the interval address in this data address conforms to this first interval address, this director cache can with data that this processor transmitted via this data bus write in this cache data memory with this data address in the corresponding storage of cache line address address in, or the data that will store in the address to be deposited reach this processor via this data bus, when if the interval address in this data address conforms to this second interval address with this first interval mail returned on ground of incorrect address, this director cache can start exchange (swap) program with in this cache data memory with this data address in the corresponding storage of cache line address address in the Data Update of being deposited in this primary memory in the stored data of this data address, when if the interval address in this data address and this first and second interval address all are not inconsistent, this director cache can make this processor directly data be deposited in this primary memory or by taking out in this primary memory, and can not start this exchange (swap) program and upgrade the data of being deposited in this cache data memory, at last this director cache the interval address in this data address can be deposited in this second speed buffering mapping memory with this data address in the corresponding storage of cache line address address in.
Purpose of the present invention, feature, advantage will be described in detail with reference to the attached drawings in conjunction with the embodiments.
Brief Description Of Drawings:
Fig. 1 is the functional-block diagram that becomes known for the cache memory system of a computer;
Fig. 2 is used for the functional-block diagram of the cache memory system of a computer for the present invention;
Fig. 3 desires to read or write the interval address of data and the graph of a relation between the exchanger for Fig. 2 processor.
See also Fig. 2, Fig. 2 is used for the functional-block diagram of the cache memory system 42 of a computer 40 for the present invention.Computer 40 includes a central processing unit 44, one first address bus 46, be electrically connected on processor 44, be used for transmitting and can read the data address 52 that respectively stores address 50 in (access) primary memory 48, and one first data bus 54, be electrically connected between processor 44 and the primary memory 48, be used for Data transmission.Data address 52 includes the cache line address (cache line address) of a low order and the interval address (block address) of a high significance bit.
Cache memory system 42 includes a cache data memory (cache datamemory) 56, one first speed buffering mapping memory, 58, one second speed buffering mapping memories 60 and a director cache 62 are used for controlling the operation of cache memory system 42.Cache data memory 56 is to be electrically connected on one second address bus 64 and one second data bus 66, and it includes the data that a plurality of storages address 68 is used for temporarily depositing in the primary memory 48 and uses for processor 44.The data that respectively store in the address 68 of cache data memory 56 can be read by the cache line address of second address bus 64.
The first speed buffering mapping memory 58 is to be electrically connected on second address bus 64, it includes a plurality of storages address 70, a plurality of storages address 70 of the first speed buffering mapping memory 58 is corresponding with a plurality of storages address 68 of cache data memory 56, is used for temporarily depositing the interval address of corresponding storage address 68 interior data of being deposited in the cache data memory 56.
The second speed buffering mapping memory 60 is to be electrically connected on second address bus 64, it includes a plurality of storages address 72, a plurality of storages address 72 of the second speed buffering mapping memory 60 is corresponding with a plurality of storages address 68 of cache data memory 56, and each that is used for temporarily depositing cache data memory 56 that second address bus 64 transmits stores the up-to-date interval address of address 68.
Director cache 62 includes one first comparator circuit, 74, one second comparator circuits 76, and a control circuit 78 is electrically connected on the output terminal of first and second comparator circuit 74,76, is used for controlling the operation of director cache 62.Whether the input end of first comparator circuit 74 is output terminal and second address buss 64 that are electrically connected on the first speed buffering mapping memory 58, be used for the interval address of the data address 52 that comparison transmitted by second address bus 64 to conform to the first interval address of the first speed buffering mapping memory, 58 outputs.The input end of second comparator circuit 76 is output terminal and the address buss 64 that are electrically connected on the second speed buffering mapping memory 60, and whether the interval address that is used in the data address 52 that comparison transmitted by address bus 64 conforms to the second interval address of the second speed buffering mapping memory, 60 outputs.
When processor 44 desires are read data or are write cache memory system 42, processor 44 can reach cache memory system 42 via second address bus 64 with the data address 52 of these data in primary memory 48, cache line address in the data address 52 can make first and second speed buffering mapping memory 58, corresponding storage address 70 in 60, the first interval address and the second interval address of being deposited in 72 export director cache 62 to, and director cache 62 then can compare the interval address in the data address 52 respectively with first and second interval address.
When if the interval address in first comparator circuit, the 74 video data addresses 52 conforms to the first interval address, control circuit 78 can be transmitted processor 44 via second data bus 66 data write in the cache data memory 56 with data address 52 in the corresponding storage of cache line address address 68 in, or will store address 68 interior data of being deposited reaches processor 44 via second data bus 66.When if the interval address in second comparator circuit, the 76 video data addresses 52 conforms to the second interval address the interval address in first comparator circuit, the 74 video data addresses 52 with the first interval mail returned on ground of incorrect address, control circuit 78 can start one exchange (swap) program with in the cache data memory 56 with data address 52 in the corresponding storage of cache line address address 68 interior Data Update of being deposited be in data address 52 stored data in the primary memory 48.When if the interval address in first and second comparator circuit 74,76 video data addresses 52 and first and second interval address all are not inconsistent, control circuit 78 can make processor 44 directly data be deposited in primary memory 48 or by taking out in the primary memory 48, and can not start this exchange (swap) program and upgrade the data of being deposited in the cache data memory 56, last control circuit 78 the interval address in the data address 52 can be deposited in the second speed buffering mapping memory 60 with data address 52 in the corresponding storage of cache line address address 72 in.
See also Fig. 3, Fig. 3 desires to read or write the interval address of data and the graph of a relation between this exchanger for processor 44.As shown in Figure 3, when processor 44 desired to read or write the interval address modification of data of cache memory system 42, the second interval addresses in the second speed buffering mapping memory 60 in the corresponding storage address 72 can be substituted.When the identical interval address of secondary appears in data continuously that desire to read or write cache memory system 42 when processor 44, the first interval addresses in the first speed buffering mapping memory 58 in the corresponding storage address 70 just can be substituted, and control circuit 78 just can start this exchanger and upgraded the data of being deposited in the cache data memory 56 this moment.
Compared to known cache system 12, cache memory system 42 of the present invention includes two speed buffering mapping memories 58,60, when the identical interval address of secondary appearred in data continuously that desire to read or write cache memory system 42 when processor 44, control circuit 78 just can start this exchanger and upgrade the data of being deposited in the cache data memory 56.Therefore if when processor 44 read a certain data of seldom using, control circuit 78 can not start this exchanger immediately and upgrade the data of being deposited in the cache data memory 56, unless these data are read secondary continuously.Such design can promote the rate of hitting (hit rate) of cache memory system 42 greatly, and reduces punishment rate (penalty), and then saves the time of computer 40 computings.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (2)
1. cache memory system that is used for a computer, this computer package contains a central processing unit, one address bus, be electrically connected on this processor, be used for transmitting and can read the data address that respectively stores the address in the primary memory, and a data bus, be electrically connected on this processor, be used for Data transmission, this data address includes the interval address of the cache line address and a high significance bit of a low order, it is characterized in that this cache memory system includes:
One cache data memory, be electrically connected on this address bus and data bus, it includes the data that a plurality of storages address is used for temporarily depositing in this primary memory and uses for this processor, and wherein the data that respectively store in the address of this cache data memory can be read by the cache line address of this address bus;
One first speed buffering mapping memory, be electrically connected on this address bus, it includes a plurality of storages address, a plurality of storages address of this first speed buffering mapping memory is corresponding with a plurality of storages address of this cache data memory, is used for temporarily depositing the interval address of the data of being deposited in the corresponding storage address in this cache data memory;
One second speed buffering mapping memory, be electrically connected on this address bus, it includes a plurality of storages address, a plurality of storages address of this second speed buffering mapping memory is corresponding with a plurality of storages address of this cache data memory, and each that is used for temporarily depositing this cache data memory that this address bus transmits stores the up-to-date interval address of address; And
One director cache is used for controlling the operation of this cache memory system; It comprises:
One first comparator circuit, its input end is output terminal and this address bus that is electrically connected on this first speed buffering mapping memory, and whether the interval address that is used in this data address that comparison transmitted by this address bus conforms to the first interval address of this first speed buffering mapping memory output;
One second comparator circuit, its input end is output terminal and this address bus that is electrically connected on this second speed buffering mapping memory, and whether the interval address that is used in this data address that comparison transmitted by this address bus conforms to the second interval address of this second speed buffering mapping memory output; And
One control circuit is electrically connected on the output terminal of this first and second comparator circuit, is used for controlling the operation of this director cache;
Wherein when this cache memory system is read or write to this processor desire with data, this processor can reach this cache memory system via this address bus with the data address of these data in this primary memory, cache line address in this data address can make the one first interval address and the one second interval address of being deposited in the corresponding storage address in this first and second speed buffering mapping memory export this director cache to, this director cache then can compare the interval address in this data address respectively with this first and second interval address, if this first comparator circuit shows when the interval address in this data address conforms to this first interval address, this control circuit can with this processor via the data that this data bus transmitted write in this cache data memory with this data address in the corresponding storage of cache line address address in, or the data that will store in the address to be deposited reach this processor via this data bus, if this first comparator circuit shows that this second comparator circuit shows when interval address in this data address conforms to this second interval address with this first interval mail returned on ground of incorrect address for interval address in this data address, this control circuit can start this exchanger with in this cache data memory with this data address in the corresponding storage of cache line address address in the Data Update of being deposited in this primary memory in the stored data of this data address, if this first and second comparator circuit shows when interval address in this data address and this first and second interval address all are not inconsistent, this control circuit can make this processor directly data be deposited in this primary memory or by taking out in this primary memory, and can not start this exchanger and upgrade the data of being deposited in this cache data memory, at last this control circuit the interval address in this data address can be deposited in this second speed buffering mapping memory with this data address in the corresponding storage of cache line address address in.
2. cache memory system as claimed in claim 1, it is characterized in that data bus and address bus between this processor and this cache memory system are second data bus and second address bus, and be provided with one first data bus and one first address bus between this processor and this primary memory in addition, be used for Data transmission and data address.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB991270541A CN1173271C (en) | 1999-12-24 | 1999-12-24 | High speed buffer storage system with double high speed buffer mapping storage |
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| CNB991270541A CN1173271C (en) | 1999-12-24 | 1999-12-24 | High speed buffer storage system with double high speed buffer mapping storage |
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| CN1173271C true CN1173271C (en) | 2004-10-27 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7174429B2 (en) * | 2001-12-28 | 2007-02-06 | Intel Corporation | Method for extending the local memory address space of a processor |
| US7085889B2 (en) * | 2002-03-22 | 2006-08-01 | Intel Corporation | Use of a context identifier in a cache memory |
| US7447953B2 (en) * | 2003-11-14 | 2008-11-04 | Intel Corporation | Lane testing with variable mapping |
| CN100447858C (en) * | 2005-10-25 | 2008-12-31 | 广达电脑股份有限公司 | Display controller capable of reducing using high speed buffer store and its frame regulating method |
| US7937534B2 (en) * | 2005-12-30 | 2011-05-03 | Rajesh Sankaran Madukkarumukumana | Performing direct cache access transactions based on a memory access data structure |
| CN100464290C (en) * | 2007-09-10 | 2009-02-25 | 杭州华三通信技术有限公司 | Caching management system |
| CN101446926B (en) | 2008-11-10 | 2011-06-01 | 成都市华为赛门铁克科技有限公司 | Method for storing power-fail data of cache memory, equipment and system thereof |
| KR20170075396A (en) * | 2015-12-23 | 2017-07-03 | 고려대학교 산학협력단 | Memory system |
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