CN117320330B - Manufacturing method of inner layer of multilayer PCB - Google Patents
Manufacturing method of inner layer of multilayer PCB Download PDFInfo
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- CN117320330B CN117320330B CN202311396197.0A CN202311396197A CN117320330B CN 117320330 B CN117320330 B CN 117320330B CN 202311396197 A CN202311396197 A CN 202311396197A CN 117320330 B CN117320330 B CN 117320330B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000008602 contraction Effects 0.000 claims abstract description 35
- 238000005553 drilling Methods 0.000 claims abstract description 18
- 238000003475 lamination Methods 0.000 claims abstract description 18
- 238000012545 processing Methods 0.000 claims abstract description 8
- 230000008961 swelling Effects 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 8
- 238000011161 development Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 3
- 150000003071 polychlorinated biphenyls Chemical class 0.000 abstract description 3
- 238000005259 measurement Methods 0.000 description 12
- 238000010030 laminating Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to the technical field of multilayer PCBs and discloses a manufacturing method of an inner layer of the multilayer PCBs, wherein an alignment ring and a swelling and shrinking bonding pad are arranged on a circuit pattern layer, when in lamination processing, X-ray is used for detecting concentricity of the alignment ring, if the detected concentricity exceeds an error range, the position of an inner core board is adjusted, and lamination processing is carried out until the detected concentricity is within the error range, so that the layer deflection of the inner core board is reduced; after the lamination treatment, the X-ray is used for detecting and calculating the expansion coefficient of the expansion and contraction bonding pad, and an average expansion and contraction system is obtained, and during the drilling treatment, the drilling position is corrected according to the average expansion and contraction coefficient, so that the occurrence of the condition that the inner layer circuit is short-circuited due to layer deflection generated by expansion and contraction of the circuit pattern layer is effectively reduced, the quality of the inner layer of the multilayer PCB is ensured, and the reject ratio of products is reduced.
Description
Technical Field
The invention relates to the technical field of multilayer PCB (printed Circuit Board), in particular to a manufacturing method of an inner layer of a multilayer PCB.
Background
With the continuous development of the electronic industry, there is an increasing demand for high-voltage and high-current printed circuit boards (PCBs, printed Circuit Board) in the fields of industrial equipment, electronic communications and the like. The multilayer PCB board is more than two layers of printed boards, and consists of connecting wires on several layers of insulating substrates and bonding pads for assembling and welding electronic elements, and has the functions of conducting each layer of circuits and insulating each other. When the multilayer PCB is manufactured, the inner layers of the multilayer PCB are manufactured firstly, the inner layers of the multilayer PCB are laminated when being manufactured, and as errors exist in positioning of the inner layer core plates during lamination and the inner layer core plates expand and contract during lamination, the circuit pattern layers on the inner layer core plates after lamination can generate layer deflection, the problem of inner circuit short circuit and the like, so that the manufacturing quality of the multilayer PCB is affected, generally, the larger the size of the inner layer core plates is, the larger the layer deflection is, the higher the reject ratio is, the size of the inner layer core plates is limited, and generally, the size of the inner layer core plates is not more than 24 inches by 28.5 inches.
Disclosure of Invention
The invention aims to provide a manufacturing method of an inner layer of a multi-layer PCB, which can effectively reduce the influence of layer bias on the quality of the multi-layer PCB, thereby ensuring that the multi-layer PCB has good qualification rate.
In order to solve the technical problems, the invention provides a manufacturing method of an inner layer of a multilayer PCB, which comprises the following steps:
s1: manufacturing a plurality of inner core plates, wherein the top surface and the bottom surface of each inner core plate form a circuit pattern layer, an alignment ring and a swelling and shrinking pad are arranged on each circuit pattern layer, the positions of the circle centers of the alignment rings on each circuit pattern layer correspond, the alignment rings are arranged at intervals, and the swelling and shrinking pads on each circuit pattern layer are arranged in a staggered mode;
s2: during lamination processing, stacking and fixing a plurality of inner core plates, firstly using X-ray detection to judge concentricity of a plurality of alignment rings, if the detected concentricity exceeds an error range, adjusting the position of the inner core plates, and if the detected concentricity is within the error range, performing lamination processing to obtain a multi-layer plate;
s3: using X-ray to detect the area of the expansion and contraction bonding pads after the pressing treatment, calculating to obtain expansion and contraction coefficients of the circuit pattern layer corresponding to each expansion and contraction bonding pad, and calculating to obtain an average expansion and contraction coefficient;
s4: drilling after cutting and grinding the multilayer board, and correcting the drilling position according to the average expansion coefficient obtained in the step S4;
s5: and carrying out copper deposition and electroplating treatment on the drilled multilayer board to finish the manufacturing of the inner layer of the multilayer PCB.
In S1, a plurality of deviation measuring pads are arranged on the first layer of the circuit pattern layer, deviation measuring rings corresponding to the deviation measuring pads one by one are respectively arranged on the rest layers of the circuit pattern layer, and the circle center positions of the deviation measuring pads correspond to the circle center positions of the deviation measuring rings.
In a preferred embodiment of the present invention, in S1, a dummy copper sheet is laid on the copper-free region of the circuit pattern layer. False copper, but avoids the original elements such as wires, bonding pads, drilling holes and the like
In the preferred scheme of the invention, in S1, the inner core plate is prepared by sequentially carrying out material cutting, baking, film pasting, exposure, development, etching, touch removal and automatic optical detection treatment on the plate.
As a preferred embodiment of the present invention, the baking temperature is 10℃higher than the Tg point of the sheet.
Compared with the prior art, the manufacturing method of the inner layer of the multilayer PCB has the beneficial effects that: according to the invention, the alignment ring and the expansion and contraction bonding pad are arranged on the circuit pattern layer, during lamination, the concentricity of the alignment ring is detected by using the X-ray, if the detected concentricity exceeds an error range, the position of the inner core plate is adjusted, and lamination is carried out until the detected concentricity is within the error range, so that the layer deflection of the inner core plate is reduced; after the lamination treatment, the X-ray is used for detecting and calculating the expansion coefficient of the expansion and contraction bonding pad, and an average expansion and contraction system is obtained, and during the drilling treatment, the drilling position is corrected according to the average expansion and contraction coefficient, so that the occurrence of the condition that the inner layer circuit is short-circuited due to layer deflection generated by expansion and contraction of the circuit pattern layer is effectively reduced, the quality of the inner layer of the multilayer PCB is ensured, and the reject ratio of products is reduced.
Drawings
FIG. 1 is a schematic illustration of the position of an alignment ring according to the present invention;
FIG. 2 is a schematic illustration of the location of a collapsible pad of the present invention;
FIG. 3 is a schematic illustration of the position of the bias measurement pad and the bias measurement ring of the present invention;
in the figure, 1, an alignment ring; 2. a collapsible pad; 3. a deflection measuring bonding pad; 4. and measuring the deflection ring.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
In the description of the present invention, it should be understood that the terms "center," "longitudinal," "transverse," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the present invention as indicated by the orientation or positional relationship shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
As shown in fig. 1-3, a method for manufacturing an inner layer of a multi-layer PCB board according to a preferred embodiment of the present invention includes the following steps:
s1: the manufacturing method of the inner core plates is a mature technology, and the manufacturing steps of the inner core plates generally comprise the steps of sequentially carrying out cutting, baking, film pasting, exposure, development, etching, film removing and automatic optical detection (AIO) on the plates to obtain the inner core plates, wherein the cutting is the cutting of the whole plate into the required size; the cut sheet is then baked at 10℃in accordance with the Tg point temperature of the sheet (Tg point is the highest temperature at which the substrate retains rigidity), as follows: taking a high-frequency material with TG of 170 ℃ as a substrate, and baking for 4 hours in a baking chamber with the temperature of 180 ℃; cooling the baked board to normal temperature, pre-treating and laminating the inner layer, transferring the circuit pattern to a dry film layer on the board surface by using an LD I exposure machine, and then manufacturing the required circuit pattern by DES development/etching/stripping to form a circuit pattern layer; and then, using an AO I automatic optical detection device to automatically scan and detect, comparing with a CAM computer aided manufacturing design manuscript, detecting the difference between a plate surface pattern and the manuscript, manually judging defects by a line VRS, and processing the repairable defects normally, thereby preparing a plurality of inner core plates.
The top surface and the bottom surface of inlayer core form circuit figure layer respectively, wherein, be equipped with counterpoint ring 1 and swell-shrink pad 2 on the circuit figure layer, the position of the centre of a circle of counterpoint ring 1 on each circuit figure layer corresponds, and each counterpoint ring 1 interval sets up, the swell-shrink pad 2 dislocation set on each circuit figure layer, namely under ideal circumstances, when each circuit figure layer from top to bottom stacks gradually, each counterpoint ring 1 coaxial setting and mutual interval sets up, each swell-shrink pad 2 each do not intersect each other.
S2: when laminating, laminating and fixing a plurality of inner core plates, wherein the laminating is the prior art, the specific operation steps are not described in detail, it can be understood that when laminating, not only the inner core plates are laminated in sequence, but also PP materials, copper foils and the like, after laminating is completed, the concentricity of a plurality of alignment rings is judged by using X-ray detection, if the detected concentricity exceeds an error range, the positions of the inner core plates are adjusted, after laminating is completed, in an ideal state, each alignment ring is concentric, but the laminating of each inner core plate has errors, so that the concentricity of each inner core plate can be detected by X-ray detection, if the errors exceed a specified range, the positions of the inner core plates are adjusted, then the lamination is carried out again, if the detected concentricity is within the error range, and the plate is obtained, so that the layer deflection of the inner core plates is reduced.
S3: the X-ray is used for detecting the area of the expansion and contraction bonding pad after the pressing treatment, the area of the expansion and contraction bonding pad also changes due to expansion and contraction because of the expansion and contraction of the circuit pattern layer after the pressing treatment, the area of the expansion and contraction bonding pad after the pressing treatment is detected and divided by the area of the expansion and contraction bonding pad before the pressing treatment (which can be known in design) to obtain the expansion and contraction coefficient of the circuit pattern layer corresponding to each expansion and contraction bonding pad, namely the expansion and contraction coefficient is the ratio of the area of the expansion and contraction bonding pad after the pressing treatment and the area of the expansion and contraction bonding pad before the pressing treatment, so that the expansion and contraction coefficient of the circuit pattern layer of each layer is obtained, the average value is calculated, and the average expansion and contraction coefficient is calculated.
S4: and (3) carrying out drilling treatment after cutting and grinding the multilayer board, at this time, correcting the position of the drilling according to the average expansion coefficient obtained in the step (S4), generally, carrying out milling target treatment on the multilayer board before drilling to determine a reference point of the drilling, and correcting the position of the drilling according to the average expansion coefficient, wherein if the design distance between the center of the through hole and the reference point is 500mm, and the average expansion coefficient is 1.02, the design distance of the through hole is multiplied by the average expansion coefficient, namely 500 x 1.02, so as to obtain an actual processing position of 510mm, and the actual drilling position is corrected according to the average expansion coefficient, thereby effectively reducing the occurrence of the condition that the inner layer circuit is short-circuited due to layer deviation caused by expansion of a circuit pattern layer, ensuring the quality of the inner layer of the multilayer PCB, and reducing the reject ratio of products.
S5: carrying out copper deposition and electroplating treatment on the drilled multilayer board to finish the manufacturing of the inner layer of the multilayer PCB; and (3) carrying out copper deposition on the drilled multilayer board, immersing copper plating liquid medicine, plating a layer of metal copper in the holes, electroplating the board in the previous procedure in a VCP vertical electroplating line, plating a layer of copper on the board surface to finish the manufacture of the inner layer of the multilayer PCB, and then completing the manufacture of the PCB according to the conventional manufacture.
According to the invention, the alignment ring and the expansion and contraction bonding pad are arranged on the circuit pattern layer, during lamination, the concentricity of the alignment ring is detected by using the X-ray, if the detected concentricity exceeds an error range, the position of the inner core plate is adjusted, and lamination is carried out until the detected concentricity is within the error range, so that the layer deflection of the inner core plate is reduced; after the lamination treatment, the X-ray is used for detecting and calculating the expansion coefficient of the expansion and contraction bonding pad, and an average expansion and contraction system is obtained, when the drilling treatment is carried out, the drilling position is corrected according to the average expansion and contraction coefficient, so that the occurrence of the condition that the inner layer circuit is short-circuited due to layer deflection generated by expansion and contraction of the circuit pattern layer is effectively reduced, the quality of the inner layer of the multi-layer PCB is ensured, the reject ratio of products is reduced, compared with the prior art, an inner layer core board with larger size can be used, and the size of the inner layer core board can reach 24 inches by 43 inches by using the method through testing.
In S1, a plurality of bias measurement pads 3 are disposed on a first circuit pattern layer, generally, a plurality of bias measurement pads are disposed at four corners of the first circuit pattern layer, it is to be noted that, instead of representing that the first circuit pattern layer is located at a top layer when laminating, a PP board is further disposed above the first circuit pattern layer, copper foils are further disposed on the PP board, bias measurement rings 4 corresponding to the bias measurement pads 3 one by one are disposed on the remaining circuit pattern layers, and the center positions of the bias measurement pads 3 correspond to the center positions of the bias measurement rings 4, and in an ideal state, when laminating, each bias measurement ring 4 and its corresponding bias measurement pad 3 are coaxially disposed, after laminating, the layer bias of the corresponding circuit pattern layer can be detected by using X-ray to detect the relative bias of the bias measurement ring 4 and its corresponding bias measurement pad 3, so as to determine whether the product meets the requirement.
Illustratively, in S1, a dummy copper sheet is laid on the copper-free region of the wiring pattern layer. The dummy copper is avoided from the original elements such as wires, bonding pads, drilling holes and the like, and because of the design specificity of the large-size plate, most of the inner core plates are designed to be a circuit layer while being provided with large copper sheets, so that the residual copper rate of the inner core plates is greatly different from that of the Zhang Naceng core plates, and in order to help the glue filling uniformity and the plate thickness balance during lamination, the dummy copper is added or added in a copper-free area.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and these modifications and substitutions should also be considered as being within the scope of the present invention.
Claims (5)
1. The manufacturing method of the inner layer of the multilayer PCB board is characterized by comprising the following steps of: the method comprises the following steps:
s1: manufacturing a plurality of inner core plates, wherein the top surface and the bottom surface of each inner core plate form a circuit pattern layer, an alignment ring and a swelling and shrinking pad are arranged on each circuit pattern layer, the positions of the circle centers of the alignment rings on each circuit pattern layer correspond, the alignment rings are arranged at intervals, and the swelling and shrinking pads on each circuit pattern layer are arranged in a staggered mode;
s2: during lamination processing, stacking and fixing a plurality of inner core plates, firstly using X-ray detection to judge concentricity of a plurality of alignment rings, if the detected concentricity exceeds an error range, adjusting the position of the inner core plates, and if the detected concentricity is within the error range, performing lamination processing to obtain a multi-layer plate;
s3: using X-ray to detect the area of the expansion and contraction bonding pads after the pressing treatment, calculating to obtain expansion and contraction coefficients of the circuit pattern layer corresponding to each expansion and contraction bonding pad, and calculating to obtain an average expansion and contraction coefficient;
s4: drilling after cutting and grinding the multilayer board, and correcting the drilling position according to the average expansion coefficient obtained in the step S4;
s5: and carrying out copper deposition and electroplating treatment on the drilled multilayer board to finish the manufacturing of the inner layer of the multilayer PCB.
2. The method for manufacturing the inner layer of the multilayer PCB according to claim 1, wherein the method comprises the following steps: in S1, a plurality of deviation measuring bonding pads are arranged on a first layer of the circuit pattern layer, deviation measuring circular rings which are in one-to-one correspondence with the deviation measuring bonding pads are respectively arranged on the rest layers of the circuit pattern layer, and the circle center positions of the deviation measuring bonding pads correspond to the circle center positions of the deviation measuring circular rings.
3. The method for manufacturing the inner layer of the multilayer PCB according to claim 1, wherein the method comprises the following steps: in S1, a dummy copper sheet is laid on the copper-free area of the circuit pattern layer.
4. The method for manufacturing the inner layer of the multilayer PCB according to claim 1, wherein the method comprises the following steps: in S1, the inner core plate is manufactured by sequentially carrying out material cutting, baking, film pasting, exposure, development, etching, touch removal and automatic optical detection treatment on the plate.
5. The method for manufacturing the inner layer of the multilayer PCB according to claim 4, wherein: the baking temperature is 10 ℃ higher than the Tg point of the plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311396197.0A CN117320330B (en) | 2023-10-25 | 2023-10-25 | Manufacturing method of inner layer of multilayer PCB |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311396197.0A CN117320330B (en) | 2023-10-25 | 2023-10-25 | Manufacturing method of inner layer of multilayer PCB |
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| Publication Number | Publication Date |
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| CN117320330A CN117320330A (en) | 2023-12-29 |
| CN117320330B true CN117320330B (en) | 2024-04-02 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105376963A (en) * | 2015-11-04 | 2016-03-02 | 江门崇达电路技术有限公司 | Method for grabbing internal layer compensation coefficients |
| CN109600941A (en) * | 2019-01-28 | 2019-04-09 | 鹤山市世安电子科技有限公司 | A kind of PCB multilayer circuit board interlayer change in size measurement method |
| CN109788669A (en) * | 2019-03-04 | 2019-05-21 | 深圳市泰科思特精密工业有限公司 | It is a kind of improve pressing after the inclined phenomenon of layer pcb board processing method |
| CN110536569A (en) * | 2019-09-29 | 2019-12-03 | 胜宏科技（惠州）股份有限公司 | It is a kind of to avoid the pcb board processing method that layer is inclined after pressing |
| CN111885834A (en) * | 2020-08-03 | 2020-11-03 | 胜宏科技（惠州）股份有限公司 | Manufacturing method of 5G high-frequency board with interlayer accurate alignment |
-
2023
- 2023-10-25 CN CN202311396197.0A patent/CN117320330B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105376963A (en) * | 2015-11-04 | 2016-03-02 | 江门崇达电路技术有限公司 | Method for grabbing internal layer compensation coefficients |
| CN109600941A (en) * | 2019-01-28 | 2019-04-09 | 鹤山市世安电子科技有限公司 | A kind of PCB multilayer circuit board interlayer change in size measurement method |
| CN109788669A (en) * | 2019-03-04 | 2019-05-21 | 深圳市泰科思特精密工业有限公司 | It is a kind of improve pressing after the inclined phenomenon of layer pcb board processing method |
| CN110536569A (en) * | 2019-09-29 | 2019-12-03 | 胜宏科技（惠州）股份有限公司 | It is a kind of to avoid the pcb board processing method that layer is inclined after pressing |
| CN111885834A (en) * | 2020-08-03 | 2020-11-03 | 胜宏科技（惠州）股份有限公司 | Manufacturing method of 5G high-frequency board with interlayer accurate alignment |
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| Publication number | Publication date |
|---|---|
| CN117320330A (en) | 2023-12-29 |
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