CN117319823A - Latching ADC, analog-to-digital conversion method, image sensor, and storage medium - Google Patents

Latching ADC, analog-to-digital conversion method, image sensor, and storage medium Download PDF

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Publication number
CN117319823A
CN117319823A CN202311600223.7A CN202311600223A CN117319823A CN 117319823 A CN117319823 A CN 117319823A CN 202311600223 A CN202311600223 A CN 202311600223A CN 117319823 A CN117319823 A CN 117319823A
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nand gate
input end
latch
output end
output
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CN117319823B (en
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戴伟
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Ruijing Microelectronics Zhuhai Co ltd
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Ruijing Microelectronics Zhuhai Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The invention discloses a latching ADC, an analog-to-digital conversion method, an image sensor and a storage medium, and relates to the technical field of analog-to-digital conversion. A latching ADC for an image sensor includes a reference voltage generating circuit, a comparator, a count comparator, and a latch; the first input end of the comparator is connected with the pixel output voltage, and the second input end of the comparator is connected with the slope voltage; the first input end of the counting comparator is connected with the output end of the comparator; the first input end of the latch is connected with the output end of the comparator, the second input end of the latch is electrically connected with the output end of the counting comparator, and the output end of the latch is respectively connected with the input end of the reference voltage generating circuit and the second input end of the counting comparator. According to the latch ADC for the image sensor, disclosed by the embodiment of the invention, the analog-to-digital conversion efficiency can be improved, and the power consumption can be reduced.

Description

Latching ADC, analog-to-digital conversion method, image sensor, and storage medium
Technical Field
The invention relates to the technical field of analog-to-digital conversion, in particular to a latching ADC, an analog-to-digital conversion method, an image sensor and a storage medium.
Background
The image sensor generally has an ADC (analog-to-digital converter) provided for each column thereof for converting an analog signal (i.e., a pixel output voltage) output by a unit pixel into a digital signal. In the analog-to-digital conversion process, the analog-to-digital converter converts the analog signal into a digital signal according to the count value by comparing the pixel output voltage with the ramp voltage and counting the count pulses until the ramp voltage is equal to the pixel output voltage. Because each pixel is compared with the same ramp voltage, the power consumption of the whole process is higher, and the analog-to-digital conversion speed is slower.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides a latching ADC, an analog-to-digital conversion method, an image sensor and a storage medium, which can dynamically adjust the ramp voltage, improve the analog-to-digital conversion efficiency and reduce the power consumption.
In one aspect, a latching ADC for an image sensor according to an embodiment of the invention includes:
a reference voltage generation circuit for generating a ramp voltage;
the first input end of the comparator is connected with the pixel output voltage, the second input end of the comparator is connected with the slope voltage, and the comparator is used for comparing the pixel output voltage with the slope voltage and outputting a reset signal when the comparison result is overturned;
The first input end of the counting comparator is connected with the output end of the comparator; the counting comparator is used for counting up or down the counting pulse, stopping counting after receiving the reset signal to obtain a counting result, converting the pixel output voltage into a corresponding digital signal according to the counting result, and generating a latch signal;
the first input end of the latch is connected with the output end of the comparator, the second input end of the latch is connected with the output end of the counting comparator, and the output end of the latch is respectively connected with the input end of the reference voltage generating circuit and the second input end of the counting comparator; the latch is used for latching the latch signal according to the reset signal to obtain a latch result, and sending the latch result to the reference voltage generating circuit and the count comparator; the reference voltage generating circuit is used for updating the slope voltage according to the latching result, and the counting comparator is used for counting up or down according to the latching result.
According to some embodiments of the invention, the latch comprises a first nand gate, a second nand gate, a third nand gate, and a fourth nand gate;
the first input end of the first NAND gate is connected with the reset signal, and the second input end of the first NAND gate is connected with the output end of the second NAND gate;
the first input end of the second NAND gate is connected with the reset signal, and the second input end of the second NAND gate is connected with the latch signal;
the first input end of the third NAND gate is electrically connected with the output end of the first NAND gate, and the second input end of the third NAND gate is electrically connected with the output end of the fourth NAND gate;
the first input end of the fourth NAND gate is electrically connected with the output end of the third NAND gate, the second input end of the fourth NAND gate is electrically connected with the output end of the second NAND gate, and the output end of the fourth NAND gate is used for outputting the latching result and sending the latching result to the reference voltage generating circuit and the counting comparator.
According to some embodiments of the invention, the counting comparator comprises an inverter and a plurality of flip-flops, and every two adjacent flip-flops are connected through a logic gate assembly;
The clock input end of the first trigger is connected with the counting pulse, and the signal input end of each trigger is connected with the reset signal;
the input end of the inverter is connected with the latch result;
the first input end of the logic gate component is connected with the latching result, the second input end of the logic gate component is connected with the output end of the previous trigger between two adjacent triggers, the third input end of the logic gate component is connected with the inverting output end of the previous trigger, the fourth input end of the logic gate component is connected with the output end of the inverter, and the output end of the logic gate component is connected with the clock input end of the next trigger between two adjacent triggers;
the logic gate component is used for generating a trigger signal according to the latching result, the output signals of the output end and the reverse phase output end of the previous trigger and the output signal of the output end of the reverse phase device, and sending the trigger signal to the clock input end of the next trigger; when the latching result is high level, the signal output by the logic gate component is the signal output by the output end of the previous trigger, and the counting comparator counts upwards; when the latch result is low level, the signal output by the logic gate component is the signal output by the inverting output end of the previous trigger, and the count comparator counts down.
According to some embodiments of the invention, the logic gate assembly includes a fifth nand gate, a sixth nand gate, and a seventh nand gate; the first input end of the fifth NAND gate is connected with the latching result, and the second input end of the fifth NAND gate is electrically connected with the output end of the previous trigger; the first input end of the sixth NAND gate is electrically connected with the inverting output end of the previous trigger, and the second input end of the sixth NAND gate is electrically connected with the output end of the inverter; the first input end of the seventh NAND gate is electrically connected with the output end of the fifth NAND gate, the second input end of the seventh NAND gate is electrically connected with the output end of the sixth NAND gate, and the output end of the seventh NAND gate is connected with the clock input end of the next trigger.
On the other hand, according to the analog-to-digital conversion method of the latch ADC for an image sensor according to an embodiment of the invention, based on the latch ADC for an image sensor described above, the analog-to-digital conversion method includes:
the reference voltage generating circuit generates a ramp voltage;
the comparator compares the slope voltage with the pixel output voltage and outputs a reset signal when the comparison result is overturned;
The counting comparator counts up or down the counting pulse, stops counting after receiving the reset signal to obtain a counting result, converts the pixel output voltage into a corresponding digital signal according to the counting result, and generates a latch signal;
the latch latches the latch signal according to the reset signal to obtain a latch result, and sends the latch result to the reference voltage generating circuit and the count comparator;
the reference voltage generating circuit updates the slope voltage according to the latching result, and the counting comparator judges to count up or count down according to the latching result; and returning to the step of comparing the slope voltage with the pixel output voltage by the comparator and outputting a reset signal when the comparison result is overturned, and converting the pixel output voltage of the next frame into a corresponding digital signal until the analog-to-digital conversion of all the pixel output voltages is completed.
According to some embodiments of the invention, the latch comprises a first nand gate, a second nand gate, a third nand gate, and a fourth nand gate; the first input end of the first NAND gate is connected with the reset signal, and the second input end of the first NAND gate is connected with the output end of the second NAND gate; the first input end of the second NAND gate is connected with the reset signal, and the second input end of the second NAND gate is connected with the latch signal; the first input end of the third NAND gate is electrically connected with the output end of the first NAND gate, and the second input end of the third NAND gate is electrically connected with the output end of the fourth NAND gate; the first input end of the fourth NAND gate is electrically connected with the output end of the third NAND gate, the second input end of the fourth NAND gate is electrically connected with the output end of the second NAND gate, and the output end of the fourth NAND gate is used for outputting the latching result and sending the latching result to the reference voltage generating circuit and the counting comparator.
According to some embodiments of the invention, the counting comparator comprises an inverter and a plurality of flip-flops, and every two adjacent flip-flops are connected through a logic gate assembly; the clock input end of the first trigger is connected with the counting pulse, and the signal input end of each trigger is connected with the reset signal; the input end of the inverter is connected with the latch result; the first input end of the logic gate component is connected with the latching result, the second input end of the logic gate component is connected with the output end of the previous trigger between two adjacent triggers, the third input end of the logic gate component is connected with the inverting output end of the previous trigger, the fourth input end of the logic gate component is connected with the output end of the inverter, and the output end of the logic gate component is connected with the clock input end of the next trigger between two adjacent triggers; the logic gate component is used for generating a trigger signal according to the latching result, the output signals of the output end and the reverse phase output end of the previous trigger and the output signal of the output end of the reverse phase device, and sending the trigger signal to the clock input end of the next trigger; when the latching result is high level, the signal output by the logic gate component is the signal output by the output end of the previous trigger, and the counting comparator counts upwards; when the latch result is low level, the signal output by the logic gate component is the signal output by the inverting output end of the previous trigger, and the count comparator counts down.
According to some embodiments of the invention, the logic gate assembly includes a fifth nand gate, a sixth nand gate, and a seventh nand gate; the first input end of the fifth NAND gate is connected with the latching result, and the second input end of the fifth NAND gate is electrically connected with the output end of the previous trigger; the first input end of the sixth NAND gate is electrically connected with the inverting output end of the previous trigger, and the second input end of the sixth NAND gate is electrically connected with the output end of the inverter; the first input end of the seventh NAND gate is electrically connected with the output end of the fifth NAND gate, the second input end of the seventh NAND gate is electrically connected with the output end of the sixth NAND gate, and the output end of the seventh NAND gate is connected with the clock input end of the next trigger.
On the other hand, the image sensor according to the embodiment of the invention comprises the latch ADC for the image sensor.
On the other hand, according to the storage medium of the embodiment of the present invention, the storage medium stores computer-executable instructions for causing a computer to execute the above-described analog-to-digital conversion method for the latch ADC of the image sensor.
The latch ADC, the analog-to-digital conversion method, the image sensor and the storage medium have at least the following beneficial effects: generating a ramp voltage by a reference voltage generating circuit, comparing the ramp voltage with a pixel output voltage by a comparator, and outputting a reset signal when the comparison result is overturned; meanwhile, the counting comparator counts the counting pulse, stops counting after receiving the reset signal to obtain a counting result, and generates a digital signal and a latch signal according to the counting result; the digital signal is an analog-to-digital conversion result of the pixel output voltage, and the latch signal is used as a control signal of the analog-to-digital conversion process of the pixel output voltage of the next frame. The counting comparator sends a latch signal to the latch, so that the latch can latch the counting result of the pixel output voltage of the frame, and sends the latch result to the reference voltage generating circuit, so that the reference voltage generating circuit updates the generated slope voltage by referring to the conversion result of the pixel output voltage of the previous frame, the generated slope voltage is enabled to be closer to the pixel output voltage of the next frame, the comparison result of the comparator can be overturned faster when the pixel output voltage of the next frame is compared with the slope voltage, the counting comparator can finish counting as soon as possible, the analog-to-digital conversion efficiency is improved, and the power consumption of the image sensor is greatly reduced.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a latch ADC for an image sensor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a latch according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a counter comparator according to an embodiment of the present invention;
FIG. 4 is a flow chart of the steps of a method for analog-to-digital conversion of a latch ADC for an image sensor according to an embodiment of the present invention;
reference numerals:
the reference voltage generating circuit 100, the comparator 200, the count comparator 300, the flip-flop 310, the logic gate component 320, the fifth nand gate 321, the sixth nand gate 322, the seventh nand gate 323, the latch 400, the first nand gate 410, the second nand gate 420, the third nand gate 430, and the fourth nand gate 414.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The image sensor generally has an ADC (analog-to-digital converter) provided for each column thereof for converting an analog signal (i.e., a pixel output voltage) output by a unit pixel into a digital signal. In the analog-to-digital conversion process, the analog-to-digital converter converts the analog signal into a digital signal according to the count value by comparing the pixel output voltage with the ramp voltage and counting the count pulses until the ramp voltage is equal to the pixel output voltage. Because each pixel is compared with the same ramp voltage, the power consumption of the whole process is higher, and the analog-to-digital conversion speed is slower.
Therefore, the embodiment of the invention provides a latch ADC, an analog-to-digital conversion method, an image sensor and a storage medium, wherein the ramp voltage generated by a reference voltage generating circuit can be adjusted according to the conversion result of the pixel output voltage of the previous frame, so that the ramp voltage is closer to the pixel output voltage of the next frame, a comparator can turn over faster, and the counter comparator can count more quickly, thereby improving the analog-to-digital conversion efficiency and reducing the power consumption.
The following describes in detail a latch ADC, an analog-to-digital conversion method, an image sensor, and a storage medium according to an embodiment of the invention with reference to fig. 1 to 4.
In one aspect, as shown in fig. 1, an embodiment of the present invention proposes a latch ADC for an image sensor, including a reference voltage generating circuit 100, a comparator 200, a count comparator 300, and a latch 400, the reference voltage generating circuit 100 being configured to generate a ramp voltage; a first input end of the comparator 200 is connected with a pixel output voltage (V-sig), a second input end of the comparator 200 is connected with a slope voltage (V-ref), and the comparator 200 is used for comparing the pixel output voltage with the slope voltage and outputting a reset signal (R) when the comparison result is overturned; a first input of the count comparator 300 is connected to an output of the comparator 200; the count comparator 300 is configured to count up or down the count pulse, stop counting after receiving the reset signal, obtain a count result, convert the pixel output voltage into a corresponding digital signal (D) according to the count result, and generate a latch signal (I); a first input end of the latch 400 is connected with an output end of the comparator 200, a second input end of the latch 400 is electrically connected with an output end of the counter comparator 300, and an output end of the latch 400 is respectively connected with an input end of the reference voltage generating circuit 100 and a second input end of the counter comparator 300; the latch 400 is configured to latch the latch signal (I) according to the reset signal (R) to obtain a latch result (O), and send the latch result (O) to the reference voltage generating circuit 100 and the count comparator 300; the reference voltage generating circuit 100 is used for updating the ramp voltage according to the latch result, and the count comparator 300 is used for counting up or down according to the latch result judgment.
For the image sensor, the pixel output voltages of adjacent frames are relatively close, the change is relatively small, and if the pixel output voltage of each frame is compared with the same slope voltage until the result of the comparator is overturned, the whole analog-to-digital conversion process is relatively long in time consumption, low in analog-to-digital conversion efficiency and relatively large in power consumption. While the latch ADC for an image sensor according to the embodiment of the invention, first, the ramp voltage (V-ref) is generated by the reference voltage generating circuit 100, the comparator 200 compares the ramp voltage (V-ref) with the pixel output voltage (V-sig), and at the same time, the count comparator 300 starts counting up or down the count pulse until the comparison result of the comparator 200 is inverted, generating the reset signal (R), the count comparator 300 stops counting, and generating the digital signal (D) and the latch signal (I); the digital signal is an analog-to-digital conversion result of the pixel output voltage, and the latch signal is used as a control signal of the analog-to-digital conversion process of the pixel output voltage of the next frame. The count comparator 300 sends a latch signal to the latch 400, so that the latch 400 can latch the count result of the pixel output voltage of this frame, and sends the latch result to the reference voltage generating circuit 100, so that the reference voltage generating circuit 100 updates the generated ramp voltage with reference to the conversion result of the pixel output voltage of the previous frame, so that the generated ramp voltage is closer to the pixel output voltage of the next frame, and when the comparator 200 compares the pixel output voltage of the next frame with the ramp voltage, the comparison result can be flipped faster, so that the count comparator 300 can complete counting as soon as possible, further improving the analog-digital conversion efficiency and greatly reducing the power consumption of the image sensor.
Further, as shown in fig. 2, in some embodiments of the present invention, latch 400 includes a first nand gate 410, a second nand gate 420, a third nand gate 430, and a fourth nand gate 440; a first input terminal of the first nand gate 410 is connected to the reset signal (R), and a second input terminal of the first nand gate 410 is connected to an output terminal of the second nand gate 420; a first input terminal of the second nand gate 420 is connected to the reset signal (R), and a second input terminal of the second nand gate 420 is connected to the latch signal (I); a first input of the third nand gate 430 is electrically connected to the output of the first nand gate 410, and a second input of the third nand gate 430 is electrically connected to the output of the fourth nand gate 440; the first input terminal of the fourth nand gate 440 is electrically connected to the output terminal of the third nand gate 430, the second input terminal of the fourth nand gate 440 is electrically connected to the output terminal of the second nand gate 420, and the output terminal of the fourth nand gate 440 is configured to output the latch result (O) and send the latch result (O) to the reference voltage generating circuit 100 and the count comparator 300.
Specifically, when the comparison result of the comparator 200 is inverted, the reset signal R is sent to the latch 400, so that the reset function of the latch 400 is turned on, and then the latch signal (I) output from the counter comparator 300 is input to the latch 400, so that the latch content in the latch 400 is updated to the latest state, and is fed back to the reference voltage generating circuit 100 and the counter comparator 300 through the latch result (O). When the reset signal (R) is in the inactive state (low level), the intermediate states M1 and M2 are high, and the latch result (O) will remain unchanged regardless of the high signal/low level of the latch signal (I) by the logic relationship of the nand gate in the latch 400. When the reset signal (R) is in an operating state (high level), if the latch signal (I) is in a low level, M1 is in a low level, M2 is in a high level and the latch result (O) is in a low level through the logic relation of the NAND gate; when the reset signal (R) is in an operating state (high level), if the latch signal (I) is high level, M1 is high level, M2 is low level, and the latch result (O) is high level by the logical relationship of the nand gate. By the above-described logical relationship, the latch function of the latch 400 is realized.
As shown in fig. 3, in some embodiments of the present invention, the counter comparator 300 includes an inverter D1 and a plurality of flip-flops 310, and each two adjacent flip-flops 310 are connected through a logic gate component 320; the clock input of the first flip-flop 310 is connected to a count pulse (CLK), and the signal input (J, K pin) of each flip-flop 310 is connected to a reset signal (R); the input end of the inverter D1 is connected with a latch result (O); a first input terminal of the logic gate assembly 320 is connected to the latch result (O), a second input terminal of the logic gate assembly 320 is connected to an output terminal (Q pin) of a previous flip-flop 310 between two adjacent flip-flops 310, a third input terminal of the logic gate assembly 320 is connected to an inverted output terminal (Q ̅ pin) of the previous flip-flop 310, a fourth input terminal of the logic gate assembly 320 is connected to an output terminal of the inverter D1, and an output terminal of the logic gate assembly 320 is connected to a clock input terminal of a next flip-flop 310 between two adjacent flip-flops 310; the logic gate component 320 is configured to generate a trigger signal according to the latch result (O), the output signals of the output terminal and the inverting output terminal of the previous flip-flop 310, and the output signal of the output terminal of the inverter D1, and send the trigger signal to the clock input terminal of the next flip-flop 310; when the latch result (O) is at the high level, the signal output by the logic gate component 320 is the signal output by the output terminal of the previous flip-flop 310, and the count comparator 300 counts up; when the latch result (O) is at a low level, the signal output from the logic gate unit 320 is the signal output from the inverting output terminal of the previous flip-flop, and the count comparator 300 counts down. In fig. 3, taking the digital signal (D) as 3Bit as an example, the count comparator 300 includes three flip-flops 310, each flip-flop 310 for outputting a 1Bit signal; it should be noted that the specific number of the flip-flops 310 may be determined according to the digital signals required, and is not limited to three. A count pulse (CLK) is applied to the clock pulse input of the first flip-flop 310, and the flip-flop 310 toggles once every count pulse is input; each stage of flip-flop 310 thereafter performs flip-flop according to the output of the logic gate assembly 320 connected to the previous stage of flip-flop 310 as a trigger signal, thereby implementing an asynchronous counting function.
More specifically, as shown in fig. 3, in some embodiments of the present invention, the logic gate assembly 320 includes a fifth nand gate 321, a sixth nand gate 322, and a seventh nand gate 323; a first input end of the fifth nand gate 321 is connected with the latch result (O), and a second input end of the fifth nand gate 321 is electrically connected with an output end (Q pin) of the previous trigger 310; a first input terminal of the sixth nand gate 322 is electrically connected to the inverting output terminal (Q ̅ pin) of the previous flip-flop 310, and a second input terminal of the sixth nand gate 322 is electrically connected to the output terminal of the inverter D1; a first input of the seventh nand gate 323 is electrically connected to the output of the fifth nand gate 321, a second input of the seventh nand gate 323 is electrically connected to the output of the sixth nand gate 322, and an output of the seventh nand gate 323 is connected to the clock input of the subsequent flip-flop 310. Before the analog-to-digital conversion starts, the counter comparator 300 performs up-counting or down-counting according to the latch result (O), during the comparison of the comparator 200, the counter comparator 300 performs up-counting/down-counting on the counter pulse (CLK), and when the comparator 200 turns over, a reset signal (R) is generated to stop the operation of the counter comparator 300, and at this time, the digital signal (D) output by the counter comparator 300 is the analog-to-digital conversion result of the pixel output voltage. When the latch result (O) is at the high level, UP is at the high level, after passing through the inverter D1, DOWN is at the low level, and at this time, the output of the flip-flop 310 is the value of Q1 output Q after passing through the logic gate component 320, and the count comparator 300 counts UP; when the latch result (O) is low, UP is low, DOWN is high after passing through the inverter D1, and the output of the flip-flop 310 is Q ̅ which is Q1 output after passing through the logic gate unit 320, the count comparator 300 counts DOWN.
In summary, according to the latch ADC for an image sensor of the embodiment of the invention, the pixel output voltages of the adjacent frames are close to each other and have small variation in consideration of the small variation of the brightness of the adjacent frames, so that each analog-to-digital conversion is performed with reference to the analog-to-digital conversion result of the pixel output voltage of the upper frame, the reference voltage generating circuit 100 is controlled to generate the corresponding ramp voltage, and the count comparator 300 is controlled to count from high to low or from low to high. The latching ADC for the image sensor can greatly reduce the working time of an ADC circuit, further greatly reduce the power consumption of the image sensor and improve the analog-to-digital conversion efficiency.
On the other hand, based on the latch ADC for an image sensor, the embodiment of the invention further provides an analog-to-digital conversion method for the latch ADC of an image sensor, as shown in fig. 4, which includes the following steps:
step S100: the reference voltage generation circuit 100 generates a ramp voltage (V-ref);
step S200: the comparator 200 compares the ramp voltage (V-ref) with the pixel output voltage (V-sig) and outputs a reset signal (R) when the comparison result is inverted;
Step S300: the count comparator 300 counts up or down the count pulse (CLK), and after receiving the reset signal (R), stops counting to obtain a count result, converts the pixel output voltage into a corresponding digital signal (D) according to the count result, and generates a latch signal (I);
specifically, before the analog-to-digital conversion starts, the count comparator 300 judges the up-count or the down-count according to the latch result (O), and in the process of the comparison by the comparator 200, the count comparator 300 counts up/down the count pulse; as shown in fig. 3, when the latch result (O) is at high level, UP is at high level, after passing through the inverter D1, DOWN is at low level, and at this time, the flip-flop 310 outputs a value of Q1 output Q after passing through the logic gate component 320, and the count comparator 300 counts UP; when the latch result (O) is low, UP is low, DOWN is high after passing through the inverter D1, and the output of the flip-flop 310 is Q ̅ which is Q1 output after passing through the logic gate unit 320, the count comparator 300 counts DOWN. When the count comparator 300 receives the reset signal (R), stops counting, obtains a count result, and based on the count result, can convert the pixel output voltage into a corresponding digital signal (D), and generate a latch signal (I), and transmit the latch signal (I) to the latch 400.
Step S400: the latch 400 latches the latch signal (I) according to the reset signal (R) to obtain a latch result (O), and transmits the latch result (O) to the reference voltage generation circuit 100 and the count comparator 300;
specifically, when the magnitude relation of the ramp voltage and the pixel output voltage is inverted, the comparison result of the comparator 200 is inverted, a reset signal (R) is sent to the latch 400 so that the reset function of the latch 400 is turned on, then a latch signal (I) output from the count comparator 300 is input to the latch 400 so that the latch content in the latch 400 is updated to the latest state, and is fed back to the reference voltage generation circuit 100 and the count comparator 300 through the latch result (O). When the reset signal (R) is in the inactive state (low level), the intermediate states M1 and M2 are high at the same time, and the latch result (O) will remain unchanged regardless of the high signal/low level of the latch signal (I) by the logic relationship of the nand gate in the latch 400. When the reset signal (R) is in an operating state (high level), if the latch signal (I) is in a low level, M1 is in a low level, M2 is in a high level and the latch result (O) is in a low level through the logic relation of the NAND gate; when the reset signal (R) is in an operating state (high level), if the latch signal (I) is high level, M1 is high level, M2 is low level, and the latch result (O) is high level by the logical relationship of the nand gate. By the above-described logical relationship, the latch function of the latch 400 is realized.
Step S500: the reference voltage generating circuit 100 updates the ramp voltage according to the latch result, and the count comparator 300 determines to count up or count down according to the latch result; returning to step S200, the pixel output voltages of the next frame are converted into corresponding digital signals until the analog-to-digital conversion of all the pixel output voltages is completed.
Specifically, after the latch 400 sends the latch result (O) to the reference voltage generating circuit 100, the reference voltage generating circuit 100 will refer to the latch result to generate a corresponding ramp voltage, so that the generated ramp voltage is closer to the pixel output voltage of the next frame, and when the comparator 200 compares the pixel output voltage of the next frame with the ramp voltage, the comparison result can be flipped faster, so that the count comparator 300 finishes counting as soon as possible, further improving the analog-to-digital conversion efficiency and greatly reducing the power consumption of the image sensor.
Therefore, according to the analog-to-digital conversion method of the latch ADC for the image sensor of the embodiment of the invention, considering that the brightness variation of the adjacent frame is small, the pixel output voltage of the adjacent frame is relatively close and the variation is small, therefore, the analog-to-digital conversion result of the pixel output voltage of the upper frame is referred to at each analog-to-digital conversion, the reference voltage generating circuit 100 is controlled to generate the corresponding ramp voltage, and the count comparator 300 is controlled to count from high to low or from low to high. The latching ADC for the image sensor can greatly reduce the working time of an ADC circuit, further greatly reduce the power consumption of the image sensor and improve the analog-to-digital conversion efficiency.
On the other hand, the embodiment of the invention also provides an image sensor, which comprises the latch ADC for the image sensor.
On the other hand, the embodiment of the invention also provides a storage medium, wherein the storage medium is a computer readable storage medium, and the storage medium stores a computer program which is executed by a processor to realize the method for converting the analog to digital of the latch ADC of the image sensor.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The apparatus embodiments described above are merely illustrative, in which the elements illustrated as separate components may or may not be physically separate, implemented to reside in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and/or processing capabilities described in connection with a particular device or component may be performed by any other device or component. In addition, while various exemplary implementations and architectures have been described in terms of embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.
Certain aspects of the present disclosure are described above with reference to block diagrams and flowchart illustrations of systems, methods, systems and/or computer program products according to example embodiments. It will be understood that one or more blocks of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by executing computer-executable program instructions. Also, some of the blocks in the block diagrams and flowcharts may not need to be performed in the order shown, or may not need to be performed in their entirety, according to some embodiments. In addition, additional components and/or operations beyond those shown in blocks of the block diagrams and flowcharts may be present in some embodiments.
Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions, elements or steps, or combinations of special purpose hardware and computer instructions.
Program modules, applications, etc. described herein may include one or more software components including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functions described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.
The software components may be encoded in any of a variety of programming languages. An exemplary programming language may be a low-level programming language, such as an assembly language associated with a particular hardware architecture and/or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler prior to execution by a hardware architecture and/or platform. Another exemplary programming language may be a higher level programming language that may be portable across a variety of architectures. Software components, including higher-level programming languages, may need to be converted to an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages include, but are not limited to, a macro language, a shell or command language, a job control language, a scripting language, a database query or search language, or a report writing language. In one or more exemplary embodiments, a software component containing instructions of one of the programming language examples described above may be executed directly by an operating system or other software component without first converting to another form.
The software components may be stored as files or other data storage constructs. Software components having similar types or related functionality may be stored together, such as in a particular directory, folder, or library. The software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention.

Claims (10)

1. A latching ADC for an image sensor, comprising:
a reference voltage generation circuit for generating a ramp voltage;
the first input end of the comparator is connected with the pixel output voltage, the second input end of the comparator is connected with the slope voltage, and the comparator is used for comparing the pixel output voltage with the slope voltage and outputting a reset signal when the comparison result is overturned;
the first input end of the counting comparator is connected with the output end of the comparator; the counting comparator is used for counting up or down the counting pulse, stopping counting after receiving the reset signal to obtain a counting result, converting the pixel output voltage into a corresponding digital signal according to the counting result, and generating a latch signal;
The first input end of the latch is connected with the output end of the comparator, the second input end of the latch is connected with the output end of the counting comparator, and the output end of the latch is respectively connected with the input end of the reference voltage generating circuit and the second input end of the counting comparator; the latch is used for latching the latch signal according to the reset signal to obtain a latch result, and sending the latch result to the reference voltage generating circuit and the count comparator; the reference voltage generating circuit is used for updating the slope voltage according to the latching result, and the counting comparator is used for counting up or down according to the latching result.
2. The latching ADC for an image sensor of claim 1, wherein the latch comprises a first nand gate, a second nand gate, a third nand gate, and a fourth nand gate;
the first input end of the first NAND gate is connected with the reset signal, and the second input end of the first NAND gate is connected with the output end of the second NAND gate;
the first input end of the second NAND gate is connected with the reset signal, and the second input end of the second NAND gate is connected with the latch signal;
The first input end of the third NAND gate is electrically connected with the output end of the first NAND gate, and the second input end of the third NAND gate is electrically connected with the output end of the fourth NAND gate;
the first input end of the fourth NAND gate is electrically connected with the output end of the third NAND gate, the second input end of the fourth NAND gate is electrically connected with the output end of the second NAND gate, and the output end of the fourth NAND gate is used for outputting the latching result and sending the latching result to the reference voltage generating circuit and the counting comparator.
3. The latching ADC for image sensors of claim 1, wherein said count comparator comprises an inverter and a plurality of flip-flops, each adjacent two of said flip-flops being connected by a logic gate assembly;
the clock input end of the first trigger is connected with the counting pulse, and the signal input end of each trigger is connected with the reset signal;
the input end of the inverter is connected with the latch result;
the first input end of the logic gate component is connected with the latching result, the second input end of the logic gate component is connected with the output end of the previous trigger between two adjacent triggers, the third input end of the logic gate component is connected with the inverting output end of the previous trigger, the fourth input end of the logic gate component is connected with the output end of the inverter, and the output end of the logic gate component is connected with the clock input end of the next trigger between two adjacent triggers;
The logic gate component is used for generating a trigger signal according to the latching result, the output signals of the output end and the reverse phase output end of the previous trigger and the output signal of the output end of the reverse phase device, and sending the trigger signal to the clock input end of the next trigger; when the latching result is high level, the signal output by the logic gate component is the signal output by the output end of the previous trigger, and the counting comparator counts upwards; when the latch result is low level, the signal output by the logic gate component is the signal output by the inverting output end of the previous trigger, and the count comparator counts down.
4. The latching ADC for image sensors according to claim 3, wherein said logic gate assembly comprises a fifth nand gate, a sixth nand gate, and a seventh nand gate;
the first input end of the fifth NAND gate is connected with the latching result, and the second input end of the fifth NAND gate is electrically connected with the output end of the previous trigger;
the first input end of the sixth NAND gate is electrically connected with the inverting output end of the previous trigger, and the second input end of the sixth NAND gate is electrically connected with the output end of the inverter;
The first input end of the seventh NAND gate is electrically connected with the output end of the fifth NAND gate, the second input end of the seventh NAND gate is electrically connected with the output end of the sixth NAND gate, and the output end of the seventh NAND gate is connected with the clock input end of the next trigger.
5. A method of analog-to-digital conversion of a latching ADC for an image sensor, based on the latching ADC for an image sensor of any one of claims 1-4, the method comprising:
the reference voltage generating circuit generates a ramp voltage;
the comparator compares the slope voltage with the pixel output voltage and outputs a reset signal when the comparison result is overturned;
the counting comparator counts up or down the counting pulse, stops counting after receiving the reset signal to obtain a counting result, converts the pixel output voltage into a corresponding digital signal according to the counting result, and generates a latch signal;
the latch latches the latch signal according to the reset signal to obtain a latch result, and sends the latch result to the reference voltage generating circuit and the count comparator;
The reference voltage generating circuit updates the slope voltage according to the latching result, and the counting comparator judges to count up or count down according to the latching result; and returning to the step of comparing the slope voltage with the pixel output voltage by the comparator and outputting a reset signal when the comparison result is overturned, and converting the pixel output voltage of the next frame into a corresponding digital signal until the analog-to-digital conversion of all the pixel output voltages is completed.
6. The method of analog-to-digital conversion of a latching ADC for an image sensor according to claim 5, wherein said latch comprises a first nand gate, a second nand gate, a third nand gate and a fourth nand gate; the first input end of the first NAND gate is connected with the reset signal, and the second input end of the first NAND gate is connected with the output end of the second NAND gate; the first input end of the second NAND gate is connected with the reset signal, and the second input end of the second NAND gate is connected with the latch signal; the first input end of the third NAND gate is electrically connected with the output end of the first NAND gate, and the second input end of the third NAND gate is electrically connected with the output end of the fourth NAND gate; the first input end of the fourth NAND gate is electrically connected with the output end of the third NAND gate, the second input end of the fourth NAND gate is electrically connected with the output end of the second NAND gate, and the output end of the fourth NAND gate is used for outputting the latching result and sending the latching result to the reference voltage generating circuit and the counting comparator.
7. The method of analog-to-digital conversion of a latching ADC for an image sensor according to claim 5, wherein said count comparator comprises an inverter and a plurality of flip-flops, each adjacent two of said flip-flops being connected by a logic gate assembly; the clock input end of the first trigger is connected with the counting pulse, and the signal input end of each trigger is connected with the reset signal; the input end of the inverter is connected with the latch result; the first input end of the logic gate component is connected with the latching result, the second input end of the logic gate component is connected with the output end of the previous trigger between two adjacent triggers, the third input end of the logic gate component is connected with the inverting output end of the previous trigger, the fourth input end of the logic gate component is connected with the output end of the inverter, and the output end of the logic gate component is connected with the clock input end of the next trigger between two adjacent triggers; the logic gate component is used for generating a trigger signal according to the latching result, the output signals of the output end and the reverse phase output end of the previous trigger and the output signal of the output end of the reverse phase device, and sending the trigger signal to the clock input end of the next trigger; when the latching result is high level, the signal output by the logic gate component is the signal output by the output end of the previous trigger, and the counting comparator counts upwards; when the latch result is low level, the signal output by the logic gate component is the signal output by the inverting output end of the previous trigger, and the count comparator counts down.
8. The method of analog-to-digital conversion of a latching ADC for an image sensor of claim 7, wherein said logic gate assembly comprises a fifth nand gate, a sixth nand gate, and a seventh nand gate; the first input end of the fifth NAND gate is connected with the latching result, and the second input end of the fifth NAND gate is electrically connected with the output end of the previous trigger; the first input end of the sixth NAND gate is electrically connected with the inverting output end of the previous trigger, and the second input end of the sixth NAND gate is electrically connected with the output end of the inverter; the first input end of the seventh NAND gate is electrically connected with the output end of the fifth NAND gate, the second input end of the seventh NAND gate is electrically connected with the output end of the sixth NAND gate, and the output end of the seventh NAND gate is connected with the clock input end of the next trigger.
9. An image sensor comprising a latching ADC for an image sensor as claimed in any one of claims 1 to 4.
10. A storage medium storing computer-executable instructions for causing a computer to perform the analog-to-digital conversion method for a latch ADC of an image sensor according to any one of claims 5 to 8.
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