CN117318543B - Starting circuit, driving device and method of direct current brushless motor - Google Patents
Starting circuit, driving device and method of direct current brushless motor Download PDFInfo
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- CN117318543B CN117318543B CN202311597199.6A CN202311597199A CN117318543B CN 117318543 B CN117318543 B CN 117318543B CN 202311597199 A CN202311597199 A CN 202311597199A CN 117318543 B CN117318543 B CN 117318543B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/08—Arrangements for controlling the speed or torque of a single motor
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/14—Electronic commutators
- H02P6/16—Circuit arrangements for detecting position
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/20—Arrangements for starting
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
Abstract
The invention provides a starting circuit, a driving device and a method of a direct current brushless motor, which relate to the technical field of motor driving, wherein a counter of the starting circuit is used for outputting a first counting signal representing the rotation times of a motor; the first multiplexer is used for selectively outputting a first duty cycle signal or a second duty cycle signal according to the first counting signal; the digital comparator is used for comparing the signals output by the first multiplexer and the digital controllable adder-subtractor and generating an addition-subtraction control signal so as to control the digital controllable adder-subtractor to add or subtract the period of the clock signal and output a second counting signal, so that the conversion control circuit generates a second pulse width modulation signal so as to control the rotating speed of the motor. The starting circuit, the driving device and the method of the direct current brushless motor ensure the success rate of motor starting and can be beneficial to improving the service efficiency and the service life of the motor.
Description
Technical Field
The present invention relates to the technical field of motor driving, and in particular, to a starting circuit, a driving device and a method for a brushless dc motor.
Background
Compared with a brush direct current motor, the electronic commutation mode of the direct current brushless motor replaces the original brush commutation mode. The characteristics of faster dynamic response, long service life, high rotating speed range, high efficiency, low noise and good rotating speed-torque characteristics make the brushless DC motor have advantages over induction motors and brush DC motors, so that the market share of the brushless DC motor also shows a gradually increasing trend in recent years.
The driving of a brushless dc motor often employs a pwm duty cycle modulation strategy to control motor speed. As shown in a schematic diagram of a driving manner of a motor in fig. 1, in general, output duty ratios of OUT1 and OUT2 are linearly related to an input duty ratio of a pulse width modulation signal PWMin, so that a motor speed is adjusted by configuring the input duty ratio of the pulse width modulation signal PWMin.
However, in the driving method shown in fig. 1, during the motor start-up phase, the phenomenon that the input duty ratio of the pwm signal PWMin is too large or too small easily occurs, and the voltage withstand of the chip of the driving circuit is tested if the input duty ratio of the pwm signal PWMin is too large; if the input duty ratio of the pwm signal PWMin is too small, the motor may not be started, which severely limits the service efficiency and service life of the motor.
Disclosure of Invention
Accordingly, an object of the present invention is to provide a starting circuit, a driving device and a method for a brushless dc motor, so as to ensure a success rate of motor starting and to suppress a kick current during starting, thereby alleviating the above-mentioned technical problems.
In a first aspect, an embodiment of the present invention provides a starting circuit of a brushless dc motor, which is applied to a brushless dc motor system, and the starting circuit includes a counter, a first multiplexer, a digital comparator, a digitally controllable adder-subtractor and a conversion control circuit, wherein: the counter is used for recording the rotation times of the motor and outputting a first counting signal representing the rotation times of the motor; the first multiplexer comprises a first input end, a second input end, a control end and an output end; the first input end of the first multiplexer is used for receiving a first duty cycle signal, and the first duty cycle signal represents a preset fixed duty cycle; the second input end of the first multiplexer is used for receiving a second duty cycle signal, and the second duty cycle signal represents the duty cycle of the first pulse width modulation signal; the control end of the first multiplexer is used for receiving a first counting signal; the first multiplexer is used for selecting to output a first duty cycle signal or a second duty cycle signal at the output end according to the value of the first counting signal; the digital comparator comprises a first input end, a second input end and an output end; the first input end of the digital comparator is connected with the output end of the first multiplexer, and the second input end of the digital comparator is connected with the output end of the digital controllable adder-subtractor; the digital comparator is used for comparing the signal output by the output end of the first multiplexer with the second counting signal output by the digital controllable adder-subtractor and generating an addition-subtraction control signal; the digital controllable adder-subtractor is provided with an input end, a control end and an output end, wherein the input end of the digital controllable adder-subtractor receives a clock signal, the control end of the digital controllable adder-subtractor receives an addition-subtraction control signal, the addition-subtraction control signal controls the digital controllable adder-subtractor to carry out addition counting or subtraction counting on the period of the clock signal, and a second counting signal is output at the output end; the conversion control circuit is used for receiving the second counting signal and generating a second pulse width modulation signal according to the second counting signal, and the second pulse width modulation signal is used for controlling the on and off time of a power switch in the direct current brushless motor system so as to control the rotating speed of the motor.
In a second aspect, an embodiment of the present invention further provides a driving apparatus for a dc brushless motor, including: the starting circuit of the first aspect is used for generating a second pulse width modulation signal; the Hall sensor senses the rotation position of the motor and generates a Hall periodic signal; and the driving circuit is connected with the starting circuit, receives the Hall periodic signal and the second pulse width modulation signal, and generates a driving signal according to the Hall periodic signal and the second pulse width modulation signal, wherein the driving signal is used for driving the on and off of a power switch in the DC brushless motor system.
In a third aspect, an embodiment of the present invention further provides a method for driving a brushless dc motor, including: the driving motor rotates at a preset constant rotating speed, wherein the constant rotating speed is determined by a preset first duty ratio signal; recording the rotation times of the motor, and judging the magnitudes of a second duty ratio signal and a preset first duty ratio signal when the rotation times of the motor reach a preset time threshold, wherein the second duty ratio signal is the duty ratio of a first pulse width modulation signal provided by a microprocessor, and the rotating speed of the motor can be changed by changing the value of the second duty ratio signal; when the second duty ratio signal is smaller than the first duty ratio signal, controlling the motor rotation speed to gradually decrease until the motor rotation speed is equal to a motor rotation speed value corresponding to the second duty ratio signal; and when the second duty ratio signal is larger than the first duty ratio signal, controlling the motor rotation speed to be gradually increased until the motor rotation speed is equal to a motor rotation speed value corresponding to the second duty ratio signal.
The embodiment of the invention has the following beneficial effects:
in the control process of the starting circuit, the driving device and the method of the direct current brushless motor, the first duty cycle signal representing the preset constant duty cycle is adopted to drive the motor in the initial stage of motor starting, so that the phenomenon that the duty cycle is too large when the motor is started by directly using the duty cycle signal of the first pulse width modulation signal can be effectively avoided, meanwhile, the situation that the motor cannot be started due to too small duty cycle signal can be avoided by setting the constant duty cycle, the success rate of motor starting is further ensured, and the use efficiency and the service life of the motor can be improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional motor driving method;
fig. 2 is a schematic diagram of a dc brushless motor system according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a start-up circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a digitally controllable adder-subtractor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another starting circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of duty cycle variation according to an embodiment of the present invention;
fig. 7 is a flowchart of a driving method of a brushless dc motor according to an embodiment of the present invention.
Reference numerals: a 100-Hall sensor; 200-starting a circuit; 300-a driving circuit; 400-a power switching unit; 500-motors; a 10-duty cycle encoding circuit; 20-a counter; 30-a first multiplexer; a 40-digital comparator; 50-a digitally controllable adder-subtractor; a 60-conversion control circuit; 70-a second multiplexer; 401-an addition-subtraction digital unit; 601-an analog-to-digital converter; 602-a triangular wave generator; 603-analog comparator.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Aiming at the problems in the prior art, the embodiment of the invention provides a starting circuit, a driving device and a method of a direct current brushless motor, which are used for ensuring the success rate of motor starting and inhibiting the recoil current during starting so as to further alleviate the technical problems.
For the sake of understanding the present embodiment, a starting circuit for a brushless dc motor according to an embodiment of the present invention will be described in detail.
In one possible implementation manner, the embodiment of the present invention provides a starting circuit (hereinafter referred to as a starting circuit) of a brushless dc motor, which is applied to a brushless dc motor system, and in particular, the starting circuit of the embodiment of the present invention is applied to a driving device (hereinafter referred to as a driving device) of a brushless dc motor, where the driving device is disposed in the brushless dc motor system to drive the brushless dc motor, and especially provides soft start for the brushless dc motor during the starting process of the brushless dc motor.
The dc brushless motor in the embodiment of the present invention is also referred to as a brushless dc motor, or simply referred to as a motor, and may specifically include a single-phase dc brushless motor, or a three-phase dc brushless motor, or the like, which is specifically based on the actual use situation, and the embodiment of the present invention is not limited thereto.
For ease of understanding, fig. 2 shows a schematic diagram of a dc brushless motor system, including a start circuit 200, a driving circuit 300, a power switch unit 400, a motor 500, and a hall sensor 100 in an embodiment of the present invention, and fig. 2 also shows a power supply VCC and a ground GND of the power switch unit 400, where the power supply VCC is a power supply for driving power switches S1, S2, S3, and S4 in the power switch unit 400.
In fig. 2, the start circuit 200 is configured to receive the first pwm signal PWMin and the hall periodic signal Hlogic sampled and output by the hall sensor 100, process the first pwm signal PWMin according to the hall periodic signal Hlogic, and then send the second pwm signal PWMout to the drive circuit 300, and the drive circuit 300 is configured to generate the corresponding drive signal DRV according to the second pwm signal PWMout and the hall periodic signal Hlogic, so as to control the on and off time of the power switches S1, S2, S3, S4 in the power switch unit 400 to regulate the current flowing through the motor, and further control the rotation speed of the motor 500.
Next, a specific circuit diagram of the start-up circuit 200 will be provided according to one embodiment of the present invention. Specifically, as shown in fig. 3, the start-up circuit includes a counter 20, a first multiplexer 30, a digital comparator 40, a digitally controllable adder-subtractor 50, and a conversion control circuit 60.
The counter 20 is for recording the number of motor rotations and outputting a first count signal Sel representing the number of motor rotations.
The first multiplexer 30 includes a first input, a second input, a control, and an output; the control end of the first multiplexer 30 is connected with the counter 20 to receive the first count signal Sel; a first input of the first multiplexer 30 is configured to receive a first duty cycle signal d_start < N:1> that characterizes a preset constant duty cycle; a second input of the first multiplexer 30 is configured to receive a second duty cycle signal DIN < N:1>, wherein the second duty cycle signal DIN < N:1> characterizes the duty cycle of the first pulse width modulated signal PWMin in fig. 2; the control end of the first multiplexer 30 is configured to receive the first count signal Sel; the first multiplexer 30 is configured to select the selection signal DSEL < N:1> to be output at its output terminal according to the value of the first count signal Sel, where the selection signal DSEL < N:1> is the first duty signal d_start < N:1> or the second duty signal DIN < N:1>. In one embodiment, the first duty ratio signal d_start < N:1>, the second duty ratio signal DIN < N:1> and the selection signal DSEL < N:1> may include digital signals of binary codes, where < N:1> may represent a series of N-bit binary codes, N represents the number of bits of the binary codes, and N is an integer greater than or equal to 1, and a suitable N value may be flexibly selected according to practical applications. In the following written description and drawings, the explanation of the < N:1> symbol appearing is similar to that explained herein and will not be described in a tired way.
The digital comparator 40 includes a first input, a second input, and an output; a first input end of the digital comparator 40 is connected with an output end of the first multiplexer 30, and a second input end of the digital comparator 40 is connected with an output end of the digital controllable adder-subtractor 50; the digital comparator 40 is used for comparing the selection signal DSEL < N:1> output from the output terminal of the first multiplexer 30 with the second count signal OUT < N:1> output from the digital controllable adder-subtractor 50 and generating the addition-subtraction control signal P.
The digitally controllable adder-subtractor 50 has an input, a control, and an output, the input of the digitally controllable adder-subtractor 50 receives the clock signal CLK, the control of the digitally controllable adder-subtractor 50 receives the addition-subtraction control signal P, which controls the digitally controllable adder-subtractor 50 to count up or down the period of the clock signal CLK and to output a second count signal OUT < N:1> at the output.
The conversion control circuit 60 receives the second count signal OUT < N:1>, and generates a second pulse width modulation signal PWMout according to the second count signal OUT < N:1>, where the second pulse width modulation signal PWMout is used to control on and off times of the power switches S1, S2, S3, S4 in the power switch unit 400 in the dc brushless motor system, so as to control the rotation speed of the motor 500.
In one embodiment, as shown in fig. 2, the second pwm signal PWMout is supplied to the driving circuit 300, and the driving circuit 300 further generates the driving signals DRV (including the driving signals DRV1, DRV2, DRV3 and DRV 4) to drive and control the on and off times of the power switches S1, S2, S3 and S4 in the power switch unit 400.
In actual use, the counter 20 is used to record the number of motor revolutions. In one embodiment, the number of motor revolutions may be used as information characterizing the degree of motor start, i.e. whether the motor is fully started. In general, the motor starts to rotate from rest after receiving the duty cycle signal, and the rotation speed gradually increases until the motor is completely started, and in this process, the rotation number of the motor is increased more and more, so that the motor start state can be truly obtained by recording the rotation number of the motor. In the embodiment of the present invention, the counter 20 is a first counting signal Sel output according to the recorded number of rotations of the motor.
In one implementation, a threshold number of times may be pre-set for counter 20, which is used to characterize the motor start-up condition. In one embodiment, the number of times threshold characterizes motor start-up completion. When the number of motor rotations recorded by the counter 20 does not reach the number threshold, the first count signal Sel is not output, but the number of motor rotations is continuously recorded until the number threshold is reached, and then the first count signal Sel is output.
In another embodiment, the above-described number of times threshold may be set in the first multiplexer 30. The counter 20 continuously records the rotation times of the motor, the first count signal Sel indicates the real-time rotation times of the motor and is sent to the first multiplexer 30, and when the first count signal Sel reaches the time threshold, the first multiplexer 30 is triggered to selectively output the duty ratio signals input by the first input end and the second input end of the first multiplexer 30. In one embodiment, the first multiplexer 30 outputs the first duty ratio signal D_start < N:1> before the first count signal Sel reaches the count threshold; when the first count signal Sel reaches the count threshold, the first multiplexer 30 outputs the second duty signal DIN < N:1>.
In one embodiment, the above-mentioned frequency threshold is usually the result of multiple tests under laboratory conditions, that is, the motor is substantially completely started under the number of rotations of the motor represented by the frequency threshold, and the specific frequency threshold may be set according to different motors, and different test conditions and use environments, which is not limited by the embodiment of the present invention.
Further, since the motor in the embodiment of the present invention mostly adopts a dc brushless motor, that is, adopts an electronic commutation manner during rotation, in the embodiment of the present invention, the number of times of motor rotation during rotation of the motor is monitored by a hall sensor, for example, the hall sensor 100 in fig. 2. In general, the hall sensor 100 outputs a hall period signal Hlogic that characterizes the hall period of the motor every two adjacent single pulse intervals. It will be appreciated that a hall period refers to the time that the motor rotor rotates across two different poles. The hall period is related to the number of pole pairs of the motor rotor. For example, the motor rotor includes a pair of magnetic poles, and the hall period is the time of one rotation of the rotor; for another example, when the motor rotor includes three pairs of poles, the hall period is one third of the time the rotor rotates. The counter 20 receives the hall period signal Hlogic output by the hall sensor, counts the period of the hall period signal Hlogic, and generates a first count signal Sel, which characterizes the period count value of the hall period signal Hlogic. Also, when counting the number of times of motor rotation by the hall sensor 100, the above-described number of times threshold may be set as a period threshold of the hall period signal Hlogic. In one embodiment, when the period of the hall period signal Hlogic reaches the period threshold, the first count signal Sel is generated, and the first multiplexer 30 is triggered to select the duty cycle signals input by the first input terminal and the second input terminal.
In order to realize soft start of the motor, in the embodiment of the invention, when the motor is just started, a constant duty ratio signal, namely, a first duty ratio signal D_start < N:1>, is adopted to control the motor to rotate at a constant rotating speed, and when the motor is completely started, a second duty ratio signal DIN < N:1> is adopted to control the rotating speed of the motor. Therefore, in the embodiment of the present invention, the first multiplexer 30 is configured to select to output the first duty signal d_start < N:1> or the second duty signal DIN < N:1> at the output terminal thereof according to the value of the first count signal Sel.
In one embodiment, the counter 20 continues to record the number of motor rotations until the first count signal Sel is output after reaching the preset number threshold. The control end of the first multiplexer 30 is triggered by the first count signal Sel, and when the number of rotations of the motor is less than the preset number threshold, it indicates that the motor is not completely started, and the counter 20 will not output the first count signal Sel, so the first multiplexer 30 selects to output the first duty ratio signal d_start < N:1> at its output end; if the number of rotations of the motor reaches the preset number threshold, the counter 20 outputs the first count signal Sel, and the control terminal of the first multiplexer 30 selects to output the second duty ratio signal DIN < N:1> at its output terminal after receiving the first count signal Sel.
The first multiplexer 30 selects the mode of outputting the first duty cycle signal d_start < N:1> or the second duty cycle signal DIN < N:1> at the output end thereof, so that the motor can be driven by adopting the first duty cycle signal d_start < N:1> representing the preset constant duty cycle at the initial stage of motor starting, thereby effectively avoiding the phenomenon that the duty cycle is too large when the motor is started by directly using the duty cycle signal of the first pulse width modulation signal PWMin, namely, the first duty cycle signal DIN < N:1>, and simultaneously avoiding the situation that the motor cannot be started due to too small duty cycle signal by setting the constant duty cycle, further ensuring the success rate of motor starting and being beneficial to improving the service efficiency and service life of the motor.
Further, the first duty ratio signal d_start < N:1> or the second duty ratio signal DIN < N:1> outputted by the first multiplexer 30 in the embodiment of the present invention is not directly applied to the motor, but approaches the target value in a gradually increasing or gradually decreasing manner after further processing by the subsequent digital comparator 40 and the digitally controllable adder-subtractor 50, and then is transmitted to the subsequent driving device, so as to avoid current abrupt change caused by abrupt change of the duty ratio signal of the driving motor, and further reduce the risk of voltage overshoot caused by current abrupt change when the motor commutates.
Specifically, when the signal output from the output terminal of the first multiplexer 30 is greater than the second count signal OUT < N:1>, the addition/subtraction control signal P output from the digital comparator 40 is used to control the digital controllable adder-subtractor 50 to perform addition counting on the period of the clock signal CLK; and, when the signal output from the output terminal of the first multiplexer 30 is smaller than the second count signal OUT < N:1>, the addition/subtraction control signal P output from the digital comparator 40 controls the digital controllable adder-subtractor 50 to perform the subtraction count on the period of the clock signal CLK.
That is, the digital comparator 40 in the embodiment of the present invention is responsible for comparing the magnitude of the selection signal DSEL < n:1> output from the output terminal of the first multiplexer 30 and the magnitude of the second count signal OUT < n:1> output from the digitally controllable adder-subtractor 50, and generating the add-subtract control signal P, which is typically a high-low level signal, for example, the processing logic of the digital comparator 40 may be expressed as: when OUT < N1 > is smaller than DSEL < N1 >, adding and subtracting the control signal P to be 0, and adding the control digital controllable adder-subtractor; when OUT < N1 > is higher than DSEL < N1 >, the addition and subtraction control signal P is 1, and the digital controllable addition and subtraction device is controlled to perform subtraction operation.
The signal DSEL < N:1> output from the output terminal of the first multiplexer 30 includes the first duty signal d_start < N:1> or the second duty signal DIN < N:1>. In one embodiment, the clock signal CLK may be generated by a circuit built inside the chip; in yet another embodiment, the clock signal CLK may also be provided by a microprocessor. In one embodiment, as shown in the embodiment of fig. 5, the digitally controllable adder-subtractor 50 further includes a second input terminal for receiving a default count value, and the digitally controllable adder-subtractor 50 adds one to the value of the second count signal OUT < N:1> after each count of cycles of the clock signal for the default count value.
Fig. 4 also shows a schematic diagram of a digitally controllable adder-subtractor 50 for ease of understanding, where the digitally controllable adder-subtractor 50 in the embodiment of the present invention is composed of a plurality of addition-subtraction digital units and flip-flops, and for ease of explanation, fig. 4 illustrates 4 addition-subtraction digital units 401 and 4D flip-flops as an example. Each of the add-subtract digital units 401 shows a data input a, a default count value input B, a control terminal P, a carry/borrow input CI, a carry/borrow output CO, and an output S. The D flip-flop then shows the clock input CLK, the data input D and the output Q. It should be understood that the addition and subtraction digital unit and the flip-flop shown in fig. 4 are merely exemplary illustrations, and the processing manners of the terminals of the addition and subtraction digital unit and the flip-flop may be set according to actual situations in actual use, and the embodiment of the present invention is not limited thereto.
As shown in fig. 4, a plurality of addition and subtraction digital units are sequentially connected, that is, a carry/borrow output end CO of a previous addition and subtraction digital unit is connected with a carry/borrow input end CI of a next addition and subtraction digital unit, a control end of each addition and subtraction digital unit is connected, a control end forming a digital controllable addition and subtraction unit receives an addition and subtraction control signal P, trigger ends of the trigger correspond to the addition and subtraction digital units one by one, a trigger end of each trigger is connected to the corresponding addition and subtraction digital unit, specifically, a data input end D of the trigger is connected with an output end S of the corresponding addition and subtraction digital unit, and an output end Q of the trigger is connected with a data input end a of the corresponding addition and subtraction digital unit; the clock inputs CLK of the plurality of flip-flops are connected to form a first input of the digitally controllable adder-subtractor 50 for obtaining the clock signal CLK; the default count value input B of each add-subtract digital unit corresponds to a second input of the digitally controllable add-subtract device 50 to receive the default count value. In the embodiment shown in FIG. 4, the default count value is an N-bit two-level system code consisting of the bits DF < N >, DF < N-1>, DF < N-2>, DF < N-3>, etc.
Based on the digitally controllable adder-subtractor shown in fig. 4, the adder-subtractor digital unit and the D flip-flop are connected according to the schematic diagram shown in fig. 4, so as to form a digitally controllable adder-subtractor whose duty cycle rising or falling slope (e.g., slopes k1 and k2 shown in fig. 6) is controlled by the clock signal CLK. The higher the frequency of the clock signal CLK, the faster the speed of accumulation or subtraction of the digitally controllable adder-subtractor, and the lower the frequency of the clock signal CLK, the slower the speed of accumulation or subtraction of the digitally controllable adder-subtractor. By means of the digitally controllable adder-subtractor shown in fig. 4, when the values of the input first duty cycle signal d_start < N:1> and the second duty cycle signal DIN < N:1> differ greatly, the value of the output second count signal OUT < N:1> does not suddenly change, but is brought close to the value of the input second duty cycle signal DIN < N:1> with a fixed slope, so that the sudden change of the current of the motor due to the sudden change of the value of the output second count signal OUT < N:1> is avoided, and the risk of voltage overshoot during commutation of the motor due to the sudden change of the current is reduced.
During motor start-up, the second count signal OUT < N:1> is also stepped up from 0 to the value of the first duty cycle signal D_start < N:1> and remains constant while characterizing the constant duty cycle of the first duty cycle signal D_start < N:1 >. In order to enable the value of the second count signal OUT < N:1> to quickly rise to the value of the first duty cycle signal d_start < N:1>, a higher frequency clock signal (e.g., CLK1 shown in fig. 5) is typically given to the digitally controllable adder-subtractor, and after the motor is completely started, the clock signal frequency (e.g., CLK2 shown in fig. 5) of the digitally controllable adder-subtractor is reduced, so that the value of the second count signal OUT < N:1> gradually approaches the value of the second duty cycle signal DIN < N:1>, and finally, the motor speed is smoothly changed.
Therefore, the starting circuit described in the embodiment of the invention further comprises a second multiplexer. For ease of understanding, fig. 5 also shows a schematic diagram of another starting circuit on the basis of fig. 3. In the embodiment shown in fig. 5, the startup circuit further comprises a second multiplexer 70. Specifically, the second multiplexer 70 includes a first input terminal, a second input terminal, a control terminal, and an output terminal. A first input of the second multiplexer 70 receives a first clock signal, CLK1 in fig. 5, and a second input of the second multiplexer 70 receives a second clock signal, CLK2 in fig. 5; the control terminal of the second multiplexer 70 receives the first count signal Sel; the second multiplexer 70 is configured to select whether to output the first clock signal CLK1 or the second clock signal CLK1 as the clock signal CLK at its output terminal according to the value of the first count signal Sel.
Specifically, when the number of motor rotations is less than the preset number threshold, the second multiplexer 70 selects to output the first clock signal CLK1 at its output; when the number of rotations of the motor reaches the preset number threshold, the second multiplexer 70 selects to output the second clock signal CLK2 at its output; wherein the frequency of the first clock signal CLK1 is greater than the frequency of the second clock signal CLK2.
In one embodiment, if the first count signal Sel is a signal output when the number of times of motor rotation reaches the number threshold, i.e., a signal indicating after the motor is completely started, the second multiplexer 70 may be set such that the first clock signal CLK1 is output before the second multiplexer 70 does not receive the first count signal Sel, and the second clock signal CLK2 is output after the second multiplexer 70 receives the first count signal Sel. By reasonably setting the clock frequency of the first clock signal CLK1, the value of the second count signal OUT < N:1> output by the digital controllable adder-subtractor can be ensured to quickly reach the value of the first duty ratio signal D_start < N:1> at the initial stage of motor start. By reasonably setting the clock frequency of the second clock signal CLK2, the value of the second count signal OUT < N:1> output by the digital controllable adder-subtractor can be enabled to approach the value of the second duty cycle signal DIN < N:1> with a fixed rising or falling slope after the motor is completely started, namely the duty cycle of the output second pulse width modulation signal PWMout approaches the duty cycle of the input first pulse width modulation signal PWMin with a fixed rising or falling slope, so that the phenomenon that the abrupt change of the motor rotation speed is caused by abrupt change of the duty cycle is avoided.
Further, in the embodiment shown in fig. 5, the start-up circuit further includes a duty cycle encoding circuit 10, where the duty cycle encoding circuit 10 is configured to receive the first pulse width modulation signal PWMin, convert the duty cycle information of the first pulse width modulation signal PWMin into a corresponding digital signal, and output a second duty cycle signal DIN < N:1>.
In one embodiment, the first pwm signal PWMin is provided by a microprocessor, which may be a microprocessor of a dc brushless motor system, which may provide the above-mentioned first clock signal CLK1 and second clock signal CLK2 in addition to the first pwm signal PWMin. In other embodiments, the control circuit may be built inside the chip to generate the first pwm signal PWMin, which is specifically based on the actual use situation, which is not limited in the embodiments of the present invention.
Further, a schematic diagram of a conversion control circuit 60 is also shown in fig. 5, according to one embodiment of the present invention. Specifically, as shown in fig. 5, the conversion control circuit 60 in the embodiment of the present invention includes an analog-to-digital converter 601, a triangular wave generator 602, and an analog comparator 603. The analog-to-digital converter 601 is configured to receive the second count signal OUT < N:1>, and convert the second count signal OUT < N:1> into an equivalent analog voltage signal. The triangular wave generator 602 is used for generating a preset triangular wave signal. The analog comparator 603 includes a first input terminal, a second input terminal, and an output terminal, where the first input terminal of the analog comparator 603 receives the equivalent analog voltage signal; a second input terminal of the analog comparator 603 receives the preset triangular wave signal; the analog comparator 603 is configured to compare the equivalent analog voltage signal with a preset triangular wave signal, and generate a second pulse width modulation signal PWMout.
In practical use, the preset triangular wave signal is mainly used for modulating the second count signal OUT < N:1> to generate the second pulse width modulation signal PWMout, and the shape of the preset triangular wave signal may be set according to application requirements, or may be a triangular wave signal with an ascending slope and a descending slope, or may be a ramp signal with only one ascending slope or descending slope, or the like, and specifically may be generated by a corresponding triangular wave generator, and by setting parameters such as the frequency of the triangular wave generator, the preset triangular wave signal required in the embodiment of the present invention is further output. The frequency of the triangular wave generator is the frequency of the second pulse width modulation signal PWMout.
Further, in addition to the above embodiments, the embodiments of the present invention further provide a driving device (abbreviated as a driving device) of a dc brushless motor, and for convenience of understanding, the driving device of the dc brushless motor will be described by taking the schematic diagram of the dc brushless motor system shown in fig. 2 as an example.
Specifically, the driving device in the embodiment of the invention comprises: the start-up circuit 200 is configured to generate a second pulse width modulation signal PWMout; a hall sensor 100 sensing a motor rotational position and generating a hall periodic signal Hlogic, wherein the hall periodic signal Hlogic represents position and speed information of a rotor of the motor; and a driving circuit 300 connected to the starting circuit, wherein the driving circuit 300 receives the hall period signal Hlogic and the second pulse width modulation signal PWMout, and generates a driving signal DRV according to the hall period signal Hlogic and the second pulse width modulation signal PWMout, and the driving signal DRV is used for driving on and off of power switches (such as power switches S1, S2, S3 and S4 in fig. 2) in the dc brushless motor system.
In actual use, based on the driving device, the soft start process of the motor is realized, and the soft start process of the motor is started through the Hall sensor.
Fig. 6 is a diagram illustrating a duty ratio variation of the second pwm signal PWMout according to an embodiment of the present invention. In the embodiment shown in fig. 6, the duty cycle shown in the ordinate is represented as the duty cycle of the second pwm signal PWMout, in the embodiment of the present invention, simply referred to as Dout, i.e. Dout is used to represent the ordinate; the abscissa represents time, generally denoted by T, and in fig. 6, T-sel in the abscissa represents time corresponding to a preset number threshold value related to the number of rotations of the motor, that is, time when the number of rotations of the motor reaches the preset number threshold value; d-start refers to the value of Dout corresponding to the first duty cycle signal D_start < N:1 >. Before the time T-sel, the first multiplexer 30 selects and outputs the first duty signal d_start < N:1>, and since the first duty signal d_start < N:1> is a fixed value, the duty ratio Dout of the second pulse width modulation signal PWMout is also a fixed value D-start; after reaching the time T-sel, the first multiplexer 30 selects and outputs the second duty signal DIN < N:1>, at which time the duty ratio Dout of the second pulse width modulation signal PWMout will be converted from the fixed value D-start to the duty ratio of the second pulse width modulation signal PWMout corresponding to the second duty signal DIN < N:1 >.
A schematic diagram of the variation of the duty cycle Dout of the second pulse width modulated signal PWMout at two different values of the second duty cycle signal DIN < N:1> is shown in fig. 6. The embodiment Din1 shown in fig. 6 refers to the duty ratio of the second pulse width modulation signal PWMout corresponding to the second duty ratio signal Din < N:1> having the first value; din2 refers to the duty cycle of the corresponding second pulse width modulation signal PWMout when the second duty cycle signal Din < N:1> is the second value. The period of the clock signal CLK is up-counted or down-counted by the digitally controllable adder-subtractor 50, and the duty ratio Dout of the second pulse width modulation signal PWMout rises with a rising slope k1 or falls with a falling slope k2, so that the duty ratio Dout of the second pulse width modulation signal PWMout does not abrupt but approaches Din1 and Din2 from a fixed value D-start with a fixed slope. Specifically, when the first value of the second duty signal DIN < N:1> is greater than the value of the first duty signal D_start < N:1>, D-start rises with a slope k1 until it is equal to Din1; when the second value of the second duty cycle signal DIN < N:1> is less than the value of the first duty cycle signal D_start < N:1>, D-start decreases with a slope k2 until Din is equal.
In one embodiment, the slopes k1 and k2 may be slopes with equal absolute values, or may have respective changing speeds, which is specific to the actual use situation, and the embodiment of the present invention is not limited thereto. Further, as can be seen from the partial enlarged graph of the curve of the rising phase of the duty cycle Dout shown in fig. 6, the value of the slope k1 is related to the count step lsb set inside the digitally controllable adder-subtractor 50, and also to the frequency f of the clock signal CLK it receives. In one embodiment, the larger the count step lsb, the larger the slope k1, with the frequency f unchanged; the smaller the count step lsb, the smaller the slope k 1. In one embodiment, the larger the frequency f, the larger the slope k1, with the count step lsb unchanged; the smaller the frequency f, the smaller the slope k 1. The relationship of the slope k2 and the count step lsb to the frequency f is similar to k1 and will not be described again here. It will be appreciated that the step size lsb herein is related to the default count value received at the second input of the digitally controllable adder-subtractor 50 as previously described. In one embodiment, the larger the default count value, the longer the step size. Specifically, the overall strategy of the motor soft start process is described below in conjunction with the start-up circuit provided by the foregoing embodiments and as shown in fig. 6.
When the motor starts to start, the second pulse width modulation signal PWMout drives the motor at a preset constant duty ratio D-start, meanwhile, the period of the Hall periodic signal Hlogic of the Hall sensor is counted, and after the motor rotation designated period is detected, namely, the motor rotation frequency reaches the frequency threshold, the starting circuit controls the duty ratio of the second pulse width modulation signal PWMout to be close to the duty ratio represented by the second duty ratio signal DIN < N:1> at a certain slope. In one embodiment, the second duty cycle signal DIN < N:1> characterizes the duty cycle of the first pulse width modulated signal PWMin. It will be appreciated that in the disclosed embodiment of the invention, the duty cycle Dout of the second pwm signal PWMout is proportional to the duty cycle of the first pwm signal PWMin after the motor is started and smoothly transitions to the corresponding rotational speed given by the duty cycle of the first pwm signal PWMin, i.e., after the time T-step is reached. Specifically, when the duty ratio of the first pulse width modulation signal PWMin is greater than the value of the first duty ratio signal d_start < N:1>, the digitally controllable adder-subtractor 50 will count up, and the duty ratio Dout of the second pulse width modulation signal PWMout rises from D-start to Din1 with a slope k 1; when the duty cycle of the first pulse width modulation signal PWMin is smaller than the value of the first duty cycle signal d_start < N:1>, the digitally controllable adder-subtractor 50 will perform a down-count, and the duty cycle Dout of the second pulse width modulation signal PWMout drops from D-start to Din2 with a slope k 2. Through the strategy, the motor can be ensured to be started normally, meanwhile, the current of the motor can be increased or reduced gradually, the risk of rising of input voltage caused by current overshoot during phase change of the motor is reduced, and the service efficiency and service life of the motor are further ensured.
Further, on the basis of the above embodiment, the embodiment of the present invention further provides a method for driving a brushless dc motor, as shown in a flowchart of a method for driving a brushless dc motor in fig. 7, which includes the following steps S702, S704 and S706.
In step S702, the driving motor rotates at a preset constant rotation speed, wherein the constant rotation speed is determined by a preset first duty ratio signal d_start < N:1 >.
In step S704, the number of motor rotations is recorded, and when the number of motor rotations reaches a preset number threshold, the magnitudes of the second duty cycle signal DIN < N:1> and the preset first duty cycle signal D_start < N:1> are determined.
Wherein the rotational speed of the motor can be varied by varying the value of the second duty cycle signal DIN < N:1 >. In one embodiment, the second duty cycle signal DIN < N:1> characterizes the duty cycle of the first pulse width modulated signal PWMin provided by the microprocessor.
Step S706, when the second duty cycle signal DIN < N:1> is smaller than the first duty cycle signal D_start < N:1>, the motor rotation speed is controlled to be gradually reduced until the rotation speed is equal to the motor rotation speed value corresponding to the second duty cycle signal DIN < N:1 >; and when the second duty ratio signal DIN < N:1> is larger than the first duty ratio signal D_start < N:1>, controlling the motor rotation speed to be gradually increased until the rotation speed is equal to a motor rotation speed value corresponding to the second duty ratio signal DIN < N:1 >.
The driving device and the driving method of the brushless direct current motor provided by the embodiment of the invention have the same technical characteristics as the starting circuit for the brushless direct current motor system provided by the embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
It will be clear to those skilled in the art that, for convenience and brevity of description, the specific working procedures of the driving apparatus and the driving method described above may refer to the corresponding procedures in the foregoing method embodiments, which are not repeated here.
In addition, in the description of embodiments of the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood by those skilled in the art in specific cases.
In the description of the present invention, it should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention for illustrating the technical solution of the present invention, but not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the foregoing examples, it will be understood by those skilled in the art that the present invention is not limited thereto: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. The utility model provides a starting circuit of brushless DC motor, its characterized in that is applied to brushless DC motor system, starting circuit includes counter, first multiplexer, digital comparator, digital controllable adder-subtractor and conversion control circuit, wherein:
the counter is used for recording the rotation times of the motor and outputting a first counting signal representing the rotation times of the motor;
The first multiplexer comprises a first input end, a second input end, a control end and an output end; the first input end of the first multiplexer is used for receiving a first duty cycle signal, and the first duty cycle signal represents a preset fixed duty cycle; the second input end of the first multiplexer is used for receiving a second duty cycle signal, and the second duty cycle signal represents the duty cycle of the first pulse width modulation signal; the control end of the first multiplexer is used for receiving the first counting signal; the first multiplexer is used for selecting to output a first duty cycle signal or a second duty cycle signal at the output end according to the value of the first counting signal; when the rotation times of the motor are smaller than a preset time threshold, the first multiplexer selects to output a first duty ratio signal at the output end of the first multiplexer; when the rotation times of the motor reach a preset time threshold, the first multiplexer selects to output a second duty ratio signal at the output end of the first multiplexer;
the digital comparator comprises a first input end, a second input end and an output end; the first input end of the digital comparator is connected with the output end of the first multiplexer, and the second input end of the digital comparator is connected with the output end of the digital controllable adder-subtractor; the digital comparator is used for comparing the signal output by the output end of the first multiplexer with the second counting signal output by the digital controllable adder-subtractor and generating an addition-subtraction control signal;
The second multiplexer comprises a first input end, a second input end, a control end and an output end; a first input end of the second multiplexer receives a first clock signal, and a second input end of the second multiplexer receives a second clock signal; the control end of the second multiplexer receives the first counting signal; the second multiplexer is used for selecting whether the first clock signal or the second clock signal is output at the output end of the second multiplexer as the clock signal according to the value of the first counting signal;
the digital controllable adder-subtractor is provided with an input end, a control end and an output end, wherein the input end of the digital controllable adder-subtractor receives the clock signal, the control end of the digital controllable adder-subtractor receives the addition-subtraction control signal, the addition-subtraction control signal controls the digital controllable adder-subtractor to carry out addition counting or subtraction counting on the period of the clock signal, and the output end outputs the second counting signal; and
the conversion control circuit is used for receiving a second counting signal and generating a second pulse width modulation signal according to the second counting signal, and the second pulse width modulation signal is used for controlling the on and off time of a power switch in the direct current brushless motor system so as to control the rotating speed of the motor.
2. The starting circuit according to claim 1, wherein,
when the signal output by the output end of the first multiplexer is larger than the second counting signal, the addition and subtraction control signal controls the digital controllable adder-subtractor to carry out addition counting on the period of the clock signal; and
and when the signal output by the output end of the first multiplexer is smaller than the second counting signal, the addition and subtraction control signal controls the digital controllable adder-subtractor to count down the period of the clock signal.
3. The startup circuit of claim 1, wherein the digitally controllable adder-subtractor further comprises a second input for receiving a default count value, the digitally controllable adder-subtractor adding one to the value of the second count signal after each count of cycles of the clock signal to the default count value.
4. The start-up circuit of claim 1, wherein the second multiplexer selects to output the first clock signal at its output when the number of motor revolutions is less than a preset number threshold; when the rotation times of the motor reach a preset time threshold, the second multiplexer selects to output a second clock signal at the output end of the second multiplexer; wherein the frequency of the first clock signal is greater than the frequency of the second clock signal.
5. The startup circuit of claim 1, further comprising:
and the duty ratio coding circuit is used for receiving the first pulse width modulation signal and converting the duty ratio information of the first pulse width modulation signal into a corresponding second duty ratio signal.
6. The startup circuit of claim 1, wherein the first pulse width modulated signal is provided by a microprocessor.
7. The startup circuit of claim 1, wherein the switching control circuit comprises:
the analog-to-digital converter is used for receiving the second counting signal and converting the second counting signal into an equivalent analog voltage signal;
a triangular wave generator for generating a triangular wave signal;
the analog comparator comprises a first input end, a second input end and an output end, wherein the first input end of the analog comparator receives the equivalent analog voltage signal; a second input end of the analog comparator receives the triangular wave signal; the analog comparator is used for comparing the equivalent analog voltage signal with the triangular wave signal to generate the second pulse width modulation signal.
8. The startup circuit of claim 1, wherein the counter receives the hall period signal output by the hall sensor and counts the period of the hall period signal and generates a first count signal that characterizes a period count value of the hall period signal.
9. A drive apparatus for a dc brushless motor, comprising:
the start-up circuit of any one of claims 1-8, configured to generate a second pulse width modulated signal;
the Hall sensor senses the rotation position of the motor and generates a Hall periodic signal; and
and the driving circuit is connected with the starting circuit, receives the Hall periodic signal and the second pulse width modulation signal, and generates a driving signal according to the Hall periodic signal and the second pulse width modulation signal, and the driving signal is used for driving the on and off of a power switch in the direct current brushless motor system.
10. A method of driving a dc brushless motor, comprising:
the driving motor rotates at a preset constant rotating speed, wherein the constant rotating speed is determined by a preset first duty ratio signal;
counting up the period of the first clock signal by adopting a digital controllable adder-subtractor and outputting a counting signal, wherein the counting is stopped until the value of the counting signal is equal to the value representing the first duty cycle signal;
recording the rotation times of a motor, and judging the magnitude of a second duty ratio signal and the magnitude of a preset first duty ratio signal when the rotation times of the motor reach a preset time threshold value, wherein the rotation speed of the motor is changed by changing the value of the second duty ratio signal; when the second duty ratio signal is smaller than the first duty ratio signal, adopting the digital controllable adder-subtractor to count down the period of the second clock signal, and outputting the count signal until the value of the count signal is equal to the value representing the second duty ratio signal;
When the second duty ratio signal is larger than the first duty ratio signal, adopting the digital controllable adder-subtractor to count up the period of the second clock signal, and outputting the counting signal until the value of the counting signal is equal to the value representing the second duty ratio signal; and
and generating a pulse width modulation signal according to the counting signal, wherein the pulse width modulation signal is used for controlling the on and off time of a power switch in the DC brushless motor system so as to control the rotating speed of the motor.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07194173A (en) * | 1993-12-28 | 1995-07-28 | Hitachi Ltd | Fan motor |
| JP2002238285A (en) * | 2001-02-09 | 2002-08-23 | Sanyo Electric Co Ltd | Soft start circuit of brushless motor |
| CN1794558A (en) * | 2004-12-21 | 2006-06-28 | 三星电子株式会社 | Device and method for starting brushless direct current motor |
| CN101124719A (en) * | 2005-02-18 | 2008-02-13 | 爱特梅尔股份有限公司 | Sensorless control of two-phase brushless DC motor |
| CN101361260A (en) * | 2006-08-30 | 2009-02-04 | 罗姆股份有限公司 | Motor drive circuit, drive method, and motor unit and electronic device using the motor unit |
| CN101908853A (en) * | 2009-06-08 | 2010-12-08 | 罗姆股份有限公司 | The drive circuit of motor and driving method |
| CN105846732A (en) * | 2016-05-27 | 2016-08-10 | 上海路虹电子科技有限公司 | Control circuit |
| CN110323977A (en) * | 2018-03-30 | 2019-10-11 | 日本电产伺服有限公司 | Motor unit |
| CN110365261A (en) * | 2019-07-08 | 2019-10-22 | 江苏科技大学 | The smooth method for starting-controlling of brshless DC motor and control system |
| CN114531067A (en) * | 2022-03-03 | 2022-05-24 | 潘兆铿 | Speed regulation structure and speed regulation method of single-phase brushless direct current motor |
| CN116388615A (en) * | 2023-06-03 | 2023-07-04 | 晶艺半导体有限公司 | Direct-current brushless motor broken line speed regulation control circuit and method |
-
2023
- 2023-11-28 CN CN202311597199.6A patent/CN117318543B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07194173A (en) * | 1993-12-28 | 1995-07-28 | Hitachi Ltd | Fan motor |
| JP2002238285A (en) * | 2001-02-09 | 2002-08-23 | Sanyo Electric Co Ltd | Soft start circuit of brushless motor |
| CN1794558A (en) * | 2004-12-21 | 2006-06-28 | 三星电子株式会社 | Device and method for starting brushless direct current motor |
| CN101124719A (en) * | 2005-02-18 | 2008-02-13 | 爱特梅尔股份有限公司 | Sensorless control of two-phase brushless DC motor |
| CN101361260A (en) * | 2006-08-30 | 2009-02-04 | 罗姆股份有限公司 | Motor drive circuit, drive method, and motor unit and electronic device using the motor unit |
| CN101908853A (en) * | 2009-06-08 | 2010-12-08 | 罗姆股份有限公司 | The drive circuit of motor and driving method |
| CN105846732A (en) * | 2016-05-27 | 2016-08-10 | 上海路虹电子科技有限公司 | Control circuit |
| CN110323977A (en) * | 2018-03-30 | 2019-10-11 | 日本电产伺服有限公司 | Motor unit |
| CN110365261A (en) * | 2019-07-08 | 2019-10-22 | 江苏科技大学 | The smooth method for starting-controlling of brshless DC motor and control system |
| CN114531067A (en) * | 2022-03-03 | 2022-05-24 | 潘兆铿 | Speed regulation structure and speed regulation method of single-phase brushless direct current motor |
| CN116388615A (en) * | 2023-06-03 | 2023-07-04 | 晶艺半导体有限公司 | Direct-current brushless motor broken line speed regulation control circuit and method |
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