CN117317798B - Integrated common-p type Peltier refrigeration high-power FP laser chip and preparation method thereof - Google Patents
Integrated common-p type Peltier refrigeration high-power FP laser chip and preparation method thereof Download PDFInfo
- Publication number
- CN117317798B CN117317798B CN202311595515.6A CN202311595515A CN117317798B CN 117317798 B CN117317798 B CN 117317798B CN 202311595515 A CN202311595515 A CN 202311595515A CN 117317798 B CN117317798 B CN 117317798B
- Authority
- CN
- China
- Prior art keywords
- layer
- laser chip
- metal electrode
- ridge waveguide
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005057 refrigeration Methods 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 103
- 239000002184 metal Substances 0.000 claims abstract description 103
- 239000004065 semiconductor Substances 0.000 claims abstract description 102
- 238000002161 passivation Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000011248 coating agent Substances 0.000 claims abstract description 3
- 238000000576 coating method Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 229910005542 GaSb Inorganic materials 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims 1
- 229910002704 AlGaN Inorganic materials 0.000 description 11
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 11
- 230000005679 Peltier effect Effects 0.000 description 9
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- 235000005811 Viola adunca Nutrition 0.000 description 1
- 240000009038 Viola odorata Species 0.000 description 1
- 235000013487 Viola odorata Nutrition 0.000 description 1
- 235000002254 Viola papilionacea Nutrition 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000026058 directional locomotion Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 150000002739 metals Chemical group 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000005676 thermoelectric effect Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/024—Arrangements for thermal management
- H01S5/02407—Active cooling, e.g. the laser temperature is controlled by a thermo-electric cooler or water cooling
- H01S5/02415—Active cooling, e.g. the laser temperature is controlled by a thermo-electric cooler or water cooling by using a thermo-electric cooler [TEC], e.g. Peltier element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/024—Arrangements for thermal management
- H01S5/02461—Structure or details of the laser chip to manipulate the heat flow, e.g. passive layers in the chip with a low heat conductivity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/2202—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure by making a groove in the upper laser structure
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Geometry (AREA)
- Semiconductor Lasers (AREA)
Abstract
The application relates to the technical field of semiconductor laser chips, in particular to an integrated co-P type Peltier refrigeration high-power FP laser chip and a preparation method thereof, wherein the laser chip comprises a substrate layer, a lower limiting layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper limiting layer and a ridge waveguide layer which are sequentially arranged along an epitaxial growth direction from bottom to top, a cathode electrode is arranged below the substrate layer, one side of the ridge waveguide layer is of a step-shaped structure, the laser chip is provided with a groove-shaped structure, the groove-shaped structure penetrates through the ridge waveguide layer, the upper limiting layer, the upper waveguide layer and the quantum well active layer from top to bottom, and the groove-shaped structure separates the ridge waveguide layer into a ridge waveguide and a P-type semiconductor; the laser chip is also provided with a passivation layer coating the periphery of the laser chip. The laser chip also comprises a metal electrode, and the quantum well active layer is rapidly radiated by utilizing the Peltier principle through the N-type semiconductor, the P-type semiconductor and the metal electrode.
Description
Technical Field
The application relates to the technical field of semiconductor laser chips, in particular to an integrated p-type Peltier refrigerating integrated high-power FP laser chip and a preparation method thereof.
Background
Because of the advantages of high-power semiconductor laser chips, FP high-power semiconductor laser chips have been widely used in many fields such as production and processing, laser communication, medical cosmetology, automatic control, and military weapons. In view of the wide application prospect of the FP high-power semiconductor laser chip, various countries are accelerated to implement the development plan of the high-power semiconductor laser chip technology, and the high-power semiconductor laser chip industry is laid out, so that the FP semiconductor laser chip and related industries thereof are rapidly developed.
As shown in fig. 1, currently mainstream FP semiconductor laser chips include a blue-violet laser chip using InGaN/GaN as an active region and an ultraviolet/deep-ultraviolet laser chip using AlGaN/GaN as an active region. The laser chip of whatever material and structure aims at reducing transverse current, improving reliability and current injection uniformity, reducing the temperature of an active region and improving device power. For this reason, researchers have conducted a series of studies. For example, chinese patent No. CN109103746a discloses a semiconductor laser chip including a substrate layer and a p-type electron flood prevention layer between an active region layer and a p-type cladding layer, and further including a p-type strain layer (p-type AlzIn1-zAs layer, where z > x) having a large band gap between the p-type electron flood prevention layer (p-type AlxIn1-xAs layer) and the p-type cladding layer. Chinese patent No. CN107112409B discloses a peltier cooling element and a method for manufacturing the same, in which a thermoelectric cooler TEC (containing a temperature sensitive material, commonly referred to as a peltier effect, also referred to as a thermo-electric effect) is provided on a base of a tunable laser chip during a semiconductor laser chip manufacturing process. The Chinese patent No. CN116417898B discloses a high-power FP laser chip integrated with Peltier refrigeration, and a Peltier cooling element is integrated at the laser chip end of a laser, so that the problem of heat dissipation of an active area of the laser chip is better solved.
However, the inventor of the present application has found in long-term research and development that NP semiconductor materials exist in the existing laser chip structure, but in the above-mentioned peltier related patents, all the peltier NP materials used are from other materials, which requires more complicated processes, and also requires more materials to be deposited, and are usually polycrystalline semiconductor materials, and multiple interfaces affect the thermal distribution of the whole device, so that the efficiency of the laser chip is reduced and the reliability is lowered.
Disclosure of Invention
In order to solve the problems, the invention provides an integrated p-type Peltier refrigeration integrated high-power FP laser chip and a preparation method thereof.
In a first aspect, the present application provides an integrated co-P type peltier refrigeration high-power FP laser chip, where the laser chip includes a substrate layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer and a ridge waveguide layer sequentially disposed along an epitaxial growth direction from bottom to top, a cathode electrode is disposed below the substrate layer, an anode electrode is disposed above the ridge waveguide layer, the ridge waveguide layer is disposed above the upper confinement layer, one side of the ridge waveguide layer is in a step structure, the laser chip is provided with a groove-like structure, and the groove-like structure penetrates through the ridge waveguide layer, the upper confinement layer, the upper waveguide layer and the quantum well active layer from top to bottom, and the groove-like structure separates the ridge waveguide layer into a ridge waveguide and a P-type semiconductor; the laser chip is also provided with a passivation layer coating the periphery of the laser chip, and the laser chip further comprises:
the N-type semiconductor is arranged on the passivation layer corresponding to the step-shaped structure;
the metal electrode comprises a cold end metal electrode, a P side hot end metal electrode and an N side hot end metal electrode, wherein the cold end metal electrode is arranged on the surface of the passivation layer on the anode electrode, extends from the surface of the passivation layer on the anode electrode to the step-shaped structures and the groove-shaped structures on two sides so as to cover the anode electrode, the ridge waveguide, one side of the N type semiconductor, which is close to the ridge waveguide, and one side of the P type semiconductor, which is close to the ridge waveguide, and fills the groove-shaped structures; the N-side hot-end metal electrode is arranged on the upper surface of the N-type semiconductor, the P-side hot-end metal electrode is arranged on the upper surface of the P-type semiconductor, and the cold-end metal electrode, the P-side hot-end metal electrode and the N-side hot-end metal electrode are separated from each other.
In one possible implementation, the N-side hot-side metal electrode is disposed on a side of an upper surface of the N-type semiconductor away from the ridge waveguide, and the P-side hot-side metal electrode is disposed on a side of an upper surface of the P-type semiconductor away from the ridge waveguide.
In one possible implementation, the laser chip further includes a reflective film and an anti-reflection film, the reflective film is coated on a rear end face of the laser chip, and the anti-reflection film is coated on a front end face of the laser chip.
In one possible implementation, the material of the P-type semiconductor is antimonide.
In one possible implementation, the material of the N-type semiconductor is ITO, the material of the P-type semiconductor is GaSb, and the material of the metal electrode is Al, au, or Ag.
In a second aspect, the present application provides a method for preparing an FP laser chip integrated with peltier refrigeration, including the following steps:
obtaining a semi-finished laser chip;
forming a step-shaped structure and a preliminary groove-shaped structure, photoetching a ridge waveguide layer to form a ridge waveguide and a P-type semiconductor, wherein one side of the ridge waveguide is formed into the step-shaped structure, and the other side of the ridge waveguide is formed into the preliminary groove-shaped structure;
forming a groove-shaped structure, photoetching a position corresponding to the preliminary groove-shaped structure in the laser chip to form a groove-shaped structure, wherein the groove-shaped structure penetrates through the quantum well active layer;
forming an anode electrode and a cathode electrode, wherein the anode electrode is arranged above the ridge waveguide, and the cathode electrode is arranged below the substrate layer;
forming a passivation layer on two sides of the laser chip, the step-shaped structures, the upper surface of the ridge waveguide and the groove-shaped structures;
forming an N-type semiconductor which is arranged on the passivation layer corresponding to the step-shaped structure;
forming a metal electrode, forming an N-side hot-end metal electrode on the N-type semiconductor by a photoetching technology, forming a P-side hot-end metal electrode on the P-type semiconductor, forming a cold-end metal electrode on the surface of a passivation layer on the anode electrode, wherein the cold-end metal electrode, the P-side hot-end metal electrode and the N-side hot-end metal electrode are separated from each other, and the cold-end metal electrode extends from the surface of the passivation layer on the anode electrode to the step-shaped structures and the groove-shaped structures on two sides so as to cover the anode electrode, the ridge waveguide layer, one side of the N-type semiconductor, which is close to the ridge waveguide layer, and one side of the P-type semiconductor, which is close to the ridge waveguide layer, and filling the groove-shaped structures.
In one possible implementation, the step of obtaining the semi-finished laser chip includes:
and growing a lower limiting layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper limiting layer and a ridge waveguide layer on the substrate layer sequentially from bottom to top.
In one possible implementation, the step of forming the metal electrode further includes the steps of:
a reflecting film and an antireflection film are formed, the rear end face of the laser chip is coated with the reflecting film, and the front end face of the laser chip is coated with the antireflection film.
The beneficial effects of this application are:
according to the invention, through the arrangement of the N-type semiconductor, the P-type semiconductor and the metal electrode, the Peltier effect is utilized to realize rapid heat dissipation of the quantum well active layer, so that the efficiency of the laser chip is improved, and the reliability and the photoelectric efficiency of the laser chip are enhanced. Meanwhile, the p-type semiconductor is directly used as a hot end, so that the process step of redeposition of other p-type materials is omitted; and this patent is in P type one side, through the recess isolation structure that gets deep into the quantum well below, utilizes PNP type structure to fine messenger's Peltier device's P type keeps apart with the P type of laser instrument, reaches compact integrated effect.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of a conventional laser chip described in the background of the present application.
Fig. 2 is a schematic cross-sectional structure diagram of an integrated co-p type peltier refrigeration high-power FP laser chip of the present application.
Fig. 3 is a schematic top view structure of an integrated co-p type peltier refrigeration high-power FP laser chip of the present application.
Fig. 4 is a flowchart of the preparation of an integrated co-p type peltier refrigeration high-power FP laser chip of the present application.
Fig. 5 is a schematic cross-sectional structure of a semi-finished laser chip of the present application.
FIG. 6 is a schematic cross-sectional view of a step structure and a preliminary groove structure formed in the step of the present application.
FIG. 7 is a schematic cross-sectional view of a step of forming a groove-like structure.
Fig. 8 is a schematic cross-sectional structure of a passivation layer formed in the step of the present application.
Description of main reference numerals:
101. a substrate layer; 102. a lower confinement layer; 103. a lower waveguide layer; 104. a quantum well active layer; 105. an upper waveguide layer; 106. an upper confinement layer; 107. a ridge waveguide; 108. a cathode electrode; 109. an anode electrode; 110. a passivation layer; 111. a cold end metal electrode; 112. a P-type semiconductor; 113. an N-type semiconductor; 114. a reflective film; 115. an antireflection film; 116. a front end face; 117. a rear end face; 118. a P-side hot-end metal electrode; 119. an N-side hot-end metal electrode; 120. a ridge waveguide layer; 121. a step-like structure; 122. a groove-like structure; 123. preliminary groove-like structure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments, and all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort based on the embodiments in the present application are all within the scope of protection of the present application.
It should be noted that "-", "" should be understood to include numerical values of endpoints thereof, for example, a certain value is 1 to 10, the numerical value is 1 or more and 10 or less, and the numerical value is 1 to 10, the numerical value is 1 or more and 10 or less.
Referring to fig. 2 and 3, the embodiment of the present application provides an integrated co-p type peltier refrigeration high-power FP laser chip, which includes a substrate layer 101, a lower confinement layer 102, a lower waveguide layer 103, a quantum well active layer 104, an upper waveguide layer 105, an upper confinement layer 106 and a ridge waveguide layer 120 sequentially disposed along an epitaxial growth direction from bottom to top, a cathode electrode 108 disposed below the substrate layer 101, an anode electrode 109 disposed above the ridge waveguide layer 120, the ridge waveguide layer 120 disposed above the upper confinement layer 106, and a step-like structure 121 disposed on one side of the ridge waveguide layer 120. The laser chip is provided with a groove-shaped structure 122, the groove-shaped structure 122 penetrates through the ridge waveguide layer 120, the upper limiting layer 106, the upper waveguide layer 105 and the quantum well active layer 104 from top to bottom, the groove-shaped structure 122 separates the ridge waveguide layer 120 into a ridge waveguide 107 and a P-type semiconductor 112, a passivation layer 110 wrapping the periphery of the laser chip is arranged on the periphery of the laser chip, an N-type semiconductor 113 is arranged on the surface of the passivation layer 110 above the step-shaped structure 121 on one side of the laser chip, and metal electrodes are arranged on the surface of the passivation layer 110, the upper surface of the N-type semiconductor 113 and the upper surface of the P-type semiconductor 112 on the anode electrode 109 to achieve the peltier effect.
Alternatively, as shown in fig. 2 and 3, the width of the ridge waveguide 107 is smaller than the width of the upper confinement layer 106 in the X-axis direction, so that one side of the ridge waveguide 107 forms a stepped structure 121, and the stepped structure 121 is a structure in which the side wall of the ridge waveguide layer 120 and the upper surface of the upper confinement layer 106 are formed together.
Alternatively, as shown in fig. 2 and 3, the groove-like structure 122 is a structure formed by the sidewalls of the lower waveguide layer 103, the upper surface of the lower waveguide layer 103, the sidewalls of the quantum well active layer 104, the sidewalls of the upper waveguide layer 105, the sidewalls of the upper confinement layer 106, the sidewalls of the ridge waveguide 107, and the P-type semiconductor 112 together.
The metal electrodes refer to metals and/or metal groups arranged in the laser chip for realizing the peltier effect, the metal electrodes include a cold end metal electrode 111, a P side hot end metal electrode 118 and an N side hot end metal electrode 119, wherein the cold end metal electrode 111 is arranged on the surface of the passivation layer 110 on the anode electrode 109, the cold end metal electrode 111 extends from the surface of the passivation layer 110 on the anode electrode 109 to the step-shaped structure 121 and the groove-shaped structure 122 on both sides so as to cover the anode electrode 109, the ridge waveguide 107, one side of the N-type semiconductor 113 close to the ridge waveguide layer 120, and one side of the P-type semiconductor 112 close to the ridge waveguide 107, and fill the groove-shaped structure 122. The N-side hot-side metal electrode 119 is disposed on the upper surface of the N-type semiconductor 113, the P-side hot-side metal electrode 118 is disposed on the upper surface of the P-type semiconductor 112, and the cold-side metal electrode 111, the P-side hot-side metal electrode 118, and the N-side hot-side metal electrode 119 are separated from each other.
Continuing with the description of fig. 2 and 3, during operation of the laser chip, positive charges are applied to the N-side hot-side metal electrode 119, and negative charges are applied to the P-side hot-side metal electrode 118, so that directional movement of electrons is generated, and the temperature of the cold-side metal electrode 111 is reduced, and the temperatures of the P-side hot-side metal electrode 118 and the N-side hot-side metal electrode 119 are increased by the peltier effect.
Further, the temperature of the cold-end metal electrode 111 is reduced, that is, the cold-end metal electrode 111 is a cold end in the peltier effect, so that the heat of the ridge waveguide 107 is transferred to the cold-end metal electrode 111, that is, the temperature of the ridge waveguide layer 120 is reduced, and the temperature of the quantum well active layer 104 is further reduced. The temperatures of the P-side hot-end metal electrode 118 and the N-side hot-end metal electrode 119 are increased, namely the P-side hot-end metal electrode 118 and the N-side hot-end metal electrode 119 are hot ends in the peltier effect, so that the temperatures of the P-type semiconductor 112 and the N-type semiconductor 113 below the P-side hot-end metal electrode 118 and the N-side hot-end metal electrode 119 are increased, the temperature balance of the laser chip is realized, the average velocity of carriers is increased, the concentration of the carriers is increased, the resistance of the device is reduced, and the reliability and the photoelectric efficiency of the device are enhanced.
The Peltier effect is a phenomenon that when current passes through loops formed by different conductors, heat absorption and heat release phenomena respectively occur at joints of the different conductors along with different current directions, and further, electrons move directionally under the action of an external electric field, so that a part of energy is brought to the other end of the electric field.
For example: the N-type semiconductor 113 and the N-side hot-end metal electrode 119 are different conductors, the P-type semiconductor 112 and the P-side hot-end metal electrode 118 are different conductors, the N-side hot-end metal electrode 119 is positively charged, and the P-side hot-end metal electrode 118 is negatively charged, so that the N-side hot-end metal electrode 119, the N-type semiconductor 113, the cold-end metal electrode 111, the P-side hot-end metal electrode 118 and the P-type semiconductor 112 form a loop, and a peltier effect is generated.
In addition, a material such as a ceramic plate may be disposed on the cold end metal electrode 111 to enhance the heat dissipation effect, which is not described herein.
In some embodiments, the N-side hot-side metal electrode 119 is disposed on a side of the upper surface of the N-type semiconductor 113 away from the ridge waveguide layer 120, and the P-side hot-side metal electrode 118 is disposed on a side of the upper surface of the P-type semiconductor 112 away from the ridge waveguide layer 120.
In some embodiments, the material of P-type semiconductor 112 is antimonide. Optionally, the material of the P-type semiconductor 112 is GaSb. It is understood that the material of the P-type semiconductor 112 is not limited to GaSb, but may be other semiconductor materials such as GaAs, gaN, and the like.
In some embodiments, the material of the N-type semiconductor 113 is ITO, and the material of the metal electrode is Al, au, or Ag. That is, the materials of the cold side metal electrode 111, the P side hot side metal electrode 118, and the N side hot side metal electrode 119 are Al, au, or Ag.
In some embodiments, the laser chip has a front end surface 116 and a rear end surface 117, the front end surface 116 and the rear end surface 117 are disposed at intervals along the Y-axis direction, the laser chip further includes a reflective film 114 and an antireflection film 115, the reflective film 114 is plated on the rear end surface 117, and the antireflection film 115 is plated on the front end surface 116.
In some embodiments, the substrate layer 101 may be made of a semiconductor material such as GaAs or GaN, and has a thickness of 200nm; the lower confinement layer 102 may be made of semiconductor material such as AlGaAs or AlGaN, and has a thickness of 300nm; the lower waveguide layer 103 may be made of semiconductor material such as AlGaAs or AlGaN, and has a thickness of 0.5-3 μm; the quantum well active layer 104 is a well layer and a barrier layer which alternately grow, wherein the materials of the well layer and the barrier layer can be semiconductor materials such as AlGaAs or AlGaN, and the thickness is 0.1 μm; the upper waveguide layer 105 may be made of AlGaAs and has a thickness of 0.1-3 μm; the upper confinement layer 106 may be made of semiconductor material such as AlGaAs or AlGaN, and has a thickness of 0.3 μm; the ridge waveguide layer 120 may be made of semiconductor material such as GaAs, gaN, or GaSb, and has a thickness of 0.3 μm; the passivation layer 110 may be formed of SiO2 with a thickness of 50nm. The cathode electrode 108 and the anode electrode 109 are made of Cr/Au, ti/Au or Ni/Au. The reflectivity of the reflective film 114 is 50% -100%, and the reflectivity of the anti-reflection film 115 is less than or equal to 10%, and it is understood that the materials and thicknesses of the layers may be selected according to practical situations, and will not be described herein.
Referring to fig. 4, the embodiment of the application further provides a method for preparing an integrated p-type peltier refrigeration high-power FP laser chip, which includes the following steps:
referring to fig. 5, s1, a semi-finished laser chip is obtained. The semi-finished laser chip includes a lower confinement layer 102, a lower waveguide layer 103, a quantum well active layer 104, an upper waveguide layer 105, an upper confinement layer 106, and a ridge waveguide layer 120.
Referring to fig. 6, s2, a step-shaped structure 121 and a preliminary groove-shaped structure 123 are formed, the ridge waveguide layer 120 is etched by photolithography to form a ridge waveguide 107 and a P-type semiconductor 112, the step-shaped structure 121 is formed on one side of the ridge waveguide 107, and the preliminary groove-shaped structure 123 is formed on the other side of the ridge waveguide 107.
The photolithographic ridge waveguide layer 120 may be etched by dry etching to a depth of 300nm such that the height of the ridge waveguide 107 in the Z-axis direction is 300nm, one side of the ridge waveguide 107 forming a stepped structure 121 and the other side forming a preliminary groove-like structure 123.
Referring to fig. 7 s3, a groove-shaped structure 122 is formed, and a position corresponding to the preliminary groove-shaped structure 123 in the laser chip is etched to form the groove-shaped structure 122, wherein the groove-shaped structure 122 penetrates through the quantum well active layer 104;
the bottom of the preliminary groove-like structure 123, i.e., the position corresponding to the preliminary groove-like structure 123 in the upper surface of the upper confinement layer 106 is etched by dry etching to an etching depth of 400nm to 4400nm to form the groove-like structure 122, i.e., the groove-like structure 122 has a depth of 700nm to 4700nm. The groove-like structure 122 penetrates the upper confinement layer 106, the upper waveguide layer 105, and the quantum well active layer 104, and is partially located in the lower waveguide layer 103.
Referring to fig. 8, s4, an anode electrode 109 and a cathode electrode 108 are formed, the anode electrode 109 is disposed above the ridge waveguide 107, and the cathode electrode 108 is disposed below the substrate layer 101; optionally, the cathode electrode 108, the anode electrode 109 are fabricated using photolithographic techniques and e-beam evaporation processes.
S5, forming passivation layers 110, and forming passivation layers 110 on two sides of the laser chip, the step-shaped structures 121, the side surfaces of the ridge waveguide 107, the surface of the anode electrode 109 and the groove-shaped structures 122.
Alternatively, the passivation layer 110 having a thickness of 50nm is deposited using PECVD, and the passivation layer 110 may use SiO material. The passivation layer 110 may be partially formed on the upper surface of the P-type semiconductor 112, or the passivation layer 110 may not be formed, as long as the P-side hot-side metal electrode 118 can be contacted and a conductive circuit can be formed. In addition, it is also necessary to remove a portion of the passivation layer 110 on the anode electrode 109 using a BOE etching solution to obtain a remaining passivation layer 110 and an electric injection window.
S6, forming an N-type semiconductor 113, wherein the N-type semiconductor 113 is arranged on the passivation layer 110 corresponding to the step-shaped structure 121;
an N-type semiconductor 113 is formed in the passivation layer 110 of the upper confinement layer 106 by a photolithography technique and an electron beam evaporation plating technique, the N-type semiconductor 113 being located on the stepped structure 121 on one side of the ridge waveguide 107.
S7, forming a metal electrode, forming an N-side hot-end metal electrode 119 on the N-type semiconductor 113, forming a P-side hot-end metal electrode 118 on the P-type semiconductor 112, forming a cold-end metal electrode 111 on the surface of the passivation layer 110 on the anode electrode 109, wherein the cold-end metal electrode 111, the P-side hot-end metal electrode 118 and the N-side hot-end metal electrode 119 are separated from each other, and the cold-end metal electrode 111 extends from the surface of the passivation layer 110 on the anode electrode 109 to the step-shaped structure 121 and the groove-shaped structure 122 on two sides so as to cover the anode electrode 109, the ridge waveguide layer 120 and one side of the N-type semiconductor 113 close to the ridge waveguide layer 120 and one side of the P-type semiconductor 112 close to the ridge waveguide layer 120, and filling the groove-shaped structure 122.
In the above embodiment, the N-type semiconductor 113, the P-type semiconductor 112 and the metal electrode are disposed on the laser chip, so that the temperature of the quantum well active region is reduced, but the temperature of the entire laser chip is not reduced, thereby enhancing the reliability and the photoelectric efficiency of the device.
Referring to fig. 5, the semi-finished laser chip includes a substrate layer 101, a lower confinement layer 102, a lower waveguide layer 103, a quantum well active layer 104, an upper waveguide layer 105, an upper confinement layer 106, and a ridge waveguide layer 120. The step of obtaining the semi-finished laser chip comprises the following steps:
forming a substrate layer 101, and growing a lower confinement layer 102, a lower waveguide layer 103, a quantum well active layer 104, an upper waveguide layer 105, an upper confinement layer 106 and a ridge waveguide layer 120 on the substrate layer 101 in sequence from bottom to top;
the substrate layer 101 may be a semiconductor material compound layer such as GaAs or GaN, and it will be understood that before performing subsequent processing, the substrate layer 101 needs to be processed, specifically, the substrate layer 101 is placed in a growth chamber of an MOCVD apparatus, heated to 750 ℃ to 810 ℃ in an H2 environment, baked for 30 to 50 minutes, and then AsH3 or NH3 is introduced to remove water and oxygen on the surface of the substrate layer 101, so as to complete surface heat treatment, where MOCVD is a novel vapor phase epitaxy growth technology developed on the basis of Vapor Phase Epitaxy (VPE), and will not be described herein.
When the lower limiting layer 102 is formed, the temperature in the growth chamber of the MOCVD equipment can be kept between 680 ℃ and 720 ℃, and TMGa (trimethylgallium), TMAl (trimethylaluminum), asH3 or NH3 is introduced to grow the lower limiting layer 102 on the substrate layer 101, wherein the lower limiting layer 102 is a semiconductor material compound layer such as AlGaAs or AlGaN, and the specific chemical reaction process is not described herein.
When the lower waveguide layer 103 is formed, the temperature in the growth chamber of the MOCVD equipment can be reduced to 630-670 ℃ so as to grow the lower waveguide layer 103 on the upper surface of the lower confinement layer 102, and the lower waveguide layer 103 can be a semiconductor material compound layer such as AlGaAs or AlGaN.
When the quantum well active layer 104 is formed, the temperature in the growth chamber of the MOCVD equipment is kept between 630 ℃ and 670 ℃, and the quantum well active layer 104 is grown on the upper surface of the lower waveguide layer 103, more specifically, the quantum well active layer 104 is a semiconductor material well layer such as AlGaAs or AlGaN and a semiconductor material barrier layer such as AlGaAs or AlGaN which are alternately grown.
When the upper waveguide layer 105 is formed, the temperature in the growth chamber of the MOCVD equipment is kept between 630 ℃ and 670 ℃, the upper waveguide layer 105 is grown on the upper surface of the quantum well active layer 104, and the upper waveguide layer 105 can be a semiconductor material compound layer such as AlGaAs or AlGaN.
When the upper confinement layer 106 is formed, the temperature in the growth chamber of the MOCVD equipment is raised to 680-720 ℃, the upper confinement layer 106 is grown on the upper surface of the upper waveguide layer 105, and the upper confinement layer 106 may be a semiconductor material compound layer such as AlGaAs or AlGaN.
When the ridge waveguide layer 120 is formed, the temperature in the growth chamber of the MOCVD equipment is reduced to 530-570 ℃, and the ridge waveguide layer 120 is grown on the upper surface of the upper confinement layer 106, and the ridge waveguide layer 120 may be a semiconductor material compound layer such as GaAs or GaN.
The integrated p-type Peltier refrigerating high-power FP laser chip can be realized, the temperature of an active layer is reduced, the efficiency of a device is improved, and the working performance of the laser chip is improved.
In addition, the effect of the integrated peltier refrigeration FP laser chip is affected by the manufacturing process and the structural dimensional change, so that appropriate optimization needs to be performed according to different device structures and process methods, and the integrated peltier refrigeration FP laser chip has an optimal effect.
In this document, terms such as front, rear, upper, lower, etc. are defined with respect to the positions of the components in the drawings and with respect to each other, for clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the protection sought herein.
It is apparent that the embodiments described above are only some embodiments of the present application, but not all embodiments, and the present application is not limited to the details of the above embodiments, and any suitable changes or modifications made by those skilled in the art will be deemed to be within the scope of the present application.
Claims (8)
1. The integrated common P-type Peltier refrigeration high-power FP laser chip comprises a substrate layer, a lower limiting layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper limiting layer and a ridge waveguide layer which are sequentially arranged along the epitaxial growth direction from bottom to top, wherein a cathode electrode is arranged below the substrate layer, an anode electrode is arranged above the ridge waveguide layer, the ridge waveguide layer is arranged above the upper limiting layer, and one side of the ridge waveguide layer is of a step-shaped structure; the laser chip is also provided with a passivation layer coating the periphery of the laser chip, and the laser chip further comprises:
the N-type semiconductor is arranged on the passivation layer corresponding to the step-shaped structure;
the metal electrode comprises a cold end metal electrode, a P side hot end metal electrode and an N side hot end metal electrode, wherein the cold end metal electrode is arranged on the surface of the passivation layer on the anode electrode, extends from the surface of the passivation layer on the anode electrode to the step-shaped structures and the groove-shaped structures on two sides so as to cover the anode electrode, the ridge waveguide, one side of the N type semiconductor, which is close to the ridge waveguide, and one side of the P type semiconductor, which is close to the ridge waveguide, and fills the groove-shaped structures; the N-side hot-end metal electrode is arranged on the upper surface of the N-type semiconductor, the P-side hot-end metal electrode is arranged on the upper surface of the P-type semiconductor, and the cold-end metal electrode, the P-side hot-end metal electrode and the N-side hot-end metal electrode are separated from each other.
2. The integrated co-P type peltier refrigeration high power FP laser chip of claim 1, wherein the N-side hot side metal electrode is disposed on a side of the upper surface of the N-type semiconductor away from the ridge waveguide, and the P-side hot side metal electrode is disposed on a side of the upper surface of the P-type semiconductor away from the ridge waveguide.
3. The integrated co-p type peltier refrigeration high power FP laser chip of claim 1, wherein the laser chip further comprises a reflective film and an anti-reflection film, the reflective film is coated on a rear end face of the laser chip, and the anti-reflection film is coated on a front end face of the laser chip.
4. The integrated co-P-type peltier refrigeration high power FP laser chip of claim 1, wherein the P-type semiconductor material is antimonide.
5. The integrated co-P type peltier refrigeration high power FP laser chip of claim 4, wherein the material of the N type semiconductor is ITO, the material of the P type semiconductor is GaSb, and the material of the metal electrode is Al, au or Ag.
6. The preparation method of the FP laser chip integrating Peltier refrigeration is characterized by comprising the following steps of:
obtaining a semi-finished laser chip;
forming a step-shaped structure and a preliminary groove-shaped structure, photoetching a ridge waveguide layer to form a ridge waveguide and a P-type semiconductor, wherein one side of the ridge waveguide is formed into the step-shaped structure, and the other side of the ridge waveguide is formed into the preliminary groove-shaped structure;
forming a groove-shaped structure, photoetching a position corresponding to the preliminary groove-shaped structure in the laser chip to form a groove-shaped structure, wherein the groove-shaped structure penetrates through the quantum well active layer;
forming an anode electrode and a cathode electrode, wherein the anode electrode is arranged above the ridge waveguide, and the cathode electrode is arranged below the substrate layer;
forming a passivation layer on two sides of the laser chip, the step-shaped structures, the upper surface of the ridge waveguide and the groove-shaped structures;
forming an N-type semiconductor which is arranged on the passivation layer corresponding to the step-shaped structure;
forming a metal electrode, forming an N-side hot-end metal electrode on the N-type semiconductor by a photoetching technology, forming a P-side hot-end metal electrode on the P-type semiconductor, forming a cold-end metal electrode on the surface of a passivation layer on the anode electrode, wherein the cold-end metal electrode, the P-side hot-end metal electrode and the N-side hot-end metal electrode are separated from each other, and the cold-end metal electrode extends from the surface of the passivation layer on the anode electrode to the step-shaped structures and the groove-shaped structures on two sides so as to cover the anode electrode, the ridge waveguide layer, one side of the N-type semiconductor, which is close to the ridge waveguide layer, and one side of the P-type semiconductor, which is close to the ridge waveguide layer, and filling the groove-shaped structures.
7. The method for manufacturing an integrated peltier refrigeration FP laser chip of claim 6, wherein the step of obtaining a semi-finished laser chip comprises:
and growing a lower limiting layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper limiting layer and a ridge waveguide layer on the substrate layer sequentially from bottom to top.
8. The method for manufacturing an FP laser chip integrated with peltier refrigeration as claimed in claim 6, wherein the step of forming the metal electrode further comprises the steps of:
a reflecting film and an antireflection film are formed, the rear end face of the laser chip is coated with the reflecting film, and the front end face of the laser chip is coated with the antireflection film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311595515.6A CN117317798B (en) | 2023-11-28 | 2023-11-28 | Integrated common-p type Peltier refrigeration high-power FP laser chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311595515.6A CN117317798B (en) | 2023-11-28 | 2023-11-28 | Integrated common-p type Peltier refrigeration high-power FP laser chip and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117317798A CN117317798A (en) | 2023-12-29 |
| CN117317798B true CN117317798B (en) | 2024-02-20 |
Family
ID=89281429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311595515.6A Active CN117317798B (en) | 2023-11-28 | 2023-11-28 | Integrated common-p type Peltier refrigeration high-power FP laser chip and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117317798B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980044612A (en) * | 1996-12-07 | 1998-09-05 | 양승택 | High power semiconductor laser with new heat dissipation structure |
| CN109103746A (en) * | 2017-06-21 | 2018-12-28 | 瑞萨电子株式会社 | Semiconductor laser |
| CN115693403A (en) * | 2023-01-05 | 2023-02-03 | 深圳市星汉激光科技股份有限公司 | GaAs FP laser chip and preparation method thereof |
| CN116417898A (en) * | 2023-06-09 | 2023-07-11 | 深圳市星汉激光科技股份有限公司 | FP laser chip integrating Peltier refrigeration and preparation method thereof |
-
2023
- 2023-11-28 CN CN202311595515.6A patent/CN117317798B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980044612A (en) * | 1996-12-07 | 1998-09-05 | 양승택 | High power semiconductor laser with new heat dissipation structure |
| CN109103746A (en) * | 2017-06-21 | 2018-12-28 | 瑞萨电子株式会社 | Semiconductor laser |
| CN115693403A (en) * | 2023-01-05 | 2023-02-03 | 深圳市星汉激光科技股份有限公司 | GaAs FP laser chip and preparation method thereof |
| CN116417898A (en) * | 2023-06-09 | 2023-07-11 | 深圳市星汉激光科技股份有限公司 | FP laser chip integrating Peltier refrigeration and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117317798A (en) | 2023-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100523484B1 (en) | Method for fabricating semiconductor optical devices having current-confined structure | |
| CN102545052B (en) | Edge-emitting diode semiconductor laser with raster structure | |
| GB2346478A (en) | Optical emission device | |
| CA2072632A1 (en) | Structure and method for fabricating indium phosphide/indium gallium arsenide phosphide buried heterostructure semiconductor lasers | |
| CN109888612A (en) | Electric pump deep ultraviolet AlGaN semiconductor laser and preparation method thereof | |
| US5163064A (en) | Laser diode array and manufacturing method thereof | |
| CN116417898B (en) | FP laser chip integrating Peltier refrigeration and preparation method thereof | |
| CN115693403A (en) | GaAs FP laser chip and preparation method thereof | |
| GB2082381A (en) | Semiconductor laser | |
| CN117317798B (en) | Integrated common-p type Peltier refrigeration high-power FP laser chip and preparation method thereof | |
| US3998672A (en) | Method of producing infrared luminescent diodes | |
| CN109830575B (en) | Super-radiation light emitting diode epitaxial wafer, preparation method of epitaxial wafer and chip | |
| CA1065461A (en) | Semiconductor light-emitting device and method of making of the same | |
| CN101902016A (en) | Semiconductor laser | |
| CN219576201U (en) | Local hollow light beam vertical cavity surface emitting laser | |
| KR100363240B1 (en) | Semiconductor laser diode and its manufacturing method | |
| JPS61107782A (en) | Compound semiconductor device | |
| KR100259004B1 (en) | Semiconductor laser diode array device and its manufacturing method | |
| CN117638647A (en) | AlGaN-based semiconductor laser structure and preparation method thereof | |
| KR910005392B1 (en) | Manufacturing method of double-hetero junction type led with junction current limited region | |
| CN116706685A (en) | SiN stress-based stepped structure GeSn laser and preparation method thereof | |
| KR100287203B1 (en) | Semiconductor laser diode with double clad structure | |
| CN118508229A (en) | Vcsel structure with low series resistance and preparation method thereof | |
| JP2599391B2 (en) | Semiconductor light emitting device manufacturing method and semiconductor light emitting device | |
| JPH01214083A (en) | Semiconductor laser device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |