CN117316918A - Three-dimensional chip packaging structure and method - Google Patents

Three-dimensional chip packaging structure and method Download PDF

Info

Publication number
CN117316918A
CN117316918A CN202311263695.8A CN202311263695A CN117316918A CN 117316918 A CN117316918 A CN 117316918A CN 202311263695 A CN202311263695 A CN 202311263695A CN 117316918 A CN117316918 A CN 117316918A
Authority
CN
China
Prior art keywords
wafer
carrier
solder ball
bare
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311263695.8A
Other languages
Chinese (zh)
Inventor
唐荣烨
高朕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chuanzhou Semiconductor Technology Shanghai Co ltd
Original Assignee
Chuanzhou Semiconductor Technology Shanghai Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chuanzhou Semiconductor Technology Shanghai Co ltd filed Critical Chuanzhou Semiconductor Technology Shanghai Co ltd
Priority to CN202311263695.8A priority Critical patent/CN117316918A/en
Publication of CN117316918A publication Critical patent/CN117316918A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

The invention provides a three-dimensional chip packaging structure and a method, wherein the packaging structure comprises: a wafer carrier for carrying a bare wafer; the bare wafer comprises a solder ball bare wafer and a non-solder ball bare wafer, the solder ball bare wafer is welded and attached to the surface of the wafer carrier, and the non-solder ball bare wafer is adhered and attached to the surface of the solder ball bare wafer or the surface of the wafer carrier; functional bonding pads are arranged on the surfaces of the two sides of the wafer carrier, the solder ball bare wafer is provided with a first side and a second side, the first side of the solder ball bare wafer is provided with wafer solder balls, and the wafer solder balls are suitable for being welded and attached to the functional bonding pads; the non-solder ball bare wafer is provided with a third side and a fourth side, the third side of the non-solder ball bare wafer is provided with a first wafer bonding pad, and the first wafer bonding pad is suitable for being connected with the functional bonding pad through a metal lead wire in a welding way; the fourth side of the non-solder ball bare wafer is adhered and attached to the second side of the solder ball bare wafer or attached to the surface of the wafer carrier. The invention reduces the occupation area of the bare wafer and improves the chip integration level.

Description

Three-dimensional chip packaging structure and method
Technical Field
The invention relates to the technical field of chip packaging, in particular to a three-dimensional chip packaging structure and method.
Background
With the rapid development of integrated circuit technology, the integration level of devices is increasingly improved, the line width is increasingly reduced, and the challenges brought to chip packaging are increasingly greater. In the existing wafer-level chip packaging technology, a bare wafer is attached to a carrier for packaging, and the bare wafer is attached to the surface of the carrier, so that the occupied area of the carrier is larger; only one surface of the carrier is attached with the bare wafer, and the other surface of the carrier is attached to the PCB after packaging is completed, so that the integration level is low; the bare wafer is packaged on the carrier in only one packaging mode, such as wire bonding or flip chip bonding, so that the packaging of the bare wafer in different processes on the same carrier is difficult to realize, and the application of the bare wafer in different processes is limited.
Therefore, it is necessary to provide a three-dimensional chip package structure and method for effectively solving the above-mentioned problems.
Disclosure of Invention
The invention provides a three-dimensional chip packaging structure and a three-dimensional chip packaging method, which are used for realizing three-dimensional stacking packaging of a non-solder ball bare wafer and a solder ball bare wafer by changing the packaging mode of the non-solder ball bare wafer on a carrier, reducing the occupied area of the bare wafer and improving the chip integration level.
The embodiment of the invention provides a three-dimensional chip packaging structure, which comprises:
a wafer carrier for carrying a bare wafer;
the bare wafer comprises a solder ball bare wafer and a non-solder ball bare wafer, the solder ball bare wafer is welded and attached to the surface of the wafer carrier, and the non-solder ball bare wafer is adhered and attached to the surface of the solder ball bare wafer or the surface of the wafer carrier;
the external bearing bodies are arranged on two sides of the wafer bearing body carrying the bare wafers;
the metal support is arranged between the wafer carrier and the external carrier and is used for connecting the wafer carrier and the external carrier;
wherein, the two side surfaces of the wafer carrier are provided with functional bonding pads,
the solder ball bare wafer is provided with a first side and a second side, the first side of the solder ball bare wafer is provided with a wafer solder ball, and the wafer solder ball is suitable for being welded and attached with the functional bonding pad;
the non-solder ball bare wafer is provided with a third side and a fourth side, the third side of the non-solder ball bare wafer is provided with a first wafer bonding pad, and the first wafer bonding pad is suitable for being connected with the functional bonding pad through a metal lead wire in a welding way;
the fourth side of the non-solder ball bare wafer is adhered and attached to the second side of the solder ball bare wafer or attached to the surface of the wafer carrier;
the wafer carrier is provided with a first conduction structure, the external carrier is provided with a second conduction structure, and the functional pads are electrically connected with the second conduction structure through the first conduction structure and the metal support columns.
Preferably, the first conducting structure comprises a first conducting hole and a first metal circuit, the first conducting hole penetrates through the wafer carrier, first hole rings are formed on two side surfaces of the wafer carrier, metal layers are plated on inner walls of the first hole rings and the first conducting hole, the first metal circuit is arranged on two side surfaces of the wafer carrier, and the first metal circuit is electrically communicated with the first hole rings and the functional pads.
Preferably, the first conductive structure further includes a wafer carrier solder ball disposed on two side surfaces of the wafer carrier, the wafer carrier solder ball is disposed at the first conductive hole, and the wafer carrier solder ball is adapted to be welded to the first hole ring and the metal pillar, and electrically communicate the first hole ring and the metal pillar.
Preferably, the second conducting structure comprises a second conducting hole and a second metal circuit, the second conducting hole penetrates through the outer supporting body, second hole rings are formed on two side surfaces of the outer supporting body, the second hole rings and the inner wall of the second conducting hole are plated with metal layers, the second metal circuit is arranged on the surface of the outer supporting body, and the second metal circuit is electrically communicated with the second hole rings.
Preferably, the second conductive structure further includes external carrier solder balls disposed on two side surfaces of the external carrier, the external carrier solder balls disposed on one side of the external carrier near the wafer carrier are adapted to be welded to the second metal circuit and the metal pillar, and electrically communicate the second metal circuit and the metal pillar; the external carrier solder balls arranged on one side of the external carrier far from the wafer carrier are suitable for being connected with the second hole ring in a welding way and electrically conducted.
Preferably, a second wafer bonding pad is arranged on the first side of the solder ball bare wafer, a metal column is arranged on the second wafer bonding pad, and the wafer solder ball covers the second wafer bonding pad and the metal column.
Preferably, the material of the wafer carrier is silicon, and the first metal circuit is sputtered on the surface of the wafer carrier; or the wafer carrier is made of PI, FR4, PET or G10, and the first metal circuit is coated on the surface of the wafer carrier; the first metal circuit is made of copper, nickel, gold, copper alloy, nickel alloy or gold alloy;
the external carrier is made of silicon, and the second metal circuit is sputtered on the surface of the external carrier; or the material of the external carrier is PI, FR4, PET or G10, and the second metal circuit is coated on the surface of the external carrier; the second metal circuit is made of copper, nickel, gold, copper alloy, nickel alloy or gold alloy.
Preferably, the material of the wafer solder ball is tin, gold, silver, copper, nickel, tin alloy, gold alloy, silver alloy, copper alloy or nickel alloy; the metal support posts are made of copper or copper alloy.
Based on the same conception, the embodiment of the invention also provides a three-dimensional chip packaging method, wherein the packaging structure comprises a wafer carrier, a bare wafer, an external carrier and a metal support, the wafer carrier is provided with a functional bonding pad and a first conduction structure, and the first conduction structure is electrically conducted with the functional bonding pad; the bare wafers comprise solder ball bare wafers and non-solder ball bare wafers, the solder ball bare wafers are provided with wafer solder balls, and the non-solder ball bare wafers are provided with first wafer bonding pads; the outer bearing body is provided with a second conducting structure; the packaging method comprises the following steps:
providing the wafer carrier, and providing the solder ball bare wafer and the non-solder ball bare wafer;
the wafer solder balls are connected with the functional bonding pads in a welding way and are electrically conducted, so that the solder ball bare wafer is welded and attached to the surface of the wafer carrier;
adhering and mounting one side of the non-solder ball bare wafer, which is not provided with the first wafer bonding pad, on the surface of the solder ball bare wafer or on the surface of the wafer carrier through conductive adhesive;
the first wafer bonding pad of the non-solder ball bare wafer is connected with the functional bonding pad through a metal lead in a welding way and is electrically conducted;
the outer bearing bodies are arranged on two sides of the wafer bearing body, and the metal support posts are arranged between the wafer bearing body and the outer bearing bodies;
and one end of the metal pillar is welded with the first conducting structure and is electrically conducted, and the other end of the metal pillar is welded with the second conducting structure and is electrically conducted, so that the functional bonding pad is electrically conducted with the second conducting structure.
Preferably, the first conducting structure includes a first conducting hole, a first metal circuit and a wafer carrier solder ball, the first conducting hole penetrates through the wafer carrier, the first conducting hole is formed with first hole rings on two side surfaces of the wafer carrier, the first hole rings and inner walls of the first conducting hole are plated with metal layers, the first metal circuit is arranged on two side surfaces of the wafer carrier, and the metal circuit is electrically connected with the first hole rings and the functional pads; the wafer carrier solder balls are electrically connected with the first hole ring;
the second conducting structure comprises a second conducting hole, a second metal circuit and an external carrier solder ball, wherein the second conducting hole penetrates through the external carrier, second hole rings are formed on the surfaces of two sides of the external carrier, metal layers are plated on the second hole rings and the inner wall of the second conducting hole, the second metal circuit is arranged on the surface of the external carrier, and the second metal circuit is electrically communicated with the second hole rings; the external carrier solder balls are arranged on the surfaces of two sides of the external carrier, the external carrier solder balls arranged on one side of the external carrier, which is close to the wafer carrier, are electrically connected with the second metal circuit, the external carrier solder balls arranged on one side of the external carrier, which is far away from the wafer carrier, are electrically connected with the second hole ring, and the packaging method further comprises:
one end of the metal pillar is welded with the wafer carrier solder ball and is electrically conducted;
and welding and connecting the other end of the metal pillar with the external carrier solder ball arranged on one side close to the wafer carrier, and conducting the other end of the metal pillar electrically.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the three-dimensional chip packaging structure and the three-dimensional chip packaging method, the non-solder ball bare wafers are adhered and attached to the solder ball bare wafers in a longitudinal superposition mode, meanwhile, the bare wafers are attached to the wafer carrier in a double-sided manner, the occupied area of the bare wafers is reduced, and the integration level is improved; the two mounting modes of wire bonding and flip chip bonding are realized on one wafer carrier, so that the bare wafers with different processes can be integrated in one carrier, and the application range of the bare wafers with different processes is enlarged.
Further, the metal support is arranged to connect the wafer carrier with the external carrier, so that the supporting connection of the carrier is realized, the first communication structure is arranged on the wafer carrier, the second communication structure is arranged on the external carrier, and the electrical extraction of the bare wafer is realized through the communication of the metal support, so that the process is simple and easy to realize.
Further, through arranging the via holes on the carrier and plating metal layers in the via holes, the metal circuits on two sides of the carrier are conducted, the process is simplified, and the efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the prior art, a brief description of the drawings is provided below, wherein it is apparent that the drawings in the following description are some, but not all, embodiments of the present invention. Other figures may be derived from these figures without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a three-dimensional chip package structure according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a bare wafer of solder balls according to one embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a bare wafer without solder balls according to one embodiment of the present invention;
fig. 4 is a schematic diagram of a three-dimensional chip package structure according to another embodiment of the invention.
In the figure:
1. a wafer carrier; 2. a bare wafer; 3. an outer carrier; 4. a metal pillar; 5. a metal lead; 6. conducting resin;
11. a functional bonding pad; 12. a first conductive structure; 121. a first via hole; 122. wafer carrier solder balls;
21. solder ball bare wafer; 211. a first side; 212. a second side; 213. wafer solder balls; 214. a second wafer pad; 215. a metal column; 22. a bare wafer of non-solder balls; 221. a third side; 222. a fourth side; 223. a first wafer pad;
31. a second conductive structure; 311. a second via hole; 312. external carrier solder balls.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Based on the problems existing in the prior art, the embodiment of the invention provides a three-dimensional chip packaging structure and a three-dimensional chip packaging method, which are used for realizing three-dimensional stacking packaging of a non-solder ball bare wafer and a solder ball bare wafer by changing the packaging mode of the non-solder ball bare wafer on a carrier, reducing the occupied area of the bare wafer and improving the chip integration level.
Fig. 1 is a schematic diagram of a three-dimensional chip package structure according to an embodiment of the present invention; FIG. 2 is a schematic cross-sectional view of a bare wafer of solder balls according to one embodiment of the present invention; FIG. 3 is a schematic cross-sectional view of a bare wafer without solder balls according to one embodiment of the present invention; fig. 4 is a schematic diagram of a three-dimensional chip package structure according to another embodiment of the invention.
Referring now to fig. 1 to 4, an embodiment of the present invention provides a three-dimensional chip package structure, including:
a wafer carrier 1, the wafer carrier 1 is used for carrying a bare wafer 2;
the bare wafer 2 comprises a solder ball bare wafer 21 and a non-solder ball bare wafer 22, wherein the solder ball bare wafer 21 is welded and attached to the surface of the wafer carrier 1, and the non-solder ball bare wafer 22 is adhered and attached to the surface of the solder ball bare wafer 21 or the surface of the wafer carrier 1;
an outer carrier 3, the outer carrier 3 being disposed on both sides of the wafer carrier 1 carrying the bare wafer 2;
a metal support column 4, wherein the metal support column 4 is arranged between the wafer carrier 1 and the external carrier 3 and is connected with the wafer carrier 1 and the external carrier 3;
wherein, the two side surfaces of the wafer carrier 1 are provided with functional pads 11, the bare wafer 2 can be mounted on the wafer carrier 1 in double-sided manner, the mounting area of the wafer carrier 1 is increased, and the integration level is improved.
The solder ball bare wafer 21 has a first side 211 and a second side 212, the first side 211 of the solder ball bare wafer 21 is provided with wafer solder balls 213, and the wafer solder balls 213 are suitable for soldering with the functional pads 11 for flip-chip mounting.
The non-solder ball bare wafer 22 has a third side 221 and a fourth side 222, the third side 221 of the non-solder ball bare wafer 22 is provided with a first wafer pad 223, and the first wafer pad 223 is suitable for being in welded connection with the functional pad 11 through the metal lead 5, so as to realize wire bonding attachment.
The fourth side 222 of the non-solder ball bare wafer 22 is adhered to the second side 212 of the solder ball bare wafer 21 or to the surface of the wafer carrier 1; and the non-solder ball bare wafer 22 is adhered and attached to the solder ball bare wafer 21 in a longitudinal superposition mode, so that the occupied area of the bare wafer 2 is reduced, and the integration level is improved.
The wafer carrier 1 is provided with a first conducting structure 12, the external carrier 3 is provided with a second conducting structure 31, and the functional pads 11 are electrically connected with the second conducting structure 31 through the first conducting structure 12 and the metal support columns 4, so that the electrical extraction of the bare wafer 2 is realized.
In a specific implementation, when the bare wafer 2 is mounted on the wafer carrier 1 in a double-sided manner, the bare wafer 2 may be symmetrically arranged or asymmetrically arranged; the wafer carrier 1 can be individually soldered with a solder ball bare wafer 21, a non-solder ball bare wafer 22 can be attached to the solder ball bare wafer 21 after soldering, and the non-solder ball bare wafer 22 can be attached to the wafer carrier 1. The area on which the bare wafer 2 is mounted or soldered needs to be kept away during soldering, and the wafer carrier 1 needs to reach a certain strength, so that the stress caused in all the processes can be supported.
In a specific embodiment, the first side 211 of the solder ball bare wafer 21 is provided with a second wafer pad 214, the second wafer pad 214 is provided with a metal pillar 215, and the wafer solder ball 213 wraps around the second wafer pad 214 and the metal pillar 215.
In some embodiments, the first conductive structure 12 includes a first conductive hole 121 and a first metal circuit, the first conductive hole 121 is disposed through the wafer carrier 1, the first conductive hole 121 is formed with first hole rings on two side surfaces of the wafer carrier 1, the inner walls of the first hole rings and the first conductive hole 121 are plated with metal layers, the first metal circuit is disposed on two side surfaces of the wafer carrier 1, and the first metal circuit is electrically connected with the first hole rings and the functional pads 11.
In some embodiments, the diameter of the first via 121 is: 20um-200um.
In some embodiments, the first conductive structure 12 further includes wafer carrier solder balls 122 disposed on two side surfaces of the wafer carrier 1, the wafer carrier solder balls 122 are disposed at the first conductive holes 121, and the wafer carrier solder balls 122 are adapted to be soldered to the first hole ring and the metal pillars 4, and electrically communicate the first hole ring and the metal pillars 4.
In some embodiments, the second conductive structure 31 includes a second conductive hole 311 and a second metal circuit, the second conductive hole 311 is disposed through the external carrier 3, the second conductive hole 311 is formed with second hole rings on two side surfaces of the external carrier 3, the inner walls of the second hole rings and the second conductive hole 311 are plated with metal layers, the second metal circuit is disposed on the surface of the external carrier 3, and the second metal circuit is electrically connected with the second hole rings 311.
In some embodiments, the diameter of the second via hole 311 is: 20um-200um.
In some embodiments, the second conductive structure 31 further includes external carrier solder balls 312 disposed on two side surfaces of the external carrier 3, and the external carrier solder balls 312 disposed on one side of the external carrier 3 near the wafer carrier 1 are adapted to be soldered to the second metal circuit and the metal pillars 4, so as to electrically communicate the second metal circuit and the metal pillars 4; the external carrier solder balls 312 disposed on the external carrier 3 at a side far from the wafer carrier 1 are adapted to be soldered to and electrically connected with the second hole ring.
In some embodiments, external circuitry is electrically connected to the PCB (Printed Circuit Board ) by external carrier solder balls 312 disposed on the side of the external carrier 3 remote from the wafer carrier 1.
In some embodiments, the fourth side 222 of the non-solder ball bare wafer 22 is adhesively attached to the second side 212 of the solder ball bare wafer 21 or to the surface of the wafer carrier 1 by the conductive adhesive 6.
In some embodiments, the material of the wafer carrier 1 is silicon, and the first metal circuit is sputtered on the surface of the wafer carrier 1.
In some embodiments, the material of the wafer carrier 1 is PI (Polyimide), FR4 (code of a flame-retardant material grade of a glass fiber epoxy resin copper-clad plate, which means a material specification that the resin material must be able to self-extinguish after being burnt), PET (Polyethylene terephthalate ) or G10 (glass fiber and resin laminated composite; G represents glass fiber, 10 means that the content of glass fiber is 10%, and the G10 material has the characteristics of insulation, corrosion resistance and wear resistance, and can bear extremely large force without damage deformation); the first metal circuit is applied on the surface of the wafer carrier 1.
In some embodiments, the first metal line is made of a metal material with a very good conductive effect, and the material of the first metal line is copper, nickel, gold, copper alloy, nickel alloy or gold alloy;
in some embodiments, the outer carrier 3 is similar to the wafer carrier 1, and is made of silicon, and the second metal line is sputtered on the surface of the outer carrier 3.
In some embodiments, the external carrier 3 is similar to the wafer carrier 1, and is made of PI, FR4, PET or G10, and the second metal circuit is applied on the surface of the external carrier 3.
In some embodiments, the second metal line is made of a metal material with very good electrical conductivity, and the material of the second metal line is copper, nickel, gold, copper alloy, nickel alloy or gold alloy.
In some embodiments, the material of the wafer solder balls 213 is tin, gold, silver, copper, nickel, tin alloy, gold alloy, silver alloy, copper alloy or nickel alloy; the metal pillar 4 is made of copper or a copper alloy.
In some embodiments, the wafer carrier solder balls 122, the external carrier solder balls 312 are similar to the wafer solder balls 213, and are made of tin, gold, silver, copper, nickel, tin alloy, gold alloy, silver alloy, copper alloy, or nickel alloy.
The embodiment of the invention also provides a method for packaging the three-dimensional chip, wherein the packaging structure comprises a wafer carrier 1, a bare wafer 2, an external carrier 3 and a metal support column 4, the wafer carrier 1 is provided with a functional bonding pad 11 and a first conducting structure 12, and the first conducting structure 12 is electrically conducted with the functional bonding pad 11; the bare wafer 2 includes a solder ball bare wafer 21 and a non-solder ball bare wafer 22, the solder ball bare wafer 21 is provided with a wafer solder ball 213, and the non-solder ball bare wafer 22 is provided with a first wafer pad 223; the outer carrier 3 is provided with a second conducting structure 31; the packaging method comprises the following steps:
s1: providing a wafer carrier 1, providing a solder ball bare wafer 21 and a non-solder ball bare wafer 22;
s2: the wafer solder ball 213 is welded and connected with the functional bonding pad 11 and is electrically conducted, so that the solder ball bare wafer 21 is welded and attached on the surface of the wafer carrier 1;
s3: bonding and attaching one side of the non-solder ball bare wafer 22, which is not provided with the first wafer bonding pad 223, to the surface of the solder ball bare wafer 21 or to the surface of the wafer carrier 1 through the conductive adhesive 6;
s4: the first wafer bonding pad 223 of the non-solder ball bare wafer 22 is welded and connected with the functional bonding pad 11 through the metal lead 5 and is electrically conducted;
s5: the outer carrier 3 is arranged on two sides of the wafer carrier 1, and the metal support posts 4 are arranged between the wafer carrier 1 and the outer carrier 3;
s6: one end of the metal pillar 4 is welded with the first conducting structure 12 and is electrically conducted, and the other end of the metal pillar is welded with the second conducting structure 31 and is electrically conducted, so that the functional pad 11 is electrically conducted with the second conducting structure 31.
In some embodiments, the first conductive structure 12 includes a first via hole 121, a first metal circuit and a wafer carrier solder ball 122, the first via hole 121 is disposed through the wafer carrier 1, the first via hole 121 is formed with first hole rings on two side surfaces of the wafer carrier 1, the inner walls of the first hole rings and the first via hole 121 are plated with metal layers, the first metal circuit is disposed on two side surfaces of the wafer carrier 1, and the metal circuit is electrically connected with the first hole rings and the functional pads 11; the wafer carrier solder balls 122 are electrically connected with the first hole ring;
the second conducting structure 31 comprises a second conducting hole 311, a second metal circuit and an external carrier solder ball 312, the second conducting hole 311 penetrates through the external carrier 3, second conducting holes 311 are respectively formed with second hole rings on the two side surfaces of the external carrier 3, the second hole rings and the inner wall of the second conducting hole 311 are respectively plated with a metal layer, the second metal circuit is arranged on the surface of the external carrier 3, and the second metal circuit is electrically communicated with the second hole rings; the external carrier solder balls 312 are disposed on two side surfaces of the external carrier 3, the external carrier solder balls 312 disposed on one side of the external carrier 3 close to the wafer carrier 1 are electrically connected with the second metal circuit, the external carrier solder balls 312 disposed on one side of the external carrier 3 far from the wafer carrier 1 are electrically connected with the second hole ring, and the packaging method further comprises:
one end of the metal pillar 4 is soldered to and electrically connected to the wafer carrier solder ball 122;
the other end of the metal pillar 4 is soldered to and electrically connected to an external carrier solder ball 312 provided on the side close to the wafer carrier 1.
In a specific implementation, in the process of preparing the solder ball bare wafer 21, the precision of the metal pillars 215 and the wafer solder balls 213 implanted on the solder ball bare wafer 21 needs to be ensured, so as to ensure the flatness of the solder ball bare wafer 21 soldered on the wafer carrier 1, and a high-precision photoetching machine and a photomask are required to be adopted to realize the implantation of the metal pillars 215 and the wafer solder balls 213. The solder ball bare wafer 21 is prepared as follows:
firstly, coating photoresist on the surface of a wafer after metal sputtering, covering the surface of the wafer by a photomask, and irradiating by microwaves on a photoetching machine;
carrying out partial windowing on the area of the surface of the wafer, which is not required to be covered by photoresist, in a developing mode, and removing the photoresist to form a windowing area; the diameter of the windowing area is 100um, and the alignment precision of the windowing area can reach +/-1.0 um.
Metal plating is performed on the windowed region of the photoresist using a semiconductor plating apparatus to produce metal pillars 215 and wafer solder balls 213. The overall height of the metal pillars 215 and the wafer solder balls 213 is typically 45um, and the accuracy of the flatness can reach ±1.5um.
In a specific implementation, when the wafer solder ball 213 is welded to the functional pad 11, it is required that the metal pillar 215 is kept at a certain flatness when the wafer solder ball 213 is supported on the functional pad 11 after being melted; when the solder ball bare wafer 21 is welded and mounted, soldering flux is printed on the wafer carrier 1, and then special FLIP CHIP FLIP-CHIP bonding equipment is adopted to mount the solder ball bare wafer 21 on the wafer carrier 1, wherein the mounting precision of the FLIP-CHIP bonding equipment can reach +/-1.0 um; finally, the wafer solder balls 213 on the solder ball bare wafer 21 are melted by a reflow soldering device, and the solder balls 213 and the functional pads 11 are soldered together.
In summary, according to the three-dimensional chip packaging structure and method provided by the embodiment of the invention, the non-solder ball bare wafer 22 is bonded and attached to the solder ball bare wafer 21 in a longitudinal superposition manner, meanwhile, the bare wafer 2 is attached to the wafer carrier 1 on both sides, so that the occupied area of the bare wafer 2 is reduced, and the integration level is improved; two mounting modes of wire bonding and flip chip bonding are realized on one wafer carrier 1, so that the bare wafers 2 with different processes can be integrated in one carrier, and the application range of the bare wafers 2 with different processes is enlarged.
Further, the metal support posts 4 are arranged to connect the wafer carrier 1 with the external carrier 3, so as to realize the supporting connection of the carrier, the first communication structure 12 is arranged on the wafer carrier 1, the second communication structure 31 is arranged on the external carrier 3, and the metal support posts 4 are communicated, so that the electrical extraction of the bare wafer 2 is realized, and the process is simple and easy to realize.
Further, through arranging the via holes on the carrier and plating metal layers in the via holes, the metal circuits on two sides of the carrier are conducted, the process is simplified, and the efficiency is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (10)

1. The utility model provides a three-dimensional chip packaging structure which characterized in that includes:
a wafer carrier for carrying a bare wafer;
the bare wafer comprises a solder ball bare wafer and a non-solder ball bare wafer, the solder ball bare wafer is welded and attached to the surface of the wafer carrier, and the non-solder ball bare wafer is adhered and attached to the surface of the solder ball bare wafer or the surface of the wafer carrier;
the external bearing bodies are arranged on two sides of the wafer bearing body carrying the bare wafers;
the metal support is arranged between the wafer carrier and the external carrier and is used for connecting the wafer carrier and the external carrier;
wherein, the two side surfaces of the wafer carrier are provided with functional bonding pads,
the solder ball bare wafer is provided with a first side and a second side, the first side of the solder ball bare wafer is provided with a wafer solder ball, and the wafer solder ball is suitable for being welded and attached with the functional bonding pad;
the non-solder ball bare wafer is provided with a third side and a fourth side, the third side of the non-solder ball bare wafer is provided with a first wafer bonding pad, and the first wafer bonding pad is suitable for being connected with the functional bonding pad through a metal lead wire in a welding way;
the fourth side of the non-solder ball bare wafer is adhered and attached to the second side of the solder ball bare wafer or attached to the surface of the wafer carrier;
the wafer carrier is provided with a first conduction structure, the external carrier is provided with a second conduction structure, and the functional pads are electrically connected with the second conduction structure through the first conduction structure and the metal support columns.
2. The three-dimensional chip packaging structure according to claim 1, wherein the first conducting structure comprises a first conducting hole and a first metal circuit, the first conducting hole penetrates through the wafer carrier, first hole rings are formed on two side surfaces of the wafer carrier, metal layers are plated on inner walls of the first hole rings and the first conducting hole, the first metal circuit is arranged on two side surfaces of the wafer carrier, and the first metal circuit is electrically communicated with the first hole rings and the functional pads.
3. The three-dimensional chip package structure of claim 2, wherein the first conductive structure further comprises wafer carrier solder balls disposed on two side surfaces of the wafer carrier, the wafer carrier solder balls being disposed at the first conductive holes, the wafer carrier solder balls being adapted to be soldered to the first hole ring and the metal posts and electrically communicate the first hole ring and the metal posts.
4. The three-dimensional chip packaging structure according to claim 1, wherein the second conducting structure comprises a second conducting hole and a second metal circuit, the second conducting hole penetrates through the outer carrier, second hole rings are formed on two side surfaces of the outer carrier, metal layers are plated on inner walls of the second hole rings and the second conducting hole, the second metal circuit is arranged on the surface of the outer carrier, and the second metal circuit is in electrical communication with the second hole rings.
5. The package structure of claim 4, wherein the second conductive structure further comprises external carrier solder balls disposed on two side surfaces of the external carrier, the external carrier solder balls disposed on one side of the external carrier near the wafer carrier being adapted to be soldered to the second metal line and the metal pillar, and electrically communicate the second metal line and the metal pillar; the external carrier solder balls arranged on one side of the external carrier far from the wafer carrier are suitable for being connected with the second hole ring in a welding way and electrically conducted.
6. The three-dimensional chip packaging structure according to claim 1, wherein a second wafer bonding pad is arranged on a first side of the solder ball bare wafer, a metal column is arranged on the second wafer bonding pad, and the wafer solder ball wraps the second wafer bonding pad and the metal column.
7. The three-dimensional chip package structure according to claim 2 or 4, wherein the wafer carrier is made of silicon, and the first metal circuit is sputtered on the surface of the wafer carrier; or the wafer carrier is made of PI, FR4, PET or G10, and the first metal circuit is coated on the surface of the wafer carrier; the first metal circuit is made of copper, nickel, gold, copper alloy, nickel alloy or gold alloy;
the external carrier is made of silicon, and the second metal circuit is sputtered on the surface of the external carrier; or the material of the external carrier is PI, FR4, PET or G10, and the second metal circuit is coated on the surface of the external carrier; the second metal circuit is made of copper, nickel, gold, copper alloy, nickel alloy or gold alloy.
8. The three-dimensional chip package structure of claim 1, wherein the solder balls are made of tin, gold, silver, copper, nickel, tin alloy, gold alloy, silver alloy, copper alloy or nickel alloy; the metal support posts are made of copper or copper alloy.
9. A three-dimensional chip packaging method, characterized by being applied to the three-dimensional chip packaging structure according to any one of claims 1 to 8; the packaging structure comprises a wafer carrier, a bare wafer, an external carrier and a metal support, wherein the wafer carrier is provided with a functional bonding pad and a first conducting structure, and the first conducting structure is electrically conducted with the functional bonding pad; the bare wafers comprise solder ball bare wafers and non-solder ball bare wafers, the solder ball bare wafers are provided with wafer solder balls, and the non-solder ball bare wafers are provided with first wafer bonding pads; the outer bearing body is provided with a second conducting structure; the packaging method comprises the following steps:
providing the wafer carrier, and providing the solder ball bare wafer and the non-solder ball bare wafer;
the wafer solder balls are connected with the functional bonding pads in a welding way and are electrically conducted, so that the solder ball bare wafer is welded and attached to the surface of the wafer carrier;
adhering and mounting one side of the non-solder ball bare wafer, which is not provided with the first wafer bonding pad, on the surface of the solder ball bare wafer or on the surface of the wafer carrier through conductive adhesive;
the first wafer bonding pad of the non-solder ball bare wafer is connected with the functional bonding pad through a metal lead in a welding way and is electrically conducted;
the outer bearing bodies are arranged on two sides of the wafer bearing body, and the metal support posts are arranged between the wafer bearing body and the outer bearing bodies;
and one end of the metal pillar is welded with the first conducting structure and is electrically conducted, and the other end of the metal pillar is welded with the second conducting structure and is electrically conducted, so that the functional bonding pad is electrically conducted with the second conducting structure.
10. The method of packaging a three-dimensional chip according to claim 9, wherein the first via structure includes a first via hole, a first metal line and a wafer carrier solder ball, the first via hole is disposed through the wafer carrier, the first via hole is formed with first hole rings on both side surfaces of the wafer carrier, the first hole rings and inner walls of the first via hole are plated with metal layers, the first metal line is disposed on both side surfaces of the wafer carrier, and the metal line is electrically connected with the first hole rings and the functional pads; the wafer carrier solder balls are electrically connected with the first hole ring;
the second conducting structure comprises a second conducting hole, a second metal circuit and an external carrier solder ball, wherein the second conducting hole penetrates through the external carrier, second hole rings are formed on the surfaces of two sides of the external carrier, metal layers are plated on the second hole rings and the inner wall of the second conducting hole, the second metal circuit is arranged on the surface of the external carrier, and the second metal circuit is electrically communicated with the second hole rings; the external carrier solder balls are arranged on the surfaces of two sides of the external carrier, the external carrier solder balls arranged on one side of the external carrier, which is close to the wafer carrier, are electrically connected with the second metal circuit, the external carrier solder balls arranged on one side of the external carrier, which is far away from the wafer carrier, are electrically connected with the second hole ring, and the packaging method further comprises:
one end of the metal pillar is welded with the wafer carrier solder ball and is electrically conducted;
and welding and connecting the other end of the metal pillar with the external carrier solder ball arranged on one side close to the wafer carrier, and conducting the other end of the metal pillar electrically.
CN202311263695.8A 2023-09-27 2023-09-27 Three-dimensional chip packaging structure and method Pending CN117316918A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311263695.8A CN117316918A (en) 2023-09-27 2023-09-27 Three-dimensional chip packaging structure and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311263695.8A CN117316918A (en) 2023-09-27 2023-09-27 Three-dimensional chip packaging structure and method

Publications (1)

Publication Number Publication Date
CN117316918A true CN117316918A (en) 2023-12-29

Family

ID=89254869

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311263695.8A Pending CN117316918A (en) 2023-09-27 2023-09-27 Three-dimensional chip packaging structure and method

Country Status (1)

Country Link
CN (1) CN117316918A (en)

Similar Documents

Publication Publication Date Title
US7929313B2 (en) Method of manufacturing multilayer printed circuit board
TWI459871B (en) Built-in parts wiring board, built-in parts wiring board manufacturing methods
JP3320979B2 (en) How to mount a device directly on a device carrier
KR101193416B1 (en) Three-dimensionally integrated semiconductor device and method for manufacturing the same
US20130119012A1 (en) Interconnection element for electric circuits
US20060124351A1 (en) Flexible multilayer wiring board and manufacture method thereof
TW201322389A (en) Package structure
KR20070100386A (en) Printed wiring board with component-mounting pins and electronic equipment using the same
US6708398B2 (en) Substrate for use in package of semiconductor device, semiconductor package using the substrate, and methods for manufacturing the substrate and the semiconductor package
JP4965989B2 (en) Electronic component built-in substrate and method for manufacturing electronic component built-in substrate
US6381837B1 (en) Method for making an electronic circuit assembly
US7755200B2 (en) Methods and arrangements for forming solder joint connections
JPWO2007080863A1 (en) Semiconductor device, printed wiring board mounting the semiconductor device, and connection structure thereof
US8243462B2 (en) Printed wiring board, semiconductor device, and method for manufacturing printed wiring board
US20160225706A1 (en) Printed circuit board, semiconductor package and method of manufacturing the same
CN117316918A (en) Three-dimensional chip packaging structure and method
JPWO2007072876A1 (en) Method for manufacturing printed wiring board
JP2012164934A (en) Circuit module, electronic component mounting board and circuit module manufacturing method
CN110784994A (en) Printed circuit board structure and manufacturing method thereof
CN107305849B (en) Packaging structure and manufacturing method thereof
JP4186055B2 (en) Electronic component device and electronic component manufacturing method
CN112038329A (en) Wafer-level chip fan-out three-dimensional stacking packaging structure and manufacturing method thereof
JP2006253167A (en) Method of manufacturing cavity structure printed wiring board and mounting structure
CN213718311U (en) Printed circuit board, chip and electronic equipment
KR20080107589A (en) Flip chip package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination