CN117316801A - Method and system for testing semiconductor device - Google Patents
Method and system for testing semiconductor device Download PDFInfo
- Publication number
- CN117316801A CN117316801A CN202311597546.5A CN202311597546A CN117316801A CN 117316801 A CN117316801 A CN 117316801A CN 202311597546 A CN202311597546 A CN 202311597546A CN 117316801 A CN117316801 A CN 117316801A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- performance
- model
- semiconductor
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 365
- 238000012360 testing method Methods 0.000 title claims abstract description 178
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004364 calculation method Methods 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 8
- 238000004590 computer program Methods 0.000 claims description 6
- 238000010998 test method Methods 0.000 claims 3
- 235000012431 wafers Nutrition 0.000 description 104
- 238000001514 detection method Methods 0.000 description 10
- 230000000670 limiting effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000019771 cognition Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention relates to the technical field of semiconductor device testing, and discloses a method and a system for testing a semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor device testing, in particular to a method and a system for testing a semiconductor device.
Background
Semiconductor devices are electronic components manufactured using semiconductor materials for controlling, amplifying, switching or measuring currents and voltages, which are key components in modern electronic devices and are widely used in various fields.
Common semiconductor device types include: diodes, thyristors, transistors, integrated circuits, sensors, photovoltaic devices, etc.; in the production of semiconductor devices, it is common to reserve a part of the performance outside the performance parameters, i.e. the semiconductor device can be operated in an operating scenario outside the standard performance parameters, which is provided in order to ensure that the semiconductor device can be operated in an operating scenario outside the standard performance parameters.
In the prior art, a semiconductor testing apparatus is usually served by a semiconductor manufacturer, and is used for testing semiconductor devices at each stage in a production process of the semiconductor devices to determine whether the semiconductor devices in the manufacturing process meet standards, but for manufacturers of the semiconductor devices, the semiconductor devices lack detection equipment, and performance detection of the semiconductor devices cannot reach the depth of the semiconductor manufacturers.
Disclosure of Invention
The invention aims to provide a method and a system for testing a semiconductor device, which aim to solve the problem that a manufacturer using the semiconductor device in the prior art has lower detection depth of the semiconductor device.
The present invention is achieved in that, in a first aspect, the present invention provides a method for testing a semiconductor device, including:
acquiring model information of a semiconductor device, acquiring various performance parameters of the semiconductor device according to the model information of the semiconductor device, and generating a semiconductor wafer model of the semiconductor device according to the model information of the semiconductor device and the various performance parameters; the semiconductor wafer model is used for describing state information of a semiconductor wafer in the semiconductor device;
determining a limit working scene of the semiconductor device according to various performance parameters of the semiconductor device, constructing a first test circuit according to the limit working scene, testing circuit operation based on the first test circuit, and acquiring a first model parameter of the semiconductor wafer model according to a test result of the first test circuit;
performing a plurality of grades of performance reservation calculation on the basis of each performance parameter of the semiconductor device to obtain reserved working scenes of the performance reservation calculation of each grade of the semiconductor device, constructing a second test circuit according to each reserved working scene, performing a circuit operation test based on the second test circuit, and obtaining second model parameters of the semiconductor wafer model according to test results of the second test circuit;
substituting the first model parameter and the second model parameter into the semiconductor wafer model to obtain state data of the semiconductor wafer model.
Preferably, the step of generating the semiconductor wafer model of the semiconductor device according to the model information and various performance parameters of the semiconductor device includes:
acquiring model information of the semiconductor device, and calling corresponding semiconductor wafer lattice data in a preset database according to the model information of the semiconductor device and applying the corresponding semiconductor wafer lattice data in the semiconductor wafer model;
generating a performance tag of a semiconductor wafer model according to various performance parameters of the semiconductor device, and binding the performance tag with the semiconductor wafer model.
Preferably, determining a limit working scene of the semiconductor device according to each performance parameter of the semiconductor device, constructing a first test circuit according to the limit working scene, testing circuit operation based on the first test circuit, and obtaining a first model parameter of the semiconductor wafer model according to a test result of the first test circuit comprises:
determining limit performance parameters of the semiconductor device according to various performance parameters of the semiconductor device, and constructing a limit working scene of the semiconductor device according to the limit performance parameters; the limit operation scene is an operation scene in which the semiconductor device operates when the performance parameter is maintained at the limit performance parameter;
constructing the first test circuit according to the limit working scene, and testing the circuit operation of the first test circuit to obtain the operation state data of the first test circuit;
and judging the running state data according to a preset standard to acquire the actual performance parameter of the semiconductor device in the limit working scene, and taking the actual performance parameter as a first model parameter of the semiconductor wafer model.
Preferably, the step of performing performance reservation estimation of a plurality of levels based on each performance parameter of the semiconductor device to obtain a reserved working scenario of the performance reservation estimation of each level of the semiconductor device includes:
acquiring semiconductor crystal lattice data of the semiconductor device, and acquiring theoretical limit performance parameters of the corresponding semiconductor device according to the semiconductor crystal lattice data;
obtaining each performance parameter of the semiconductor device, carrying out difference calculation and classification on the theoretical limit performance parameter and the performance parameter, adding the difference value of each classification to the performance parameter, and obtaining the calculated performance parameter of the performance reservation calculation corresponding to each grade;
and respectively generating the corresponding reserved working scenes according to the calculated performance parameters calculated by the performance reservation of each level.
Preferably, the step of substituting the first model parameter and the second model parameter into the semiconductor wafer model to obtain the state data of the semiconductor wafer model includes:
substituting the first model parameter into the performance label in the semiconductor wafer model, and comparing the first model parameter with the performance parameter in the performance label to obtain basic state data of the semiconductor wafer model;
substituting second model parameters corresponding to performance reservation calculation of each grade into the performance labels in the semiconductor wafer model respectively, comparing the second model parameters with the performance parameters in the performance labels to obtain additional state data of the semiconductor wafer model, and superposing the additional state data with the basic state data to obtain the state data of the semiconductor wafer.
Preferably, the method further comprises:
randomly extracting a plurality of representative test pieces from the semiconductor devices in the same batch, and respectively testing each representative test piece to obtain the state data of the semiconductor wafer of each representative test piece;
and generating a mass distribution map of the semiconductor devices of the batch according to the state data of each representative test piece.
In a second aspect, the present invention provides a test system for a semiconductor device, comprising a memory and a processor, the memory storing a computer program executable on the processor, the processor implementing a method for testing a semiconductor device according to any one of the first aspects when executing the computer program.
Preferably, the test circuit device is further included;
the test circuit device is provided with a plurality of electronic element units and a plurality of circuit switch units, and the circuit switch units are used for controlling the connection and disconnection of the electronic element units so as to construct a first test circuit and a second test circuit;
the test circuit device is also provided with a plurality of mounting positions, and the mounting positions are used for setting the semiconductor devices.
Preferably, the method further comprises: clamping mechanical arm and image acquisition device; the clamping mechanical arm is used for clamping and moving the semiconductor device, and the image acquisition device is used for carrying out image recognition on the semiconductor device so as to acquire model information of the semiconductor device.
The invention provides a method for testing a semiconductor device, which has the following beneficial effects:
according to the invention, through the identification of the semiconductor device, the wafer specification and the performance parameters of the semiconductor device are obtained, so that the first round of test of the limit performance and the second round of test of the reserved performance are carried out on the semiconductor device, the state data of the semiconductor wafer are obtained through the test result, and compared with the simple sexual-life test of the semiconductor device, the semiconductor device can be subjected to deeper performance cognition, and the problem that the detection depth of the semiconductor device is lower by a manufacturer in the prior art is solved.
Drawings
Fig. 1 is a schematic diagram of steps of a testing method of a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The same or similar reference numerals in the drawings of the present embodiment correspond to the same or similar components; in the description of the present invention, it should be understood that, if there is an azimuth or positional relationship indicated by terms such as "upper", "lower", "left", "right", etc., based on the azimuth or positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus terms describing the positional relationship in the drawings are merely illustrative and should not be construed as limiting the present invention, and specific meanings of the terms described above may be understood by those of ordinary skill in the art according to specific circumstances.
The implementation of the present invention will be described in detail below with reference to specific embodiments.
Referring to FIG. 1, a preferred embodiment of the present invention is provided.
In a first aspect, the present invention provides a method for testing a semiconductor device, including:
s1: acquiring model information of a semiconductor device, acquiring various performance parameters of the semiconductor device according to the model information of the semiconductor device, and generating a semiconductor wafer model of the semiconductor device according to the model information of the semiconductor device and the various performance parameters; the semiconductor wafer model is used for describing state information of a semiconductor wafer in the semiconductor device;
s2: determining a limit working scene of the semiconductor device according to various performance parameters of the semiconductor device, constructing a first test circuit according to the limit working scene, testing circuit operation based on the first test circuit, and acquiring a first model parameter of the semiconductor wafer model according to a test result of the first test circuit;
s3: performing a plurality of grades of performance reservation calculation on the basis of each performance parameter of the semiconductor device to obtain reserved working scenes of the performance reservation calculation of each grade of the semiconductor device, constructing a second test circuit according to each reserved working scene, performing a circuit operation test based on the second test circuit, and obtaining second model parameters of the semiconductor wafer model according to test results of the second test circuit;
s4: substituting the first model parameter and the second model parameter into the semiconductor wafer model to obtain state data of the semiconductor wafer model.
Specifically, the testing method of the invention is oriented to the semiconductor device manufacturer, and for the semiconductor device manufacturer, the semiconductor wafer in the semiconductor device can not be tested in stages in the production process of the semiconductor device like the semiconductor manufacturer, and only the finished semiconductor device can be tested.
More specifically, the method provided by the invention is an automatic test scheme for semiconductor devices, and the main idea is as follows: the performance parameters marked on the semiconductor device are the performance parameters which the semiconductor device is supposed to bear, and a part of the performance is reserved in actual production, namely the semiconductor device can bear more limited functions in practice, a plurality of limit test circuits are built according to the performance parameters of the semiconductor device, a first round of test is carried out on the semiconductor device, a plurality of new test circuits are built according to the performance parameters which are estimated by the reserved space, a second round of test is carried out on the semiconductor device, and the state data of the semiconductor wafer is obtained through the results obtained by the two rounds of test.
Specifically, in step S1 provided by the present invention, model information of a semiconductor device is obtained, each performance parameter of the semiconductor device is obtained according to the model information of the semiconductor device, and a semiconductor wafer model of the semiconductor device is generated according to the model information of the semiconductor device and each performance parameter.
It should be noted that, the core part in the semiconductor device is a semiconductor wafer, and the state data of the semiconductor wafer represents how much the performance of the semiconductor device can be achieved.
More specifically, the semiconductor wafer model is a computational model that generates state data of a semiconductor wafer based on test data of subsequent first and second rounds of testing.
More specifically, the model signal of the semiconductor device may be obtained by the appearance and the surface marked model of the semiconductor device, and after the model information is obtained, the model information may be input into a preset database for searching, so as to obtain various performance parameters of the semiconductor device corresponding to the model information.
In the step S2 provided by the invention, the limit working scene of the semiconductor device is determined according to the performance parameters of each device of the semiconductor device, a first test circuit is constructed according to the limit working scene for testing, and the first model parameters of the semiconductor wafer model are obtained through the test result of the first test circuit.
Specifically, the performance parameter of the semiconductor device is usually a range value, the values of the edges of the range values are limit values that can be achieved by the semiconductor device in a standard working state, the generation of a limit working scene is performed based on the limit values, and the limit working scene is a working scene in which the performance of the semiconductor device is kept to work under the limit values, so that the requirements of other electronic components electrically connected with the semiconductor device can be deduced through the limit working scene, and when the electronic components meeting the requirements are electrically connected with the semiconductor device to construct a complete circuit, the performance of the semiconductor device is kept at the limit performance parameter when the circuit works.
More specifically, the device for performing the first round test and the second round test on the semiconductor device in the present invention is an automatic device, that is, various electronic components are integrated, and the connection and disconnection between the electronic components are controlled by a switch, so that different test circuits can be formed, and the semiconductor device is required to bear the working performance of a limit value by adjusting the type and model of the electronic components used for constructing the test circuits and the connection relation between the electronic components, for example: when the semiconductor device is a diode, one of the limit values is reverse breakdown voltage, the diode cannot be broken down before the voltage rises to the reverse breakdown voltage, the circuit is broken, if the diode is broken down, the circuit is short-circuited, the first test circuit applies the reverse voltage of the limit value to the diode, and the test circuit is broken during normal operation.
More specifically, the first test circuit is a circuit for realizing a limit operation scenario, and the limit operation scenario corresponding to each limit value of the semiconductor device is configured by automatically switching on and off each electronic component on the test apparatus, respectively, so that the limit number operation performance of the semiconductor device is detected.
More specifically, in step S1, the recognition of the model information of the semiconductor device may be performed by using the clamping mechanical arm in combination with the image capturing device, and after the recognition of the model information of the semiconductor device is completed, the semiconductor device may be set at a corresponding position in the testing device by using the clamping mechanical arm to perform a subsequent test.
In step S3 provided by the present invention, on the basis of each performance parameter of the semiconductor device, a plurality of levels of performance reservation computation is performed to obtain reserved working scenes of the performance reservation computation of each level of the semiconductor device, a second test circuit is constructed according to each reserved working scene for testing, and a second model parameter of the semiconductor wafer model is obtained according to the test result of the second test circuit.
Specifically, during production of the semiconductor device, a certain space is generally reserved for the performance, that is, the actual limiting performance of the semiconductor device is larger than the standard limiting value, and the state data of the semiconductor wafer in the semiconductor device can be fed back through detection of the actual limiting performance.
More specifically, in order to detect the influence of the reserved performance of the semiconductor wafer on the state data of the semiconductor wafer, a plurality of levels of performance reservation estimation are performed on the basis of the performance parameters of the semiconductor wafer, the performance reservation estimation of different levels represents that the semiconductor wafer reserves different degrees of performance space, the semiconductor wafer reserved with different degrees of performance space has different state data, and further, the service life, the working environment adaptability, the aging durability and the like of the semiconductor wafer with different state data have different performances.
More specifically, through the performance reservation computation of a plurality of grades, reservation working scenes of the performance reservation computation of the semiconductor device corresponding to each grade are obtained, and the reservation working scenes respectively correspond to one performance reservation computation of the semiconductor device.
More specifically, the steps of constructing the second test circuit according to the reserved operating scenario are similar to those of constructing the first test circuit according to the performance parameter of the limit value, and thus will not be described herein.
More specifically, the second model parameters of the semiconductor wafer model may be obtained through the test result of the second test circuit, and the first model parameters and the second model parameters are substituted into the semiconductor wafer model, so as to obtain the state data of the semiconductor wafer based on the semiconductor wafer model.
The invention provides a method for testing a semiconductor device, which has the following beneficial effects:
according to the invention, through the identification of the semiconductor device, the wafer specification and the performance parameters of the semiconductor device are obtained, so that the first round of test of the limit performance and the second round of test of the reserved performance are carried out on the semiconductor device, the state data of the semiconductor wafer are obtained through the test result, and compared with the simple sexual-life test of the semiconductor device, the semiconductor device can be subjected to deeper performance cognition, and the problem that the detection depth of the semiconductor device is lower by a manufacturer in the prior art is solved.
Preferably, the step of generating the semiconductor wafer model of the semiconductor device according to the model information and various performance parameters of the semiconductor device includes:
s11: acquiring model information of the semiconductor device, and calling corresponding semiconductor wafer lattice data in a preset database according to the model information of the semiconductor device and applying the corresponding semiconductor wafer lattice data in the semiconductor wafer model;
s12: generating a performance tag of a semiconductor wafer model according to various performance parameters of the semiconductor device, and binding the performance tag with the semiconductor wafer model.
Specifically, semiconductor wafers in different semiconductor devices are molded into different shapes, correspondence between model information of the semiconductor devices and specification data of the semiconductor wafers in the model information is stored in a preset database, the data of the semiconductor wafers are obtained through searching the database, the data are applied to a semiconductor wafer model, and a basic model of the semiconductor wafer is built through the specification data of the semiconductor wafers.
More specifically, the semiconductor wafer lattice data is used to describe basic specification information such as the shape, size, thickness, etc. of the semiconductor wafer, and the specification of the semiconductor wafer has a limiting effect on the function of the semiconductor wafer, that is, the performance of the semiconductor wafer cannot exceed the upper limit limited by the specification of the semiconductor wafer, and in the second round of testing, the calculation of the reserved performance of the semiconductor wafer is required, and the calculated performance space needs to refer to the specification data of the semiconductor wafer itself.
More specifically, a performance tag of a semiconductor wafer model is generated according to each performance parameter of the semiconductor wafer, and the performance tag is bound to the semiconductor wafer model, where in step S4, the performance tag is used to describe the performance of the semiconductor wafer, and in other words, the first model parameter and the second model parameter are substituted into the semiconductor wafer model, that is, the performance of the working performance of the limit value of the semiconductor wafer and the test performance of the reserved performance space are added to the performance tag, and the state of the semiconductor wafer is fed back through the difference between the actual limit performance and the reserved performance of the semiconductor device and the labeling performance.
Preferably, determining a limit working scene of the semiconductor device according to each performance parameter of the semiconductor device, constructing a first test circuit according to the limit working scene, testing circuit operation based on the first test circuit, and obtaining a first model parameter of the semiconductor wafer model according to a test result of the first test circuit comprises:
s21: determining limit performance parameters of the semiconductor device according to various performance parameters of the semiconductor device, and constructing a limit working scene of the semiconductor device according to the limit performance parameters; the limit operation scene is an operation scene in which the semiconductor device operates when the performance parameter is maintained at the limit performance parameter;
s22: constructing the first test circuit according to the limit working scene, and testing the circuit operation of the first test circuit to obtain the operation state data of the first test circuit;
s23: and judging the running state data according to a preset standard to acquire the actual performance parameter of the semiconductor device in the limit working scene, and taking the actual performance parameter as a first model parameter of the semiconductor wafer model.
Specifically, the performance parameter of the semiconductor device is typically a range of values, and the values of the edges of the range of values are limit values that the semiconductor device can achieve in a standard operating state, and the generation of a limit operation scene is performed based on the limit values, where the performance of the semiconductor device is kept to operate at the limit values.
More specifically, the corresponding first test circuit is constructed according to the working scene, and since there are a plurality of performance parameters to be tested of the semiconductor device, there are a plurality of corresponding first test circuits, and the test of the semiconductor device by the first test circuit also needs to be performed in a plurality of times.
More specifically, the working scenario can be regarded as two parts, one is a semiconductor device, and the other is a peripheral circuit electrically connected with the semiconductor device, and by setting parameters of the peripheral circuit, the semiconductor device can work with limit performance parameters when the semiconductor device is electrically connected with the peripheral circuit to form a complete circuit and works, and according to the parameters set by the peripheral circuit, it can be deduced which electronic elements are required to form the peripheral circuit.
More specifically, after the semiconductor device is tested by the first test circuit, the operation state data of the first test circuit is obtained according to the test result, that is, whether the first test circuit can normally operate, if the first test circuit can normally operate, the performance parameter representing the limit value can be born by the semiconductor device, and if the first test circuit cannot normally operate, the performance parameter representing the limit value cannot be born by the semiconductor device.
More specifically, the first test circuit operates to detect whether the semiconductor device is in charge of the detection by detecting whether the first test circuit is operating normally, for example: when the semiconductor device is a diode, one of the limit values is reverse breakdown voltage, the diode cannot be broken down before the voltage rises to the reverse breakdown voltage, the circuit is kept open, if the diode is broken down, the circuit is short-circuited, the first test circuit applies the reverse voltage of the limit value to the diode at the moment, and the test circuit is open in normal operation, that is, the detection of the operation state of the first test circuit is to perform corresponding information acquisition on the first test circuit according to the function and effect of the first test circuit.
More specifically, the operation state data is judged according to a preset standard to obtain the working completion degree of the semiconductor device in the first test circuit, and it can be understood that the better the operation state data of the first test circuit is, the higher the working completion degree of the semiconductor device in the first test circuit is, and the working completion degree of the semiconductor device in the first test circuit can be used for feeding back the actual performance parameter of the semiconductor device in a limited working scene, and the actual performance parameter can be used as a first model parameter to feed back the performance parameter of the semiconductor wafer in the semiconductor device, which can meet the marking.
Preferably, the step of performing performance reservation estimation of a plurality of levels based on each performance parameter of the semiconductor device to obtain a reserved working scenario of the performance reservation estimation of each level of the semiconductor device includes:
s31: acquiring semiconductor crystal lattice data of the semiconductor device, and acquiring theoretical limit performance parameters of the corresponding semiconductor device according to the semiconductor crystal lattice data;
s32: obtaining each performance parameter of the semiconductor device, carrying out difference calculation and classification on the theoretical limit performance parameter and the performance parameter, adding the difference value of each classification to the performance parameter, and obtaining the calculated performance parameter of the performance reservation calculation corresponding to each grade;
s31: and respectively generating the corresponding reserved working scenes according to the calculated performance parameters calculated by the performance reservation of each level.
Specifically, in step S1, semiconductor wafer lattice data of the semiconductor device is obtained, and the semiconductor wafer lattice data determines an upper limit of a performance parameter of the semiconductor wafer, that is, a reserved performance space of the semiconductor device does not exceed a difference between the upper limit of performance determined by the semiconductor wafer lattice data and the performance parameter of the semiconductor label.
More specifically, the corresponding theoretical limit performance parameter, that is, the highest performance parameter that can be achieved under the semiconductor crystal lattice data is obtained through the semiconductor crystal lattice data of the semiconductor device, on the basis, the numerical value and the performance parameter in the limit state of the semiconductor in S2 are subjected to difference calculation, the obtained difference is graded, the difference of different grades represents different grades of performance reserved space, and the difference of each grade is added with the performance parameter, so that the calculated performance parameter corresponding to the performance reserved calculation of each grade can be obtained.
More specifically, after each estimated performance parameter is obtained by calculation, a corresponding reserved working scene is generated according to the estimated performance parameters.
Preferably, the step of substituting the first model parameter and the second model parameter into the semiconductor wafer model to obtain the state data of the semiconductor wafer model includes:
s41: substituting the first model parameter into the performance label in the semiconductor wafer model, and comparing the first model parameter with the performance parameter in the performance label to obtain basic state data of the semiconductor wafer model;
s42: substituting second model parameters corresponding to performance reservation calculation of each grade into the performance labels in the semiconductor wafer model respectively, comparing the second model parameters with the performance parameters in the performance labels to obtain additional state data of the semiconductor wafer model, and superposing the additional state data with the basic state data to obtain the state data of the semiconductor wafer.
Specifically, the basic state data of the semiconductor wafer model is used for describing the working performance state of the semiconductor wafer in the limit value of the marked performance parameter, that is, the basic function detection is performed on the semiconductor wafer, and if the semiconductor wafer cannot reach the standard, the performance of the semiconductor device is not in accordance with the requirement.
More specifically, each second model parameter corresponds to each level of performance reservation computation, and it can be understood that the performance reservation computation is classified into two types, one type is the actual performance reservation of the semiconductor device, and the other type is non-conforming, and according to whether the computation is conforming or not, the performance reservation computation can be obtained through comparing feedback of the second model parameter and the performance parameter summarized by the performance label.
More specifically, the results obtained by sequentially comparing the second model parameters generate additional state data, and the additional state data is superimposed with the basic state data to generate state data of the semiconductor wafer, where the state data of the semiconductor wafer is used to describe a range of actual working performance that can be borne by the semiconductor wafer, an actual reserved performance space of the semiconductor wafer, and advantages that can be brought by the reserved performance space.
Preferably, the method further comprises:
s51: randomly extracting a plurality of representative test pieces from the semiconductor devices in the same batch, and respectively testing each representative test piece to obtain the state data of the semiconductor wafer of each representative test piece;
s52: and generating a mass distribution map of the semiconductor devices of the batch according to the state data of each representative test piece.
Specifically, when testing of semiconductor devices of the same batch is required, it is not necessary to test each semiconductor device of the batch, but some representative test pieces are randomly extracted to perform sampling detection.
More specifically, the quality of the batch of semiconductor devices can be representatively described by the distribution of the state data representing the test piece.
In a second aspect, the present invention provides a system for testing a semiconductor device, comprising a memory and a processor, the memory storing a computer program executable on the processor, the processor implementing a method for testing a semiconductor device according to any one of the first aspects when executing the computer program.
Preferably, the test circuit device is further included; the test circuit device is provided with a plurality of electronic element units and a plurality of circuit switch units, and the circuit switch units are used for controlling the connection and disconnection of the electronic element units so as to construct a first test circuit and a second test circuit; the test circuit device is also provided with a plurality of mounting positions for mounting the semiconductor devices.
Preferably, the method further comprises: clamping mechanical arm and image acquisition device; the clamping mechanical arm is used for clamping and moving the semiconductor device, and the image acquisition device is used for carrying out image recognition on the semiconductor device so as to acquire model information of the semiconductor device.
The principle and the operation of the above parts are described in the first aspect, and are not described in detail herein.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (9)
1. A method of testing a semiconductor device, comprising:
acquiring model information of a semiconductor device, acquiring various performance parameters of the semiconductor device according to the model information of the semiconductor device, and generating a semiconductor wafer model of the semiconductor device according to the model information of the semiconductor device and the various performance parameters; the semiconductor wafer model is used for describing state information of a semiconductor wafer in the semiconductor device;
determining a limit working scene of the semiconductor device according to various performance parameters of the semiconductor device, constructing a first test circuit according to the limit working scene, testing circuit operation based on the first test circuit, and acquiring a first model parameter of the semiconductor wafer model according to a test result of the first test circuit;
performing a plurality of grades of performance reservation calculation on the basis of each performance parameter of the semiconductor device to obtain reserved working scenes of the performance reservation calculation of each grade of the semiconductor device, constructing a second test circuit according to each reserved working scene, performing a circuit operation test based on the second test circuit, and obtaining second model parameters of the semiconductor wafer model according to test results of the second test circuit;
substituting the first model parameter and the second model parameter into the semiconductor wafer model to obtain state data of the semiconductor wafer model.
2. The method of testing a semiconductor device according to claim 1, wherein the step of generating a semiconductor wafer model of the semiconductor device based on model information and performance parameters of the semiconductor device comprises:
acquiring model information of the semiconductor device, and calling corresponding semiconductor wafer lattice data in a preset database according to the model information of the semiconductor device and applying the corresponding semiconductor wafer lattice data in the semiconductor wafer model;
generating a performance tag of a semiconductor wafer model according to various performance parameters of the semiconductor device, and binding the performance tag with the semiconductor wafer model.
3. The method for testing a semiconductor device according to claim 1, wherein the steps of determining a limit operation scenario of the semiconductor device according to each performance parameter of the semiconductor device, constructing a first test circuit according to the limit operation scenario, performing a test of circuit operation based on the first test circuit, and acquiring a first model parameter of the semiconductor wafer model from a test result of the first test circuit comprise:
determining limit performance parameters of the semiconductor device according to various performance parameters of the semiconductor device, and constructing a limit working scene of the semiconductor device according to the limit performance parameters; the limit operation scene is an operation scene in which the semiconductor device operates when the performance parameter is maintained at the limit performance parameter;
constructing the first test circuit according to the limit working scene, and testing the circuit operation of the first test circuit to obtain the operation state data of the first test circuit;
and judging the running state data according to a preset standard to acquire the actual performance parameter of the semiconductor device in the limit working scene, and taking the actual performance parameter as a first model parameter of the semiconductor wafer model.
4. The method for testing a semiconductor device according to claim 2, wherein the step of performing a plurality of levels of performance reservation computation based on each performance parameter of the semiconductor device to obtain a reservation operation scenario of the performance reservation computation of the semiconductor device corresponding to each level comprises:
acquiring semiconductor crystal lattice data of the semiconductor device, and acquiring theoretical limit performance parameters of the corresponding semiconductor device according to the semiconductor crystal lattice data;
obtaining each performance parameter of the semiconductor device, carrying out difference calculation and classification on the theoretical limit performance parameter and the performance parameter, adding the difference value of each classification to the performance parameter, and obtaining the calculated performance parameter of the performance reservation calculation corresponding to each grade;
and respectively generating the corresponding reserved working scenes according to the calculated performance parameters calculated by the performance reservation of each level.
5. The method of testing a semiconductor device according to claim 4, wherein substituting the first model parameter and the second model parameter into the semiconductor wafer model to obtain the state data of the semiconductor wafer model comprises:
substituting the first model parameter into the performance label in the semiconductor wafer model, and comparing the first model parameter with the performance parameter in the performance label to obtain basic state data of the semiconductor wafer model;
substituting second model parameters corresponding to performance reservation calculation of each grade into the performance labels in the semiconductor wafer model respectively, comparing the second model parameters with the performance parameters in the performance labels to obtain additional state data of the semiconductor wafer model, and superposing the additional state data with the basic state data to obtain the state data of the semiconductor wafer.
6. The method for testing a semiconductor device according to claim 1, further comprising:
randomly extracting a plurality of representative test pieces from the semiconductor devices in the same batch, and respectively testing each representative test piece to obtain the state data of the semiconductor wafer of each representative test piece;
and generating a mass distribution map of the semiconductor devices of the batch according to the state data of each representative test piece.
7. A test system for a semiconductor device, comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that the processor implements a method for testing a semiconductor device according to any one of claims 1 to 6 when executing the computer program.
8. A system for testing a semiconductor device according to claim 7, further comprising test circuit means;
the test circuit device is provided with a plurality of electronic element units and a plurality of circuit switch units, and the circuit switch units are used for controlling the connection and disconnection of the electronic element units so as to construct a first test circuit and a second test circuit;
the test circuit device is also provided with a plurality of mounting positions, and the mounting positions are used for setting the semiconductor devices.
9. A semiconductor device testing system according to claim 7, further comprising: clamping mechanical arm and image acquisition device; the clamping mechanical arm is used for clamping and moving the semiconductor device, and the image acquisition device is used for carrying out image recognition on the semiconductor device so as to acquire model information of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311597546.5A CN117316801B (en) | 2023-11-28 | 2023-11-28 | Method and system for testing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311597546.5A CN117316801B (en) | 2023-11-28 | 2023-11-28 | Method and system for testing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117316801A true CN117316801A (en) | 2023-12-29 |
| CN117316801B CN117316801B (en) | 2024-03-15 |
Family
ID=89255548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311597546.5A Active CN117316801B (en) | 2023-11-28 | 2023-11-28 | Method and system for testing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117316801B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110727721A (en) * | 2018-06-28 | 2020-01-24 | 瑞萨电子株式会社 | Semiconductor device, semiconductor product quality management server and system |
| CN115906732A (en) * | 2022-11-28 | 2023-04-04 | 摩尔线程智能科技(北京)有限责任公司 | Method and device for establishing scenized CPM model and machine-readable storage medium |
| CN116338434A (en) * | 2023-04-06 | 2023-06-27 | 展讯半导体(成都)有限公司 | Average power consumption measuring method and device |
| CN116359700A (en) * | 2023-03-31 | 2023-06-30 | 安徽信诺达微电子有限公司 | Semiconductor electrical performance parameter detection system |
| CN116884864A (en) * | 2023-05-22 | 2023-10-13 | 弘润半导体(苏州)有限公司 | Failure analysis method of semiconductor device |
-
2023
- 2023-11-28 CN CN202311597546.5A patent/CN117316801B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110727721A (en) * | 2018-06-28 | 2020-01-24 | 瑞萨电子株式会社 | Semiconductor device, semiconductor product quality management server and system |
| CN115906732A (en) * | 2022-11-28 | 2023-04-04 | 摩尔线程智能科技(北京)有限责任公司 | Method and device for establishing scenized CPM model and machine-readable storage medium |
| CN116359700A (en) * | 2023-03-31 | 2023-06-30 | 安徽信诺达微电子有限公司 | Semiconductor electrical performance parameter detection system |
| CN116338434A (en) * | 2023-04-06 | 2023-06-27 | 展讯半导体(成都)有限公司 | Average power consumption measuring method and device |
| CN116884864A (en) * | 2023-05-22 | 2023-10-13 | 弘润半导体(苏州)有限公司 | Failure analysis method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117316801B (en) | 2024-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7689876B2 (en) | Real-time optimized testing of semiconductor device | |
| CN104321659B (en) | Method and device for testing electric energy accumulation systems for driving vehicles | |
| CN105842559A (en) | Test result write-in method, test result write-in device, testing system and mobile terminal | |
| CN109429264A (en) | A kind of data processing method, device, equipment and computer readable storage medium | |
| CN117316801B (en) | Method and system for testing semiconductor device | |
| CN115239626A (en) | Defect detection method, optical detection device, electronic device, and storage medium | |
| CN110795817A (en) | Laboratory data processing method and processing system | |
| US20160282418A1 (en) | Process for Auto-Testing a Fully Discharged Battery, Such as Double-Layer Capacitor Battery, and Circuit for Doing the Same | |
| CN112256555A (en) | Automatic test case management system and test case execution state conversion method | |
| CN108539862B (en) | Electric power operation auxiliary method and device | |
| CN110443777B (en) | PCB image alignment method and device and computer storage medium | |
| CN106990343B (en) | The test method and system of electronic component | |
| US6590408B1 (en) | Microelectronic fabrication electrical test apparatus and method providing enhanced electrical test accuracy | |
| CN115483759A (en) | Operation and maintenance control management system for high-voltage power transmission power grid | |
| CN111368928B (en) | Wafer pattern matching method and device, electronic equipment and storage medium | |
| CN103972122A (en) | Wafer probing method and wafer probing device | |
| CN111458628A (en) | Template file updating method, device, equipment and computer readable storage medium | |
| CN117250467B (en) | Silicon carbide diode fault diagnosis method and related device | |
| CN106409204A (en) | Display screen parameter setting method and device | |
| Fabrice et al. | SMD Detection and Classification Using YOLO Network Based on Robust Data Preprocessing and Augmentation Techniques | |
| US20230368637A1 (en) | Adaptive automated alarm response system | |
| CN114234816B (en) | New energy vehicle-mounted connector connection test method, system and storage medium | |
| CN115407178A (en) | Integrated circuit power consumption evaluation method, system, computer and readable storage medium | |
| CN219799614U (en) | Battery management system testing arrangement | |
| CN217638759U (en) | Chip production automatic detection system based on optics CCD module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |