CN117316091A

CN117316091A - Pixel circuit and driving method thereof, display panel and driving method thereof

Info

Publication number: CN117316091A
Application number: CN202210713273.5A
Authority: CN
Inventors: 李洋; 李云泽; 万宝红; 汪浩
Original assignee: Chengdu Vistar Optoelectronics Co Ltd
Current assignee: Chengdu Vistar Optoelectronics Co Ltd
Priority date: 2022-06-22
Filing date: 2022-06-22
Publication date: 2023-12-29

Abstract

The embodiment of the invention discloses a pixel circuit and a driving method thereof, a display panel and a driving method thereof. The pixel circuit includes: the device comprises a first driving module, a second driving module, a light-emitting control module and a light-emitting module. The first driving module is used for responding to the first data signal in each subframe to generate driving current with corresponding amplitude so as to drive the light emitting module to emit light. The second driving module is used for responding to the second data signal and turning on or off in each subframe, and the light-emitting control module is used for responding to the light-emitting control signal and turning on in corresponding time length in each subframe so as to control the light-emitting time of the light-emitting module in each subframe through the second driving module and the light-emitting control module, thereby controlling the light-emitting brightness of the light-emitting module in one frame. The technical scheme of the embodiment of the invention realizes the digital-analog hybrid driving of the pixel circuit, is beneficial to improving the color cast problem, is beneficial to simplifying the structure of the pixel circuit, improves the sub-pixel density of the display panel and realizes high PPI.

Description

Pixel circuit and driving method thereof, display panel and driving method thereof

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a driving method thereof, a display panel and a driving method thereof.

Background

With the continuous development of display technology, display performance requirements of display panels are increasing. The display panel includes pixel circuits, and the pixel circuits are driven in a plurality of modes, and one mode is a driving mode in which digital driving and analog driving are combined (abbreviated as digital-analog hybrid driving). At present, the existing digital-analog hybrid driving pixel circuit has a complex structure, so that the density of the sub-pixels of the display panel is low, the color cast and other problems are easy to cause, and the display effect of the display panel is affected.

Disclosure of Invention

The embodiment of the invention provides a pixel circuit, a driving method thereof, a display panel and a driving method thereof, which are used for improving the color cast problem and simplifying the structure of the pixel circuit while realizing digital-analog hybrid driving of the pixel circuit so as to improve the sub-pixel density of the display panel and realize high PPI.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the light-emitting device comprises a first driving module, a second driving module, a light-emitting control module and a light-emitting module, wherein the first driving module, the second driving module, the light-emitting control module and the light-emitting module are connected in series between a first power line and a second power line;

The first driving module is used for responding to a first data signal to generate driving current with corresponding amplitude in each subframe in a plurality of subframes contained in one frame so as to drive the light emitting module to emit light; wherein the first data signal is a pulse amplitude modulation signal;

the second driving module is used for responding to a second data signal and turning on or off in each subframe, the light-emitting control module is used for responding to a light-emitting control signal in each subframe and turning on in a corresponding time length so as to control the light-emitting time of the light-emitting module in each subframe through the second driving module and the light-emitting control module, and therefore the light-emitting brightness of the light-emitting module in one frame is controlled;

the second data signal in each subframe is a high level signal or a low level signal, and pulse widths of on level signals in the light-emitting control signals are different in different subframes of the same frame.

Optionally, each of the subframes includes a data writing phase and a light emitting phase; the second driving module comprises a first driving unit and a first data writing unit;

the first data writing unit is connected with the control end of the first driving unit and is used for responding to a first scanning signal and writing the second data signal into the control end of the first driving unit in the data writing stage of each subframe;

The first driving unit is connected in series between the first power line and the second power line and is used for being turned on or turned off in response to a signal of a control end of the first driving unit in a light emitting stage of each subframe;

preferably, the first driving unit includes a first driving transistor, and the first data writing unit includes a first transistor; the first driving transistor is connected in series between the first power line and the second power line, a gate electrode of the first transistor is connected with the first scanning signal, a first electrode of the first transistor is connected with the second data signal, and a second electrode of the first transistor is connected with the gate electrode of the first driving transistor;

preferably, the second driving module further comprises a first storage unit, a first end of the first storage unit is connected with a fixed voltage, and a second end of the first storage unit is connected with a control end of the first driving unit;

preferably, the first storage unit includes a first capacitor, a first pole of the first capacitor is connected to the fixed voltage, and a second pole of the first capacitor is connected to a control end of the first driving unit.

Optionally, in one frame, pulse widths of the light emission control signals in the light emission stage of each of the subframes are different, and pitches between pulse signals in the first scan signals in the data writing stage of adjacent subframes are different.

Optionally, each of the subframes further includes an initialization phase; the second driving module further comprises a first initializing unit;

the first initialization unit is connected with the control end of the first driving unit and is used for responding to a second scanning signal and writing a first initialization signal into the control end of the first driving unit in the initialization stage of each subframe so as to control the first driving unit to be turned off;

preferably, the first initializing unit includes a second transistor, a gate of the second transistor is connected to the second scan signal, a first pole of the second transistor is connected to the first initializing signal, and a second pole of the second transistor is connected to a control end of the first driving unit;

preferably, in one frame, the intervals between pulse signals in the second scan signals in the initialization stage of adjacent subframes are different.

Optionally, each of the subframes includes a data writing phase and a light emitting phase; the first driving module comprises a second driving unit and a second data writing unit;

the second data writing unit is connected with the second driving unit and is used for responding to a third scanning signal and writing the first data signal to the control end of the second driving unit in the data writing stage of each subframe;

The second driving unit is connected in series between the first power line and the second power line and is used for responding to a signal of a control end of the second driving unit in a light-emitting stage of each subframe to generate driving current with corresponding amplitude so as to drive the light-emitting module to emit light;

preferably, the second driving unit includes a second driving transistor, and the second data writing unit includes a third transistor; the second driving transistor is connected in series between the first power line and the second power line, a gate electrode of the third transistor is connected with the third scanning signal, a first electrode of the third transistor is connected with the first data signal, and a second electrode of the third transistor is connected with the second driving transistor;

preferably, in one frame, the intervals between pulse signals in the third scan signals of the data writing stage of adjacent subframes are different;

preferably, each of the subframes further includes an initialization phase; the first driving module further comprises a threshold compensation unit, a second initialization unit and a second storage unit; the second end of the second data writing unit is connected with the first end of the second driving unit, the threshold compensation unit is connected between the second end and the control end of the second driving unit, and the threshold compensation unit is used for compensating the threshold voltage of the second driving unit in response to the third scanning signal; the second initializing unit is connected with the control end of the second driving unit and is used for responding to a second scanning signal and writing a second initializing signal into the control end of the second driving unit in the initializing stage of each subframe; the first end of the second storage unit is connected with a fixed voltage, and the second end of the second storage unit is connected with the control end of the second driving unit;

Preferably, the threshold compensation unit includes a fourth transistor, the second initialization unit includes a fifth transistor, and the second storage unit includes a second capacitor; the grid electrode of the fourth transistor is connected with the third scanning signal, and the fourth transistor is connected between the second end and the control end of the second driving unit; the grid electrode of the fifth transistor is connected with the second scanning signal, the first electrode of the fifth transistor is connected with the second initializing signal, and the second electrode of the fifth transistor is connected with the control end of the second driving unit; the first end of the second capacitor is connected to the fixed voltage, and the second end of the second capacitor is connected with the control end of the second driving unit.

Optionally, the light emitting control module includes a sixth transistor, the light emitting module includes a light emitting device, the sixth transistor and the light emitting device are connected in series between the first power line and the second power line, and a gate of the sixth transistor is connected to the light emitting control signal.

In a second aspect, an embodiment of the present invention further provides a driving method of a pixel circuit, where the pixel circuit includes: the light-emitting device comprises a first driving module, a second driving module, a light-emitting control module and a light-emitting module, wherein the first driving module, the second driving module, the light-emitting control module and the light-emitting module are connected in series between a first power line and a second power line;

The driving method of the pixel circuit comprises the following steps:

dividing a frame into a plurality of subframes;

generating a driving current with corresponding amplitude in response to a first data signal in each subframe through the first driving module so as to drive the light emitting module to emit light; wherein the first data signal is a pulse amplitude modulation signal;

the second driving module is turned on or off in each subframe in response to a second data signal, and the light-emitting control module is turned on in each subframe in response to a light-emitting control signal for a corresponding time length, so that the light-emitting time of the light-emitting module in each subframe is controlled through the second driving module and the light-emitting control module, and the light-emitting brightness of the light-emitting module in one frame is controlled;

Optionally, each of the subframes includes a data writing phase and a light emitting phase; the second driving module comprises a first driving unit and a first data writing unit; the first driving module comprises a second driving unit and a second data writing unit; the first data writing unit is connected with the control end of the first driving unit, and the first driving unit is connected in series between the first power line and the second power line; the second data writing unit is connected with the second driving unit, and the second driving unit is connected in series between the first power line and the second power line;

The driving method of the pixel circuit specifically comprises the following steps:

in the data writing stage of each subframe, writing the second data signal to the control end of the first driving unit through the first data writing unit in response to a first scanning signal, and writing the first data signal to the control end of the second driving unit through the second data writing unit in response to a third scanning signal;

in the light-emitting stage of each subframe, the second driving unit responds to the signal of the control end of the second driving unit to generate driving current with corresponding amplitude so as to drive the light-emitting module to emit light, the first driving unit responds to the signal of the control end of the second driving unit to turn on or off, and the light-emitting control module responds to the light-emitting control signal to turn on at corresponding time length so as to control the light-emitting time of the light-emitting module in each subframe through the first driving unit and the light-emitting control module, thereby controlling the light-emitting brightness of the light-emitting module in one frame;

preferably, each of the subframes further includes an initialization phase; the second driving module further comprises a first initializing unit, and the first initializing unit is connected with the control end of the first driving unit; the first driving module further comprises a second initializing unit, and the second initializing unit is connected with the control end of the second driving unit; the driving method of the pixel circuit further includes:

In the initialization stage of each subframe, a first initialization signal is written into the control end of the first driving unit through the first initialization unit in response to a second scanning signal so as to control the first driving unit to be turned off, and a second initialization signal is written into the control end of the second driving unit through the second initialization unit in response to a second scanning signal.

In a third aspect, an embodiment of the present invention further provides a display panel, including a plurality of rows of the pixel circuits according to the first aspect.

In a fourth aspect, an embodiment of the present invention further provides a driving method of a display panel, for driving the display panel according to the third aspect to work, where the driving method of the display panel includes:

and controlling the pixel circuits to drive the light-emitting modules in sequence in each subframe in a frame, and controlling the pixel circuits in each row to drive the light-emitting modules in each row in a frame.

In the pixel circuit, the driving method thereof, the display panel and the driving method thereof provided by the embodiment of the invention, in the light-emitting stage of each subframe, the first driving module responds to the first data signal to generate the driving current with corresponding amplitude so as to control the magnitude of the driving current flowing through the light-emitting module, the second driving module responds to the second data signal to conduct or turn off, and the light-emitting control module responds to the light-emitting control signal to conduct with the time length corresponding to the subframe so as to control whether a current path is formed between the first power line and the second power line, thereby controlling whether the light-emitting module emits light and the light-emitting time length in the light-emitting stage of each subframe, and realizing digital driving. The brightness of the light emitting module in each subframe can be jointly determined by controlling the driving current flowing through the light emitting module and controlling the light emitting time of the light emitting module, so that the integral brightness of the light emitting module in one frame is controlled by controlling the brightness of the light emitting module in each subframe, and the digital-analog hybrid driving is realized.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

1) The second data signal is a high-level signal or a low-level signal, so that the state of the second driving module only comprises a conducting state and a switching-off state, and an intermediate state between the conducting state and the switching-off state does not exist, and therefore the state of the second driving module does not gradually change the magnitude of the driving current, and the color cast problem of the light emitting module is improved; 2) The whole structure of the pixel circuit is simple, and the second driving module does not have an intermediate state, and a structure for carrying out threshold voltage compensation on the second driving module is not needed, so that the structure of the pixel circuit is simplified, the density of sub-pixels of the display panel is improved, and high PPI is realized; 3) By adopting the subframe control mode, data writing and light emission can be performed in each subframe, and the light emission and lighting are not required after all pixel circuits in the display panel complete data writing, so that the data signal holding time required by the pixel circuits is shortened, and the problem of flicker is relieved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a digital-analog hybrid driving pixel circuit in the related art;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a driving timing diagram of a pixel circuit according to an embodiment of the present invention;

Fig. 10 is a flowchart of a driving method of a pixel circuit according to an embodiment of the invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As described in the background art, the existing digital-analog hybrid driving pixel circuit has a complex structure, so that the density of the sub-pixels of the display panel is low, and the problems of color shift and the like are easily caused, thereby influencing the display effect of the display panel. The inventors found that the cause of the above problems is specifically as follows:

the pixel circuit of the digital-analog hybrid driving refers to a pixel circuit of a combination of pulse width modulation (Pulse Width Modulation, PWM) driving (i.e., digital driving) and pulse amplitude modulation (Pulse Amplitude Modulation, PAM) driving (i.e., analog driving), which commonly controls the luminance of the light emitting device by controlling the current and the light emitting time of the light emitting device. Fig. 1 is a schematic diagram of a structure of a digital-analog hybrid driving pixel circuit in the related art, in which only a part of the structure of the pixel circuit is shown. Illustratively, referring to fig. 1, the pixel circuit includes a PWM driving module 01 and a PAM driving module 02, the PWM driving module 01 includes at least a coupling capacitor C0 and a driving transistor M1, and the PAM driving module 02 includes at least a driving transistor M2 and a data writing transistor M3. The PAM driving module 02 writes the Data voltage Data to the gate of the driving transistor M2 through the Data writing transistor M3 to control the magnitude of the driving current provided to the light emitting device D0 by the driving transistor M2 through the Data voltage Data, and the PWM driving module 01 couples the ramp signal Sweep to the gate of the driving transistor M1 through the coupling capacitor C0 to control the time when the driving transistor M1 writes the power signal VDDW to the gate of the driving transistor M2, thereby controlling the time when the driving transistor M2 generates the driving current, and further controlling the light emitting time of the light emitting device D0. The magnitude of the driving current flowing through the light emitting device D0 is controlled by the PAM driving module 02, and the light emitting time of the light emitting device D0 is controlled by the PWM driving module 01, so that the luminance of the light emitting device D0 within one frame time is commonly determined by controlling the driving current and the light emitting time of the light emitting device D0.

The above-mentioned digital-analog hybrid driving pixel circuit has the following problems: 1) The PWM driving module 01 turns on the driving transistor M1 by gradually pulling down the gate voltage of the driving transistor M1 through the ramp signal Sweep, which causes the driving transistor M1 to have a half-on intermediate state, and when the driving transistor M1 is in the half-on state, the driving transistor M2 cannot be completely turned off, so that the driving current flowing through the light emitting device D0 gradually decreases, and as known from the light emitting characteristics of the light emitting device D0, the light emitting device D0 has a color cast problem, thereby affecting the display effect of the display panel; 2) In practical applications, it is also necessary to initialize gate voltage, write data and compensate threshold value of the driving transistor M1, initialize gate voltage and compensate threshold value of the driving transistor M2, and store gate voltages of the driving transistor M1 and the driving transistor M2, so that it is necessary to set corresponding initializing transistor, data writing transistor, threshold value compensating transistor and storage capacitor in the PWM driving module 01, set corresponding initializing transistor, threshold value compensating transistor and storage capacitor in the PAM driving module 02, and set light-emitting control transistor on a line in which the driving transistor M2 and the light-emitting device D0 are connected in series, so that the number of transistors in the pixel circuit is large, and the sub-pixel density of the display panel is low, and it is difficult to implement high PPI (Pixels Per Inch, sub-pixel density unit); 3) The ramp signal Sweep is a global signal, and light emission and lighting can be performed only after all pixel circuits in the display panel have completed writing of data voltages, so that the light emission time of the light emitting device D0 driven by each pixel circuit is controlled by the ramp signal Sweep, the data voltage holding time required by the pixel circuits is long, and the problem of flicker is easily caused.

In view of the foregoing, embodiments of the present invention provide a pixel circuit. Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 2, the pixel circuit includes: the driving device includes a first driving module 10, a second driving module 20, a light emission control module 30, and a light emission module 40. The first driving module 10, the second driving module 20, the light emission control module 30, and the light emission module 40 are connected in series between the first power line L1 and the second power line L2.

The first driving module 10 is configured to generate a driving current with a corresponding magnitude in response to the first data signal Vdata1 in each of a plurality of subframes included in one frame, so as to drive the light emitting module 40 to emit light. The first data signal Vdata1 is a pulse amplitude modulation signal.

The second driving module 20 is configured to be turned on or off in response to the second data signal Vdata2 in each sub-frame, and the light emission control module 30 is configured to be turned on in response to the light emission control signal EM in each sub-frame for a corresponding period of time, so as to control the light emission time of the light emitting module 40 in each sub-frame through the second driving module 20 and the light emission control module 30, thereby controlling the light emission luminance of the light emitting module 40 in one frame. The second data signal Vdata2 in each sub-frame is a high level signal or a low level signal, and the pulse width of the on level signal in the light emission control signal EM is different in different sub-frames of the same frame.

Specifically, the current paths of the first driving module 10, the second driving module 20, the light emitting control module 30 and the light emitting module 40 are the same, the first power line L1 is connected to the first power voltage VDD, the second power line L2 is connected to the second power voltage VSS, and the first power voltage VDD may be positive voltage, and the second power voltage VSS may be negative voltage or 0V.

The pixel circuit can drive the light emitting module 40 to emit light in one frame, which may be divided into a plurality of subframes, and each subframe may include a light emitting stage. The light emission control signal EM includes an on-level signal and an off-level signal, the on-level signal is a signal for controlling the light emission control module 30 to be turned on, the off-level signal is a signal for controlling the light emission control module 30 to be turned off, and the light emission control signal EM in the light emission stage of each subframe is the on-level signal, so that the pulse width of the on-level signal in the light emission control signal EM in each subframe corresponds to the light emission stage duration in the subframe. In different subframes of the same frame, pulse widths of the on-level signals in the light-emitting control signals EM are different, that is, the light-emitting period duration of the different subframes in the same frame is different.

Illustratively, the lighting phase duration of each subframe may be assigned by a binary weight. For example, a frame is divided into 8 subframes, and the light-emitting period duration ratio of the 1 st to 8 th subframes is set as follows: 2 ⁰ ：2 ¹ ：2 ² ：2 ³ ：2 ⁴ ：2 ⁵ ：2 ⁶ ：2 ⁷ 1:2:4:8:16:32:64:128. since the pulse width of the on-level signal in the emission control signal EM in each sub-frame corresponds to the emission phase duration in that sub-frame, the ratio of the pulse widths of the on-level signals in the emission control signals EM in the 1 st to 8 th sub-frames can be expressed as 1:2:4:8:16:32:64:128 to be turned on by the light emission control module 30 in response to the on-level signal in the light emission control signal EM within each sub-frame and to be turned on for a period corresponding to the pulse width of the on-level signal, thereby controlling the light emission period duration of each sub-frame.

The first data signal Vdata1 is an analog voltage signal and is a pulse amplitude modulation signal, so that the voltage value of the first data signal Vdata1 is adjustable, and the amplitude of the driving current generated by the first driving module 10 in response to the first data signal Vdata1 can be controlled by controlling the magnitude of the voltage value of the first data signal Vdata 1. The second data signal Vdata2 in each sub-frame is a high level signal or a low level signal, one of the high level signal and the low level signal can control the second driving module 20 to be turned on, and the other can control the second driving module 20 to be turned off, so that the state of the second driving module 20 only comprises an on state and an off state, and no intermediate state between the on state and the off state exists, therefore, the state of the second driving module 20 does not gradually change the magnitude of the driving current, and color cast of the light emitting module 40 is avoided.

The light emitting time of the light emitting module 40 within each sub-frame can be commonly controlled by the second driving module 20 and the light emitting control module 30. Illustratively, in the light emitting stage of each sub-frame, the light emitting control module 30 is turned on for a corresponding period of time in response to the on-level signal in the light emitting control signal EM, the second driving module 20 is turned on or off in response to the second data signal Vdata2, and in the case where the second driving module 20 is turned on in response to the second data signal Vdata2, a current path is formed between the first power line L1 to the second power line L2, such that the light emitting period of the light emitting module 40 corresponds to the light emitting stage period of the current sub-frame, and in the case where the second driving module 20 is turned off in response to the second data signal Vdata2, a current path cannot be formed between the first power line L1 to the second power line L2, such that the light emitting period of the light emitting module 40 in the current sub-frame is 0.

According to the technical scheme, in the light-emitting stage of each subframe, the first driving module responds to the first data signal to generate the driving current with the corresponding amplitude so as to control the magnitude of the driving current flowing through the light-emitting module, analog driving is realized, the second driving module responds to the second data signal to conduct or turn off, and the light-emitting control module responds to the light-emitting control signal to conduct with the time length corresponding to the subframe so as to control whether a current path is formed between the first power line and the second power line, and therefore whether the light-emitting module emits light and emits light time length in the light-emitting stage of each subframe is controlled, and digital driving is realized. The brightness of the light emitting module in each subframe can be jointly determined by controlling the driving current flowing through the light emitting module and controlling the light emitting time of the light emitting module, so that the integral brightness of the light emitting module in one frame is controlled by controlling the brightness of the light emitting module in each subframe, and the digital-analog hybrid driving is realized.

Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 3, each sub-frame optionally includes a data writing phase and a light emitting phase on the basis of the above-described embodiments. The second driving module 20 includes a first driving unit 210 and a first data writing unit 220. The first data writing unit 220 is connected to the control terminal of the first driving unit 210, and is configured to write the second data signal Vdata2 to the control terminal of the first driving unit 210 in the data writing stage of each subframe in response to the first scan signal G1. The first driving unit 210 is connected in series between the first power line L1 and the second power line L2, and is configured to be turned on or off in response to a signal from a control terminal thereof during a light emitting period of each sub-frame.

Specifically, the control terminal of the first data writing unit 220 is connected to the first scanning signal G1, the first terminal of the first data writing unit 220 is connected to the second data signal Vdata2, and the second terminal of the first data writing unit 220 is connected to the control terminal of the first driving unit 210. The second driving module 20 is connected in series with the first driving module 10, the light emission control module 30, and the light emitting module 40 through the first driving unit 210. The first data writing unit 220 is turned on or off in response to the first scan signal G1 to turn on in the data writing phase of each sub-frame, and writes the second data signal Vdata2 to the control terminal of the first driving unit 210. The second data signal Vdata2 in each sub-frame is a high level signal or a low level signal, one of the high level signal and the low level signal can control the first driving unit 210 to be turned on, and the other can control the first driving unit 210 to be turned off, so that the state of the first driving unit 210 only includes an on state and an off state, and no intermediate state between the on state and the off state exists, and therefore the state of the first driving unit 210 does not cause the magnitude of the driving current to be gradually changed, which helps to avoid the occurrence of color cast of the light emitting module 40. In addition, since the first driving unit 210 does not have an intermediate state, a structure for performing threshold voltage compensation on the first driving unit 210 is not required, which is helpful to simplify the pixel circuit structure, to improve the subpixel density of the display panel, and to realize high PPI.

Alternatively, within one frame, the pulse width of the emission control signal EM in the emission phase of each subframe is different, and the interval between pulse signals in the first scan signal G1 in the data writing phase of the adjacent subframe is different. Specifically, the pulse width of the emission control signal EM in the emission stage of each subframe refers to the pulse width of the on-level signal that controls the emission control module 30 to be turned on, if the on-level signal is a low-level signal, it refers to the pulse width of the low-level signal, and if the on-level signal is a high-level signal, it refers to the pulse width of the high-level signal. The pulse signal in the first scan signal G1 in the data writing stage of each subframe is a pulse signal for controlling the first data writing unit 220 to be turned on. By setting different subframes of the same frame, pulse widths of the on-level signals in the light-emitting control signal EM are different, so that light-emitting stage duration of the different subframes of the same frame is different. Since the light emitting period durations of the adjacent subframes are different, the intervals between the pulse signals in the first scan signal G1 in the data writing period of the adjacent subframes are different, and the explanation is made taking four subframes as an example, the intervals between the pulse signals in the first scan signal G1 in the data writing period of the first and second subframes, the intervals between the pulse signals in the first scan signal G1 in the data writing period of the second and third subframes, and the intervals between the pulse signals in the first scan signal G1 in the data writing period of the third and fourth subframes are different.

With continued reference to fig. 3, the second driving module 20 may optionally further include a first storage unit 230, a first terminal of the first storage unit 230 is connected to a fixed voltage, and a second terminal of the first storage unit 230 is connected to a control terminal of the first driving unit 210. The fixed voltage connected to the first terminal of the first memory cell 230 may be any fixed voltage, for example, the first terminal of the first memory cell 230 may be connected to the first power line L1, so that the first terminal of the first memory cell 230 is connected to the first power voltage VDD. The first storage unit 230 is configured to store a voltage of a control terminal of the first driving unit 210.

Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 4, further, the first driving unit 210 includes a first driving transistor DT1, the first data writing unit 220 includes a first transistor T1, and the first storage unit 230 includes a first capacitor C1. The first driving transistor DT1 is connected in series between the first power line L1 and the second power line L2, a gate of the first transistor T1 is connected to the first scanning signal G1, a first pole of the first transistor T1 is connected to the second data signal Vdata2, and a second pole of the first transistor T1 is connected to the gate of the first driving transistor DT 1. The first pole of the first capacitor C1 is connected to a fixed voltage (e.g., the first power voltage VDD, or other fixed voltage), and the second pole of the first capacitor C1 is connected to the control terminal of the first driving unit 210.

It should be noted that, in the case where the module or the unit in the embodiments of the present invention is formed of only one transistor, the gate of the transistor may be used as the control terminal of the corresponding module or unit, the first pole of the transistor may be used as the first terminal of the corresponding module or unit, the second pole of the transistor may be used as the second terminal of the corresponding module or unit, and one of the first pole and the second pole of the transistor may be the source, and the other may be the drain.

With continued reference to fig. 4, each subframe optionally further includes an initialization phase. The second driving module 20 further includes a first initializing unit 240, where the first initializing unit 240 is connected to the control terminal of the first driving unit 210, and is configured to write a first initializing signal V1 to the control terminal of the first driving unit 210 in response to the second scanning signal G2 during the initializing phase of each sub-frame, so as to control the first driving unit 210 to be turned off. Specifically, the control end of the first initializing unit 240 is connected to the second scanning signal G2, the first end of the first initializing unit 240 is connected to the first initializing signal V1, and the second end of the first initializing unit 240 is connected to the control end of the first driving unit 210. The first initializing unit 240 is turned on or off in response to the second scan signal G2 to be turned on in an initializing phase of each sub-frame, and writes the first initializing signal V1 to the control terminal of the first driving unit 210. The first initialization signal V1 is a signal for controlling the first driving unit 210 to be turned off, if the signal for controlling the first driving unit 210 to be turned off is a high level signal, the first initialization signal V1 is a high level signal, if the signal for controlling the first driving unit 210 to be turned off is a low level signal, the first initialization signal V1 is a low level signal. In the initialization phase, the light emitting module 40 does not emit light, so the first driving unit 210 is controlled to be turned off.

Alternatively, the intervals between the pulse signals in the second scan signals G2 in the initialization stage of the adjacent subframes are different within one frame. Specifically, the pulse signal in the second scan signal G2 in the initialization stage of each subframe refers to a pulse signal that controls the first initialization unit 240 to be turned on. Since the light emitting period durations of the adjacent subframes are different, the intervals between the pulse signals in the second scan signal G2 of the initialization period of the adjacent subframes are different.

With continued reference to fig. 4, further, the first initializing unit 240 includes a second transistor T2, a gate of the second transistor T2 is connected to the second scan signal G2, a first pole of the second transistor T2 is connected to the first initializing signal V1, and a second pole of the second transistor T2 is connected to the control terminal of the first driving unit 210.

Fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 5, optionally, each subframe includes a data writing phase and a light emitting phase. The first driving module 10 includes a second driving unit 110 and a second data writing unit 120. The second data writing unit 120 is connected to the second driving unit 110, and is configured to write the first data signal Vdata1 to the control terminal of the second driving unit 110 in the data writing stage of each sub-frame in response to the third scan signal G3. The second driving unit 110 is connected in series between the first power line L1 and the second power line L2, and is configured to generate a driving current with a corresponding magnitude in response to a signal at a control terminal thereof during a light emitting stage of each sub-frame, so as to drive the light emitting module 40 to emit light.

Specifically, the control end of the second data writing unit 120 is connected to the third scan signal G3, the first end of the second data writing unit 120 is connected to the first data signal Vdata1, and the second end of the second data writing unit 120 is connected to the second driving unit 110, for example, the second end of the second data writing unit 120 may be directly connected to the control end of the second driving unit 110. The first driving module 10 is connected in series with the second driving module 20, the light emission control module 30, and the light emitting module 40 through the second driving unit 110. The second data writing unit 120 is turned on or off in response to the third scan signal G3 to turn on in the data writing stage of each sub-frame, and writes the first data signal Vdata1 into the control terminal of the second driving unit 110, so that the second driving unit 110 generates a driving current with a corresponding amplitude in response to the first data signal Vdata1 at the control terminal thereof in the light emitting stage of each sub-frame to drive the light emitting module 40 to emit light. The voltage value of the first data signal Vdata1 corresponding to each subframe in the same frame may be the same or may be different, so as to control the driving current amplitude of each subframe by controlling the voltage value of the first data signal Vdata1 corresponding to each subframe, thereby controlling the brightness of the light emitting module 40 in each subframe.

Alternatively, the intervals between the pulse signals in the third scan signal G3 in the data writing stage of the adjacent sub-frames are different within one frame. Specifically, the pulse signal in the third scan signal G3 of the data writing stage of each subframe refers to a pulse signal that controls the second data writing unit 120 to be turned on. Since the light emitting period durations of the adjacent subframes are different, the intervals between the pulse signals in the third scan signal G3 of the data writing period of the adjacent subframes are different.

With continued reference to fig. 5, optionally, the first driving module 10 further includes a second storage unit 130, a first end of the second storage unit 130 is connected to a fixed voltage, and a second end of the second storage unit 130 is connected to a control end of the second driving unit 110. The fixed voltage connected to the first terminal of the second memory unit 130 may be any fixed voltage, for example, the first terminal of the second memory unit 130 may be set to be connected to the first power line L1, so that the first terminal of the second memory unit 130 is connected to the first power voltage VDD. The second storage unit 130 is configured to store a voltage of a control terminal of the second driving unit 110.

Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 6, further, the second driving unit 110 includes a second driving transistor DT2, the second data writing unit 120 includes a third transistor T3, and the second storage unit 130 includes a second capacitor C2. The second driving transistor DT2 is connected in series between the first power line L1 and the second power line L2, a gate of the third transistor T3 is connected to the third scanning signal G3, a first pole of the third transistor T3 is connected to the first data signal Vdata1, a second pole of the third transistor T3 is connected to the second driving transistor DT2, for example, a second pole of the third transistor T3 may be connected to the gate of the second driving transistor DT 2. The first end of the second capacitor C2 is connected to a fixed voltage (e.g. the first power voltage VDD, or other fixed voltage), and the second end of the second capacitor C2 is connected to the control end of the second driving unit 110.

Fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 7, optionally, each subframe further includes an initialization phase. The first driving module 10 further includes a threshold compensation unit 140 and a second initialization unit 150. The second terminal of the second data writing unit 120 is connected to the first terminal of the second driving unit 110, the threshold compensation unit 140 is connected between the second terminal and the control terminal of the second driving unit 110, and the threshold compensation unit 140 is configured to compensate the threshold voltage of the second driving unit 110 in response to the third scan signal G3. The second initializing unit 150 is connected to the control terminal of the second driving unit 110, and is configured to write a second initializing signal Vref to the control terminal of the second driving unit 110 in an initializing stage of each subframe in response to the second scan signal G2.

Specifically, the control end of the threshold compensation unit 140 is connected to the third scan signal G3, the first end of the threshold compensation unit 140 is connected to the second end of the second driving unit 110, and the second end of the threshold compensation unit 140 is connected to the control end of the second driving unit 110. In the data writing stage of each sub-frame, the second data writing unit 120 and the threshold compensation unit 140 are turned on in response to the third scan signal G3, and the first data signal Vdata1 is sequentially written into the control terminal of the second driving unit 110 through the second data writing unit 120, the second driving unit 110 and the threshold compensation unit 140, while the threshold voltage of the second driving unit 110 is compensated through the threshold compensation unit 140. The control end of the second initializing unit 150 is connected to the second scanning signal G2, the first end of the second initializing unit 150 is connected to the second initializing signal Vref, and the second end of the second initializing unit 150 is connected to the control end of the second driving unit 110. The second initializing unit 150 is turned on or off in response to the second scan signal G2 to be turned on in an initializing stage of each sub-frame, and writes a second initializing signal Vref to the control terminal of the second driving unit 110 to initialize the voltage of the control terminal of the second driving unit 110.

With continued reference to fig. 7, further, the threshold compensation unit 140 includes a fourth transistor T4, and the second initialization unit 150 includes a fifth transistor T5. The second pole of the third transistor T3 is connected to the first terminal of the second driving unit 110. The gate of the fourth transistor T4 is connected to the third scan signal G3, and the fourth transistor T4 is connected between the second terminal and the control terminal of the second driving unit 110. The gate of the fifth transistor T5 is connected to the second scan signal G2, the first pole of the fifth transistor T5 is connected to the second initialization signal Vref, and the second pole of the fifth transistor T5 is connected to the control terminal of the second driving unit 110.

With continued reference to fig. 7, the light emission control module 30 optionally includes a sixth transistor T6, and the light emission module 40 includes a light emitting device D1. The sixth transistor T6 and the light emitting device D1 are connected in series between the first power line L1 and the second power line L2, and the gate of the sixth transistor T6 is connected to the light emission control signal EM. The Light Emitting device D1 includes an Organic Light-Emitting Diode (OLED), a Micro-sized Light Emitting Diode (Micro-LED), and the like.

Fig. 8 is a schematic diagram of another pixel circuit according to an embodiment of the present invention. Fig. 9 is a schematic diagram of a driving timing diagram of a pixel circuit according to an embodiment of the present invention. The driving timing shown in fig. 9 is suitable for driving the pixel circuit in fig. 8 to operate. The transistors in the embodiments of the present invention may be P-type transistors or N-type transistors, and the transistors in the pixel circuits are only illustrated as P-type transistors in fig. 4 and 6-8, and the types of the transistors are not limited. The operation principle of the pixel circuit will be described below with reference to fig. 8 and 9, taking P-type transistors as examples of each transistor in the pixel circuit, based on the above embodiments.

For example, one frame P0 may be divided into 8 subframes, which are the first to eighth subframes P1 to P8, respectively. Fig. 9 only shows the first to fourth subframes P1 to P4, but does not show the fifth to eighth subframes P5 to P8, and the duration distribution of the fifth to eighth subframes P5 to P8 and the corresponding waveforms of the signals can be understood in combination with the duration distribution of the first to fourth subframes P1 to P4 and the corresponding waveforms of the signals and the text description in this embodiment. Each of the subframes includes an initialization phase, a data writing phase, and a light-emitting phase, the data writing phase includes a first data writing phase and a second data writing phase, and a ratio of time periods of the light-emitting phases Q1 to Q8 (only the light-emitting phases Q1 to Q4 are shown in fig. 9, and the light-emitting phases Q5 to Q8 are not shown) in the first to eighth subframes P1 to P8 is: 1:2:4:8:16:32:64:128, the ratio of pulse width of the low level signal of the emission control signal EM in the emission period Q1 to the emission period Q8 is 1 within one frame P0: 2:4:8:16:32:64:128.

in the initialization stage of the first sub-frame P1, the second scan signal G2 is a low level signal, and the first scan signal G1, the third scan signal G3, and the emission control signal EM are high level signals. The second transistor T2 and the fifth transistor T5 are turned on, and the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off. The first initialization signal V1 is a high level signal, and the first initialization signal V1 is written into the gate of the first driving transistor DT1 through the second transistor T2 to turn off the first driving transistor DT 1. The second initialization signal Vref is written into the gate of the second driving transistor DT2 through the fifth transistor T5 to initialize the gate voltage of the second driving transistor DT2 and control the second driving transistor DT2 to be turned on.

In the first data writing stage of the first sub-frame P1, the third scan signal G3 is a low level signal, and the first scan signal G1, the second scan signal G2, and the emission control signal EM are high level signals. The second driving transistor DT2, the third transistor T3, and the fourth transistor T4 are turned on, and the remaining transistors are turned off. The first data signal Vdata1 is written into the gate of the second driving transistor DT2 through the third transistor T3, the second driving transistor DT2, and the fourth transistor T4 in sequence, and simultaneously, the threshold voltage compensation is performed on the second driving transistor DT2 through the fourth transistor T4, and the gate voltage of the second driving transistor DT2 is stored through the second capacitor C2.

In the second data writing stage of the first sub-frame P1, the first scan signal G1 is a low level signal, and the second scan signal G2, the third scan signal G3, and the emission control signal EM are high level signals. The first transistor T1 is on and the remaining transistors are off. The second data signal Vdata2 is written into the gate of the first driving transistor DT1 through the first transistor T1 and stores the gate voltage of the first driving transistor DT1 through the first capacitor C1. The second data signal Vdata2 is a high level signal or a low level signal, and if the second data signal Vdata2 is a high level signal, the first driving transistor DT1 is turned off in response to the second data signal Vdata2, and if the second data signal Vdata2 is a low level signal, the first driving transistor DT1 is turned on in response to the second data signal Vdata 2.

In the light emitting stage Q1 of the first subframe P1, the light emission control signal EM is a low level signal, and the first, second and third scan signals G1, G2 and G3 are high level signals. The sixth transistor T6 is turned on, and the first driving transistor DT1 is turned on or off in response to the second data signal Vdata2 stored in the first capacitor C1. When both the first driving transistor DT1 and the sixth transistor T6 are turned on to form a current path between the first power line L1 and the second power line L2, the second driving transistor DT2 generates a driving current with a corresponding magnitude according to the first data signal Vdata1 stored in the second capacitor C2 to drive the light emitting device D1 to emit light. By controlling the voltage value of the first data signal Vdata1 of the first sub-frame P1, the magnitude of the driving current generated by the second driving transistor DT2 can be controlled. By controlling the second data signal Vdata2 of the first sub-frame P1 to be a high level signal or a low level signal, whether a current path is formed between the first power line L1 and the second power line L2 can be controlled to control the light emitting time of the light emitting device D1. When the second data signal Vdata2 is a high level signal, a current path cannot be formed between the first power line L1 and the second power line L2 when the first driving transistor DT1 is turned off, the light emitting device D1 does not emit light, the light emitting device D1 has a light emitting duration of 0 in the light emitting period Q1, when the second data signal Vdata2 is a low level signal, a current path is formed between the first power line L1 and the second power line L2 when the first driving transistor DT1 is turned on, and the light emitting device D1 emits light for a corresponding duration in the light emitting period Q1, thereby realizing the control of the light emitting brightness of the light emitting device D1 in the first subframe P1 by controlling the driving current and the light emitting duration of the light emitting device D1.

In each of the second to eighth subframes P2 to P8, an initialization phase, a first data writing phase, a second data writing phase, and a light emitting phase are sequentially performed. The specific working principles of the second to eighth subframes P2 to P8 can be understood with reference to the first subframe P1, and will not be described herein.

The driving current amplitude in each sub-frame can be controlled by controlling the voltage value of the first data signal Vdata1 of each sub-frame, and the light emitting brightness of the light emitting device D1 in each sub-frame can be controlled by controlling the driving current and the light emitting duration of the light emitting device D1 by setting the duration of the light emitting phase of each sub-frame and controlling the second data signal Vdata2 of each sub-frame to be a high level signal or a low level signal, whether the light emitting device D1 emits light in the light emitting phase of each sub-frame for a corresponding duration. By controlling the light emission luminance of the light emitting device D1 in the first to eighth subframes P1 to P8, it is finally possible to realize control of the overall luminance of the light emitting device D1 in one frame P0.

The principle of the pixel circuit controlling the overall luminance of the light emitting device D1 within one frame P0 will be described in a specific embodiment. Illustratively, in conjunction with fig. 8 and 9, the duration of the light-emitting phases Q1 to Q8 of the first to eighth subframes P1 to P8 is sequentially: 1. 2, 4, 8, 16, 32, 64, 128, and the light-emitting period duration of each subframe corresponds to the gray-scale value represented by the continuous light emission of the light-emitting device D1 in the light-emitting period of the subframe. When the pixel circuit needs to drive the light emitting device D1 to display 4 gray scales, in the second data writing stage of the first sub-frame P1 and the second sub-frame P2, the second data signal Vdata2 is controlled to be a high level signal, so that the first driving transistor DT1 is turned off, and the light emitting device D1 does not emit light in the light emitting stage Q1 and the light emitting stage Q2. In the second data writing stage of the third sub-frame P3, the second data signal Vdata2 is controlled to be a low level signal, so that the first driving transistor DT1 is turned on to make the light emitting device D1 emit light in a corresponding "4" period in the light emitting stage Q3. In the second data writing phase of the fourth to eighth subframes P4 to P8, the second data signal Vdata2 is controlled to be a high level signal, so that the first driving transistor DT1 is turned off to make the light emitting device D1 emit no light in the light emitting phase Q4 to Q8. Accordingly, the cumulative light emission duration of the light emitting device D1 is "4" in one frame P0, and the gray scale displayed by the light emitting device D1 in one frame P0 is 4 gray scales. If the high level signal is represented by a binary value of 1, the low level signal is represented by a binary value of 0, and the second data signal Vdata2 of the first to eighth sub-frames P1 to P8 is represented by respective bits of binary, the second data signal Vdata2 of each sub-frame can be binary represented as: 11011111. similarly, if the light emitting device D1 needs to be controlled to display 9 gray scales in one frame P0, the light emitting device D1 may be controlled to display 1 gray scale and 8 gray scales in the first subframe P1 and the fourth subframe P8, respectively, so that the gray scale displayed by the light emitting device D1 in one frame P0 is 9 gray scales obtained by overlapping 1 gray scale and 8 gray scale, and the second data signal Vdata2 of each subframe may be binary represented as: 01101111. if the light emitting device D1 needs to be controlled to display other gray scales in one frame P0, the second data signal Vdata2 of each sub-frame may also be controlled according to the above principle, so that the gray scales displayed in each sub-frame by the light emitting device D1 are controlled to be accumulated into the whole gray scales. On the basis, the brightness of the light emitting device D1 in each subframe can be further controlled by combining the control of the voltage value of the first data signal Vdata1 of each subframe, so that finer gray scale control is realized.

In the above embodiment, only one frame is divided into 8 subframes, and the lighting period duration of each subframe is respectively 1, 2, 4, 8, 16, 32, 64, and 128, which is not limited in this embodiment, in other embodiments, one frame may be divided into other number of subframes, and the lighting period duration of each subframe may be set according to the requirement.

According to the technical scheme provided by the embodiment of the invention, the driving current and the light emitting time of the light emitting device D1 are controlled by controlling the driving current of the light emitting device D1, so that the driving current and the light emitting time of the light emitting device D1 jointly determine the brightness of the light emitting device D1 in each subframe, and the overall brightness of the light emitting device D1 in one frame is controlled by controlling the brightness of the light emitting device D1 in each subframe, so that digital-analog hybrid driving is realized.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects: 1) By setting the second data signal Vdata2 to a high level signal or a low level signal, the state of the first driving transistor DT1 only includes an on state and an off state, and there is no intermediate state between the on state and the off state, so that the state of the first driving transistor DT1 does not gradually change the magnitude of the driving current, which is helpful for improving the color shift problem of the light emitting module. 2) The pixel circuit only comprises 8 transistors and 2 capacitors, compared with the existing digital-analog hybrid driving pixel circuit, the pixel circuit has fewer transistors and capacitors, and because the first driving transistor DT1 has no intermediate state, the transistor for carrying out threshold voltage compensation on the first driving transistor DT1 is not required, thereby being more beneficial to simplifying the structure of the pixel circuit, improving the density of the sub-pixels of the display panel and realizing high PPI; 3) By adopting the subframe control mode, data writing and light emission can be performed in each subframe, and the light emission and lighting are not required after all pixel circuits in the display panel complete data writing, so that the data signal holding time required by the pixel circuits is shortened, and the problem of flicker is relieved.

In addition, in the embodiments of the present invention, in the case where the signal for controlling the on state of the first driving unit 210 (i.e., the gate of the first driving transistor DT 1) in the second data signal Vdata2 is a low level signal, for example, in the case where the first driving transistor DT1 is a P-type transistor, the voltage value of the low level signal may be set to any voltage value capable of controlling the on state of the P-type transistor (the voltage value is not too high to avoid controlling the on state of the transistor), which is because the magnitude of the second data signal Vdata2 only determines the on state of the first driving unit 210 (i.e., the gate of the first driving transistor DT 1) without affecting the voltage of the control terminal of the second driving unit 110 (i.e., the gate of the second driving transistor DT 2), and thus the specific voltage value of the low level signal in the second data signal Vdata2 may be flexibly set.

Similarly, in the case where the signal for controlling the on state of the first driving unit 210 (i.e., the first driving transistor DT 1) in the data signal Vdata2 is a high level signal, for example, in the case where the first driving transistor DT1 is an N-type transistor, the voltage value of the high level signal may be set to any voltage value capable of controlling the on state of the N-type transistor (the voltage value is not too low to avoid the inability to control the on state of the transistor), which is because the size of the second data signal Vdata2 only determines the on state of the first driving unit 210 (i.e., the first driving transistor DT 1) and does not affect the voltage of the control terminal of the second driving unit 110 (i.e., the gate of the second driving transistor DT 2), so that the data writing process of the first driving unit 210 (i.e., the first driving transistor DT 1) is not affected.

The embodiment of the invention also provides a driving method of the pixel circuit, which is suitable for driving the pixel circuit in each embodiment to work. Fig. 10 is a flowchart of a driving method of a pixel circuit according to an embodiment of the invention. Referring to fig. 10, the method specifically includes the steps of:

s110, dividing one frame into a plurality of subframes.

S120, generating a driving current with corresponding amplitude in response to the first data signal in each sub-frame through the first driving module so as to drive the light emitting module to emit light.

Wherein the first data signal is a pulse amplitude modulated signal.

S130, the second driving module responds to the second data signal in each sub-frame to turn on or off, and the light-emitting control module responds to the light-emitting control signal in each sub-frame to turn on in corresponding time length, so that the light-emitting time of the light-emitting module in each sub-frame is controlled by the second driving module and the light-emitting control module, and the light-emitting brightness of the light-emitting module in one frame is controlled.

The second data signal in each subframe is a high level signal or a low level signal, and pulse widths of the on level signals in the light-emitting control signals are different in different subframes of the same frame.

1) The second data signal is a high-level signal or a low-level signal, so that the state of the second driving module only comprises a conducting state and a switching-off state, and an intermediate state between the conducting state and the switching-off state does not exist, and therefore the state of the second driving module does not gradually change the magnitude of the driving current, and the color cast problem of the light emitting module is improved; 2) The whole structure of the pixel circuit is simple, and the second driving module does not need to be subjected to threshold voltage compensation because the second driving module does not have an intermediate state, so that the driving method of the pixel circuit is simplified; 3) By adopting the subframe control mode, data writing and light emission can be performed in each subframe, and the light emission and lighting are not required after all pixel circuits in the display panel complete data writing, so that the data signal holding time required by the pixel circuits is shortened, and the problem of flicker is relieved.

On the basis of the above embodiment, optionally, steps S120 to S130 specifically include:

in the data writing stage of each subframe, a first data writing unit is used for responding to a first scanning signal to write a second data signal into a control end of a first driving unit, and a second data writing unit is used for responding to a third scanning signal to write the first data signal into the control end of a second driving unit;

in the light-emitting stage of each subframe, a driving current with corresponding amplitude is generated by the second driving unit in response to a signal of the control end of the second driving unit so as to drive the light-emitting module to emit light, the first driving unit is turned on or off in response to a signal of the control end of the second driving unit, and the light-emitting control module is turned on in corresponding time duration in response to a light-emitting control signal so as to control the light-emitting time of the light-emitting module in each subframe through the first driving unit and the light-emitting control module, thereby controlling the light-emitting brightness of the light-emitting module in one frame.

Optionally, each subframe further comprises an initialization phase. Accordingly, the driving method of the pixel circuit further includes:

in the initialization stage of each subframe, a first initialization signal is written into a control end of a first driving unit through a first initialization unit in response to a second scanning signal so as to control the first driving unit to be turned off, and a second initialization signal is written into a control end of a second driving unit through a second initialization unit in response to the second scanning signal.

The embodiment of the invention also provides a display panel, which comprises a plurality of rows of the pixel circuits in any of the embodiments. The display panel may be an Organic Light-Emitting Diode (OLED) display panel, an Active-Matrix Organic Light-Emitting Diode (OLED) display panel, a Micro-scale Light-Emitting Diode (Micro-LED) display panel, or the like.

The display panel provided by the embodiment of the invention adopts a subframe control mode to control each row of pixel circuits to drive the light emitting module. By way of example, each pixel circuit in the display panel performs an initialization phase, a data writing phase and a lighting phase in each subframe in a frame, so that the pixel circuit drives the lighting module in each subframe, that is, controls the driving current flowing through the lighting module and the lighting time of the lighting module, sequentially drives the lighting module by controlling each subframe in a frame by controlling each row of pixel circuits, and drives the lighting module by controlling each row of pixel circuits in a frame by rows, progressive scanning can be realized, so that the lighting module is driven by each row of pixel circuits by rows, and after all pixel circuits in the display panel do not need to wait for data writing, the lighting module is driven by all pixel circuits at the same time, thereby contributing to shortening the data signal holding time required by the pixel circuits and alleviating the problem of flicker.

The display panel provided by the embodiment of the invention comprises the pixel circuit in any embodiment, so that the display panel has corresponding functional modules and beneficial effects of the pixel circuit, and the details are not repeated here.

The embodiment of the invention also provides a driving method of the display panel, which is suitable for driving the display panel in the embodiment to work. The driving method of the display panel specifically comprises the following steps:

and controlling each row of pixel circuits to drive the light emitting modules in sequence in each subframe in one frame, and controlling each row of pixel circuits to drive the light emitting modules row by row in one frame.

According to the technical scheme, the sub-frame control mode is adopted to control each row of pixel circuits to drive the light emitting module, each sub-frame in one frame is controlled to sequentially drive each row of pixel circuits to drive the light emitting module, each row of pixel circuits are controlled to drive the light emitting module row by row in one frame, progressive scanning can be achieved, the light emitting module is driven row by row through each row of pixel circuits, after data writing is completed for all pixel circuits in the display panel, the light emitting module is driven simultaneously through all the pixel circuits, and therefore the data signal retention time required by the pixel circuits is shortened, and the flicker problem is relieved.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A pixel circuit, comprising: the light-emitting device comprises a first driving module, a second driving module, a light-emitting control module and a light-emitting module, wherein the first driving module, the second driving module, the light-emitting control module and the light-emitting module are connected in series between a first power line and a second power line;

2. The pixel circuit of claim 1, wherein each of the subframes includes a data writing phase and a light emitting phase; the second driving module comprises a first driving unit and a first data writing unit;

3. The pixel circuit according to claim 2, wherein a pulse width of the emission control signal in an emission period of each of the subframes is different within one frame, and a pitch between pulse signals in the first scan signals in a data writing period of adjacent subframes is different.

4. A pixel circuit according to claim 2 or 3, wherein each of the subframes further comprises an initialization phase; the second driving module further comprises a first initializing unit;

5. The pixel circuit of claim 1, wherein each of the subframes includes a data writing phase and a light emitting phase; the first driving module comprises a second driving unit and a second data writing unit;

6. The pixel circuit according to claim 1, wherein the light-emitting control module includes a sixth transistor, the light-emitting module includes a light-emitting device, the sixth transistor and the light-emitting device are connected in series between the first power line and the second power line, and a gate of the sixth transistor is connected to the light-emitting control signal.

7. A driving method of a pixel circuit, characterized in that the pixel circuit comprises: the light-emitting device comprises a first driving module, a second driving module, a light-emitting control module and a light-emitting module, wherein the first driving module, the second driving module, the light-emitting control module and the light-emitting module are connected in series between a first power line and a second power line;

The driving method of the pixel circuit comprises the following steps:

dividing a frame into a plurality of subframes;

8. The method of driving a pixel circuit according to claim 7, wherein each of the subframes includes a data writing stage and a light emitting stage; the second driving module comprises a first driving unit and a first data writing unit; the first driving module comprises a second driving unit and a second data writing unit; the first data writing unit is connected with the control end of the first driving unit, and the first driving unit is connected in series between the first power line and the second power line; the second data writing unit is connected with the second driving unit, and the second driving unit is connected in series between the first power line and the second power line;

9. A display panel comprising a plurality of rows of pixel circuits according to any one of claims 1-6.

10. A driving method of a display panel, characterized in that it is used for driving the display panel according to claim 9 to operate, the driving method of the display panel comprising: