CN117295245A

CN117295245A - Printed circuit board and manufacturing method thereof

Info

Publication number: CN117295245A
Application number: CN202210691522.5A
Authority: CN
Inventors: 王柏翔; 吴明豪
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2022-06-17
Filing date: 2022-06-17
Publication date: 2023-12-26

Abstract

The invention relates to the field of printed circuit boards, and provides a printed circuit board which comprises a first substrate, at least one first wire layer and at least one second wire layer. The first substrate is provided with a first surface and a second surface, and the first surface and the second surface are opposite along the axial direction. The first wire layer is formed on the first surface and/or the second surface of the first substrate, and is provided with at least one first wire etched and at least one first hole etched beside the first wire. The second wire layer is formed on the first wire layer, and the second wire layer is provided with at least one second wire etched and at least one second hole etched beside the second wire. The first wire and the second wire are mutually jointed along the axial direction so as to form a laminated wire. Wherein the etching factors of the first wire, the second wire and the overlapped wire are all more than or equal to 4.6.

Description

Printed circuit board and manufacturing method thereof

Technical Field

The present invention relates to a printed circuit board and a method for manufacturing the same, and more particularly, to a printed circuit board with a high etching factor for a conductive wire and a method for manufacturing the same.

Background

The thick copper printed circuit board is a printed circuit board whose lead is thicker than that of a general printed circuit board, and in recent years, with the driving of industries such as electric vehicles, the demand for the thick copper printed circuit board applied to products such as high heat dissipation and high current is increasing. Currently, thick copper printed circuit boards are typically fabricated using multiple etching processes. However, since the copper layer is subjected to multiple etching, the etching factor is small in addition to the reduction in productivity. In addition, the small etching factor affects the layout of the circuit design, and the lead wires in the inner layer of the printed circuit board are easy to generate tip discharge, so that short circuit or insulation damage occurs.

Therefore, it is worth thinking by those skilled in the art how to manufacture a printed circuit board with wires having a high etching factor.

Disclosure of Invention

The present invention provides a printed circuit board and a method for manufacturing the same, which can make the wires in the printed circuit board have a higher etching factor.

In view of the above and other objects, the present invention provides a printed circuit board, which includes a first substrate, at least one first conductive layer, and at least one second conductive layer. The first substrate is provided with a first surface and a second surface, and the first surface and the second surface are opposite along an axial direction. The first wire layer is formed on the first surface and/or the second surface of the first substrate, and is provided with at least one first wire etched and at least one first hole etched beside the first wire. Wherein the etching factor of the first wire is more than or equal to 2.3. The second wire layer is formed on the first wire layer, and is provided with at least one second wire etched and at least one second hole etched beside the second wire, wherein the etching factor of the second wire is more than or equal to 2.3. The first wire and the second wire are mutually jointed along the axial direction to form a laminated wire, and the etching factor of the laminated wire is more than or equal to 4.6.

In the printed circuit board described above, the bonding between the first and second wires is by a low temperature copper-to-copper bonding (Low Temperature Copper Bonding) technique.

In the printed circuit board, the first wire and the second wire are bonded by a conductive adhesive.

In the printed circuit board, the first and second holes are mutually penetrated along the axial direction, and the first and second holes are filled with a dielectric material.

In the above printed circuit board, the bonding between the first wire and the second wire includes applying a planarization technique. Further, the planarization technique is, for example, a chemical mechanical polishing technique.

In the printed circuit board, a solder resist ink is formed on an outer surface of the second conductive line layer and/or the laminated conductive line.

In the above printed circuit board, the second conductive layer is disposed on a second substrate surface.

Based on the above and other objects, the present invention further provides a method for manufacturing a printed circuit board, which comprises the following steps:

providing a first substrate, wherein the first substrate is provided with a first surface and a second surface, and the first surface and the second surface are opposite along an axial direction;

at least one first conducting wire layer is formed on the first surface and/or the second surface of the first substrate. The first conducting wire layer is provided with at least one first conducting wire which is etched, and at least one first hole which is formed by etching beside the first conducting wire, wherein the etching factor of the first conducting wire is more than or equal to 2.3;

at least one second conductive line layer is formed on the first conductive line layer. The second conducting wire layer is provided with at least one second conducting wire which is etched, and at least one second hole which is formed by etching beside the second conducting wire. Wherein the etching factor of the second wire is more than or equal to 2.3; a kind of electronic device with high-pressure air-conditioning system

Forming a laminated wire, wherein the laminated wire is formed by bonding the first wire and the second wire along the axial direction, and the etching factor of the laminated wire is greater than or equal to 4.6.

In the above-mentioned method for manufacturing a printed circuit board, the bonding between the first wire and the second wire is performed by using a low temperature copper-to-copper bonding technique.

In the above-mentioned method for manufacturing a printed circuit board, the first conductive wire and the second conductive wire are bonded by a conductive adhesive.

In the above-mentioned method for manufacturing a printed circuit board, the first hole and the second hole are mutually penetrated along the axial direction, and the first hole and the second hole are filled with a dielectric material.

In the above-mentioned method for manufacturing a printed circuit board, the bonding between the first conductive line and the second conductive line comprises applying a planarization technique. Further, the planarization technique is, for example, a chemical mechanical polishing technique.

In the above-mentioned method for manufacturing the printed circuit board, a surface treatment (Surface treatment) is performed on the outer surface of the second conductive line layer and/or the stacked conductive lines.

In the above method for manufacturing a printed circuit board, the second conductive layer is disposed on a second substrate surface.

In summary, when the printed circuit board of the present invention is manufactured, the printed circuit board with higher etching factor of the conductive lines can be obtained due to etching the respective conductive layers.

To achieve the foregoing and other objects, and in accordance with the purpose of the invention, as embodied and broadly described, a preferred embodiment of the present invention is illustrated and described below.

Drawings

Fig. 1 to 7 show a first embodiment of a method for manufacturing a printed circuit board according to the present invention.

Fig. 8 to 13 show a second embodiment of the method for manufacturing a printed circuit board according to the present invention.

Fig. 14 to 21 show a third embodiment of the method for manufacturing a printed circuit board according to the present invention.

Fig. 22 shows a fourth embodiment of the printed circuit board of the present invention.

Detailed Description

The invention is best understood by reference to the detailed description and accompanying drawings set forth herein. Various embodiments are discussed below with reference to the figures. However, those of ordinary skill in the art will readily appreciate that the detailed description given herein with respect to the figures is for explanatory purposes only and is not representative of actual scale of the components, as the claimed subject matter and/or method may deviate from the described embodiments. For example, the teachings presented and the needs of a particular application may result in a variety of alternative and suitable methods to implement the functionality of any of the details described herein. Accordingly, any subject matter and/or method to be protected by this disclosure may extend beyond the scope of the particular implementations described in the following embodiments.

Referring to fig. 1 to 7, fig. 1 to 7 show a first embodiment of a method for manufacturing a printed circuit board according to the present invention. First, referring to fig. 1, a first substrate 1 is provided, the first substrate 1 has a first surface 10 and a second surface 12, and the first surface 10 and the second surface 12 are opposite to each other along an axial direction Y. Here, the first surface 10 and the second surface 12 being opposite to each other along the axial direction Y means that: the first surface 10 and the second surface 12 are located at different heights in the axial direction Y, and the direction in which the first surface 10 faces and the direction in which the second surface 12 faces are opposite to each other. In the present embodiment, the first substrate 1 is, for example, a polypropylene substrate. However, in other embodiments, the first substrate 1 may be a polyimide substrate, a polymethyl methacrylate substrate, a glass substrate, a ceramic substrate, or a silicon-on-insulator substrate.

Referring to fig. 2, a first conductive line layer 2 is formed on the first surface 10 and the second surface 12 of the first substrate 1, respectively. In the present embodiment, the material of the first conductive line layer 2 is copper, but in other embodiments, the material of the first conductive line layer 2 may be other conductive materials, for example: aluminum. Furthermore, in other embodiments, the first wire layer 2 may also be formed only on the first surface 10 or the second surface 12.

Thereafter, referring to fig. 3, the first conductive line layer 2 is etched (e.g., wet etched) to form a plurality of first conductive lines 20. After the etching is completed, a first hole 22 is formed by etching beside the first conductive line 20, and the size of the aperture or width of the first hole 22 is tapered toward the substrate 1 and exposes the surface of the first substrate 1 (i.e., the first surface 10 and the second surface 12). In the present embodiment, the etching factor of the first conductive line 20 is 2.3 or more; in other words, the etching factor of the walls of the first pores 22 is 2.3 or more. In the present invention, the definition of the etching factor may be: etched layer thickness/(etched layer bottom width-etched layer top width). For example, the etching factor of the first conductive line 20 may be defined as: thickness of the first conductive line 20/(lower width of the first conductive line 20-upper width of the first conductive line 20). Alternatively, in the present invention, the etching factor may be defined as: etched layer thickness/width of hole wall lateral etch.

Then, referring to fig. 4 and 5, at least one second conductive line layer 3 is provided, and the second conductive line layer 3 is overlapped on the first conductive line layer 2 on which the plurality of first conductive lines 20 are formed. In fig. 4, the arrow indicates the direction of overlap. In this embodiment, the second conductive line layer 3 is a metal plate, and the metal plate is made of copper. Furthermore, in the present embodiment, before the second conductive line layer 3 is laminated on the first conductive line layer 2, the surfaces of the second conductive line layer 3 and the first conductive line layer 2 are processed by planarization technology. In this embodiment, the planarization technique is a chemical mechanical polishing technique.

Further, referring to fig. 5, the first conductive line layer 2 and the second conductive line layer 3 may be stacked by using a low temperature copper-to-copper bonding technique. Regarding low temperature copper-to-copper bonding techniques, reference may be made to the following documents:

Chien-Min Liu,Han-Wen Lin,Yi-Sa Huang,Yi-Cheng Chu,Chih Chen,Dian-Rong Lyu,Kuan-Neng Chen&King-Ning Tu.(2015).Low-temperature direct copper-to-copper bonding enabled by creep on(111)surfaces of nanotwinned Cu.Scientific Reports,5:09734.doi:10.1038/srep09734

in the above document, the minimum operating temperature for copper-to-copper bonding is 150 ℃ and the time required is 1 hour; if the temperature is 250 ℃, the time required is 10 minutes. In the circuit board industry, the operating temperature is typically less than 200 ℃. In this example, the operating temperature is 190-200 ℃.

Next, referring to fig. 6, the second conductive line layer 3 is etched to form a plurality of second conductive lines 30 on the second conductive line layer 3. After the etching is completed, a second hole 32 is formed by etching beside the second wire 30. In the present embodiment, the second hole 32 penetrates the second conductive wire layer 3, and the first hole 22 and the second hole 32 penetrate each other along the axial direction Y, and the aperture or width of the second hole 32 is tapered from top to bottom toward the first hole 22. In the present embodiment, the etching factor of the second conductive line 30 is 2.3 or more; in other words, the etching factor of the walls of the second pores 32 is 2.3 or more. Since the etching factor of the first conductive line 20 and the second conductive line 30 is greater than or equal to 2.3, the etching factor of the stacked conductive line 40 formed by bonding the first conductive line 20 and the second conductive line 30 together along the axial direction Y is also greater than or equal to 4.6. In addition, in this or other embodiments, the first aperture 22 and the second aperture 32 may be referred to as holes (holes) or gaps (gaps) between wires.

It should be noted that the steps shown in fig. 4 and 6 may be repeated to manufacture the stacked wire 40 with a higher etching factor. For example, after a conductive layer is further stacked on the second conductive line 30, the conductive layer is etched to form a stacked conductive line 40 with a higher etching factor.

Then, referring to fig. 7, a dielectric material 4 is filled in the first hole 22 and the second hole 32, and the dielectric material 4 is, for example, resin, epoxy, solder mask or other adhesive material, so that the dielectric material 4 is filled to better avoid occurrence of short circuit or dielectric breakdown between the stacked wires 40. Please refer to fig. 7 again. In this embodiment, after the filling of the dielectric material 4 is completed, a surface treatment may be performed on the outer surfaces of the dielectric material 4 and the stacked wire 40 (precisely, the second wire layer 3), for example, a surface protection layer 7 and a solder resist ink 8 are formed on the outer surfaces of the dielectric material 4 and the stacked wire 40, wherein the surface protection layer 7 is disposed on the stacked wire 40, the solder resist ink 8 is disposed on the dielectric material 4, and the solder resist ink 8 covers a portion of the surface of the stacked wire 40. The surface protection layer 7 is used for protecting the stacked wires 40, and the material of the surface protection layer 7 is, for example, nickel-palladium immersion gold (ENEPIG), an organic solder (organic solderability preservatives, OSP) layer, or electroless nickel immersion gold (Electroless Nickel Immersion Gold, ENEPIG), but not limited thereto.

Thus, the printed circuit board 100 is manufactured, and the conductive lines (i.e., the stacked conductive lines 40) of the printed circuit board 100 have a high etching factor. In the process of manufacturing the printed circuit board 100, the respective conductive layers (i.e., the first conductive line layer 2 and the second conductive line layer 3) are etched, so that the printed circuit board 100 with higher etching factor of the conductive lines can be obtained.

Next, a second embodiment of the method for manufacturing a printed circuit board according to the present invention will be described with reference to fig. 8 to 13. In the second embodiment, the same or similar components as those of the first embodiment will be denoted by the same reference numerals. First, referring to fig. 8, a first substrate 1 is provided, the first substrate 1 has a first surface 10 and a second surface 12, and the first surface 10 and the second surface 12 are opposite to each other along an axial direction Y. Referring to fig. 9, a first conductive line layer 2 is formed on the first surface 10 and the second surface 12 of the first substrate 1, respectively. Thereafter, referring to fig. 10, the first conductive line layer 2 is etched to form a plurality of first conductive lines 20. After the etching is completed, a first hole 22 is formed by etching beside the first conductive line 20, and the first hole 22 exposes the surface of the first substrate 1 (i.e., the first surface 10 and the second surface 12). In the present embodiment, the etching factor of the first conductive line 20 is 2.3 or more; in other words, the etching factor of the walls of the first pores 22 is 2.3 or more. Thereafter, the surface of the first wire layer 2 on which the plurality of first wires 20 have been formed will be subjected to a planarization technique. In this embodiment, the planarization technique is a chemical mechanical polishing technique. Next, referring to fig. 11, the first hole 22 is filled with a dielectric material 4a.

Referring to fig. 12, a second substrate 6 is provided, and a second conductive line layer 3 is formed on two opposite surfaces of the second substrate 6. In addition, the second conductive line layer 3 has a plurality of etched second conductive lines 30, and a second hole 32 formed by etching is formed beside the second conductive lines 30, wherein the etching factor of the second conductive lines 20 is greater than or equal to 2.3. In addition, the second aperture 32 is filled with a dielectric material 4b. In the present embodiment, the second conductive line 30, the second hole 32, and the dielectric material 4b on the second substrate 6 may be formed in the same manner as the first conductive line 20, the first hole 22, and the dielectric material 4a on the first substrate 1; accordingly, the manner in which the second conductive line 30, the second aperture 32, and the dielectric material 4b are formed will not be described in detail herein.

Then, referring to fig. 12, the second conductive wires 30 on one surface of the second substrate 6 are combined with the first conductive wires 20 on one surface of the first substrate 1 along the axial direction Y. When the first and second holes 22 and 32 are combined, the positions of the first and second holes 22 and 32 correspond to each other, that is, the first and second holes 22 and 32 are mutually communicated along the axial direction Y after the combination (as shown in fig. 13); in addition, the positions of the first and second wires 20 and 30 may also correspond to each other. It should be noted that, before bonding, a planarization technique, which is a chemical mechanical polishing technique, is applied to the surface of the second conductive line 30. In this embodiment, the second wire 30 is bonded to the first wire 20 using a low temperature copper-to-copper bonding technique.

Referring to fig. 13, the second conductive line 30 is combined with the first conductive line 20 to form a stacked conductive line 40. Since the etching factor of the first conductive line 20 and the second conductive line 30 is greater than or equal to 2.3, the etching factor of the stacked conductive line 40 formed by bonding the first conductive line 20 and the second conductive line 30 together along the axial direction Y is also greater than or equal to 4.6. After the fabrication of the stacked wires 40 is completed, the outer surface of the second wires 30 on the other surface of the second substrate 6 and the outer surface of the first wires 20 on the other surface of the first substrate 1 may be surface-treated. In the present embodiment, the surface treatment includes applying a surface protection layer 7 and solder resist ink 8, wherein the surface protection layer 7 is disposed on the first conductive line 20 and the second conductive line 30 for protecting the first conductive line 20 and the second conductive line 30. The solder resist ink 8 is disposed on the dielectric material 4a and the dielectric material 4b, and the solder resist ink 8 covers a portion of the first conductive line 20 and a portion of the second conductive line 30.

Thus, the printed circuit board 200 is manufactured, and the conductive lines (i.e., the stacked conductive lines 40) of the printed circuit board 200 have a high etching factor. Compared with the first embodiment, the second conductive line layer 3 is etched and then combined with the first conductive line layer 2 in the present embodiment, but the respective conductive layers (i.e. the first conductive line layer 2 and the second conductive line layer 3) are etched, so that the printed circuit board 200 with higher etching factor of the conductive lines can be obtained.

A third embodiment of the method for manufacturing a printed circuit board according to the present invention will be described below with reference to fig. 14 to 21. In the third embodiment, the same or similar components as those of the second embodiment will be denoted by the same reference numerals. First, referring to fig. 14, a first substrate 1 is provided, the first substrate 1 has a first surface 10 and a second surface 12, and the first surface 10 and the second surface 12 are opposite to each other along an axial direction Y. Referring to fig. 15, a first conductive line layer 2 is formed on the first surface 10 and the second surface 12 of the first substrate 1, respectively. Thereafter, referring to fig. 16, the first conductive line layer 2 is etched to form a plurality of first conductive lines 20. After the etching is completed, a first hole 22 is formed by etching beside the first conductive line 20, and the first hole 22 exposes the surface of the first substrate 1 (i.e., the first surface 10 and the second surface 12). In the present embodiment, the etching factor of the first conductive line 20 is 2.3 or more; in other words, the etching factor of the walls of the first pores 22 is 2.3 or more. Next, referring to fig. 17, the first hole 22 is filled with a dielectric material 4a.

Then, referring to fig. 18, the dielectric material 4a on the first surface 10 is coated with an adhesive layer 9. The material of the adhesive layer 9 is mainly resin, epoxy resin or other non-conductive adhesive material. Next, referring to fig. 19, a conductive paste 5 is coated on the first conductive wire 20 on the first surface 10, and the conductive paste 5 is, for example, a conductive copper paste (cup). In this embodiment, the conductive paste 5 may be coated on the first conductive line 20 by printing.

Then, referring to fig. 20, a second substrate 6 is provided, and a second conductive line layer 3 is formed on each of two opposite surfaces of the second substrate 6. In addition, the second conductive line layer 3 has a plurality of etched second conductive lines 30, and a second hole 32 formed by etching is formed beside the second conductive lines 30, wherein the etching factor of the second conductive lines 20 is greater than or equal to 2.3. In addition, the second aperture 32 is filled with a dielectric material 4b. In the present embodiment, the second conductive line 30, the second hole 32, and the dielectric material 4b on the second substrate 6 may be formed in the same manner as the first conductive line 20, the first hole 22, and the dielectric material 4a on the first substrate 1; accordingly, the manner in which the second conductive line 30, the second aperture 32, and the dielectric material 4b are formed will not be described in detail herein.

Then, referring to fig. 20, the second conductive wires 30 on one surface of the second substrate 6 and the first conductive wires 20 on one surface of the first substrate 1 are combined along the axial direction X by the adhesive layer 9 and the conductive adhesive 5. When combined, the positions of the first and second apertures 22, 32 correspond to each other, and the positions of the first and second wires 20, 30 correspond to each other. Furthermore, the bonding of the second wire 30 and the first wire 20 is performed, for example, at a specific temperature to cure the adhesive layer 9 and the conductive adhesive 5.

Referring to fig. 21, the second conductive line 30, the conductive adhesive 5, and the first conductive line 20 are combined to form a stacked conductive line 40. Since the etching factor of the first conductive line 20 and the second conductive line 30 is greater than or equal to 2.3, the etching factor of the stacked conductive line 40 formed by bonding the first conductive line 20 and the second conductive line 30 together along the axial direction X is also greater than or equal to 4.6. After the fabrication of the stacked wires 40 is completed, the surface treatment may be performed on the second wires 30 on the other surface of the second substrate 6 and the first wires 20 on the other surface of the first substrate 1. In this embodiment, the surface treatment step includes the addition of a surface protective layer 7 and a solder resist ink 8.

Thus, the printed circuit board 300 is manufactured, and the conductive lines (i.e., the stacked conductive lines 40) of the printed circuit board 300 have a high etching factor. In comparison with the second embodiment, the second conductive line layer 3 is bonded to the first conductive line layer 2 by the conductive paste 5 instead of using the low temperature copper-to-copper bonding technique. Further, in the present embodiment, a planarization technique such as chemical mechanical polishing may not be used. In the present embodiment, since the respective conductive layers (i.e., the first conductive line layer 2 and the second conductive line layer 3) are still etched, the printed circuit board 300 with higher etching factor of the conductive lines can be obtained.

In the above embodiment, the first conductive layer 2 is disposed on both the first surface 10 and the second surface 12 of the first substrate 1, but the first conductive layer 2 may be disposed on only one surface (the first surface 10 or the second surface 12) of the first substrate 1. Referring to fig. 22, fig. 22 shows a fourth embodiment of the printed circuit board of the present invention. In the present embodiment, the printed circuit board 400 includes a first substrate 1, a first conductive line layer 2, and a second conductive line layer 3. The first substrate 1 has a first surface 10 and a second surface 12, and the first surface 10 and the second surface 12 are opposite along an axial direction X. The first conductive line layer 2 is formed on the first surface 10 of the first substrate 1, the first conductive line layer 2 has at least one first conductive line 20 (a plurality of first conductive lines in this embodiment), and at least one first hole 22 (a plurality of first holes in this embodiment) is disposed beside the first conductive line 20, and the first hole 22 is etched. Wherein the etching factor of the first conductive line 20 is greater than or equal to 2.3. In addition, the second conductive line layer 3 is formed on the first conductive line layer 2, and the second conductive line layer 3 has at least one second conductive line 30 (a plurality in the present embodiment), and the second conductive line 30 is provided with at least one second hole 32 (a plurality in the present embodiment). Wherein the etching factor of the second conductive line 30 is greater than or equal to 2.3. In addition, the first aperture 22 and the second aperture 32 are mutually communicated along the axial direction Y, and the first aperture 22 and the second aperture 32 are filled with the dielectric material 4. The first conductive line 20 and the second conductive line 30 are bonded to each other along the axial direction Y to form a stacked conductive line 40, and an etching factor of the stacked conductive line 40 is greater than or equal to 4.6. In addition, a surface protection layer 7 and a solder resist ink 8 are formed on the outer surfaces of the dielectric material 4 and the laminated wire 40, wherein the surface protection layer 7 is disposed on the laminated wire 40, the solder resist ink 8 is disposed on the dielectric material 4, and the solder resist ink 8 covers a portion of the surface of the laminated wire 40. The manufacturing method of the printed circuit board 400 is substantially the same as the manufacturing method of the printed circuit board 100 (see fig. 1 to 7), and the main differences are that: the printed circuit board 400 is manufactured without any components on the second surface 12, and thus the manufacturing method of the printed circuit board 400 is not described in detail herein.

In summary, when the printed circuit board of the present invention is manufactured, the printed circuit board with higher etching factor of the conductive lines can be obtained due to etching the respective conductive layers. In addition, in the above embodiment, the dielectric material 4 is filled in the first hole 22 and the second hole 32 to increase the insulation between the stacked wires 40, but one skilled in the art may choose not to fill the dielectric material 4 in the first hole 22 and the second hole 32.

The invention is described above without limiting the scope of the claims. Modifications and variations which may be made by those skilled in the art without departing from the spirit or scope of the invention are intended to be included within the scope of the following claims.

Claims

1. A printed circuit board, comprising:

the first substrate is provided with a first surface and a second surface, and the first surface and the second surface are opposite along an axial direction;

at least one first wire layer formed on the first surface and/or the second surface of the first substrate, wherein the first wire layer is provided with at least one first wire etched and at least one first hole formed by etching beside the first wire, and the etching factor of the first wire is more than or equal to 2.3; a kind of electronic device with high-pressure air-conditioning system

At least one second wire layer formed on the first wire layer, wherein the second wire layer is provided with at least one second wire etched and at least one second hole formed by etching beside the second wire, and the etching factor of the second wire is more than or equal to 2.3;

the first wire and the second wire are mutually jointed along the axial direction to form a laminated wire, and the etching factor of the laminated wire is more than or equal to 4.6.

2. The printed circuit board of claim 1, wherein the bonding between the first wire and the second wire uses a low temperature copper-to-copper bonding technique.

3. The printed circuit board of claim 1, wherein the first conductive line and the second conductive line are bonded by a conductive adhesive.

4. The printed circuit board of claim 1, wherein the first aperture and the second aperture are interconnected along the axial direction, and the first aperture and the second aperture are filled with a dielectric material.

5. The printed circuit board of claim 2, wherein the bonding between the first wire and the second wire comprises using a planarization technique.

6. The printed circuit board of claim 5, wherein the planarization technique is a chemical mechanical polishing technique.

7. The printed circuit board of claim 1, wherein a solder resist ink is formed on an outer surface of the second conductive line layer and/or the stacked conductive lines.

8. The printed circuit board of claim 1, wherein the second conductive line layer is disposed on a second substrate surface.

9. A method of manufacturing a printed circuit board, comprising:

forming at least one first wire layer on the first surface and/or the second surface of the first substrate, wherein the first wire layer is provided with at least one first wire etched and at least one first hole formed by etching beside the first wire, and the etching factor of the first wire is more than or equal to 2.3;

forming at least one second wire layer on the first wire layer, wherein the second wire layer is provided with at least one second wire etched and at least one second hole formed by etching beside the second wire, and the etching factor of the second wire is more than or equal to 2.3; a kind of electronic device with high-pressure air-conditioning system

10. The method of claim 9, wherein the bonding between the first conductive line and the second conductive line is performed using a low temperature copper-to-copper bonding technique.

11. The method of claim 9, wherein the first conductive line and the second conductive line are bonded by a conductive adhesive.

12. The method of claim 9, wherein the first and second holes are formed through each other along the axial direction, and the first and second holes are filled with a dielectric material.

13. The method of claim 9, wherein the bonding between the first conductive line and the second conductive line comprises using a planarization technique.

14. The method of claim 13, wherein the planarization technique is chemical mechanical polishing.

15. The method of claim 9, wherein the second conductive line layer and/or the outer surface of the stacked conductive lines is subjected to a surface treatment step.

16. The method of claim 9, wherein the second conductive line layer is disposed on a surface of a second substrate.