CN117292729A - Circuit structure for reading ground terminal of flash memory - Google Patents

Abstract

The invention discloses a circuit structure for reading a grounding end of a flash memory, which comprises the following components: a first current path and a second current path that are mirror images of each other. The selected memory cell is located on the first current path. The drain of the selected memory cell is connected to a first voltage, which is a fixed voltage. The source of the selected memory cell is connected to ground through the input side circuit of the current mirror and forms a cell current in a first current path. The second current path comprises a mirror side circuit of the current mirror, and the mirror side circuit of the current mirror forms a unit mirror current and outputs the unit mirror current at an output end of the second current path; the cell mirror current is proportional to the cell current. The unit image current is connected with the sense amplifier. The invention can carry out the ground terminal reading to the storage unit of the flash memory, and prevent the influence of the change of the drain voltage on the reading current when the storage unit of the flash memory is read from the drain terminal of the storage unit of the flash memory, thereby eliminating the limitation of the source drain voltage of the storage unit of the flash memory on the reading speed and the 0/1 window, and increasing the reading speed and the 0/1 window.

Description

Circuit structure for reading ground terminal of flash memory

Technical Field

The present invention relates to a semiconductor integrated circuit, and more particularly, to a circuit structure for ground sensing (ground sensing) of a flash memory.

Background

As shown in fig. 1, the conventional sense amplifier circuit reads a circuit diagram of a memory cell of a flash memory; the existing sense amplifier circuit includes: and a bit line adjusting unit connected between the bit line node A and the data line node C.

The bit line adjustment unit includes a first NMOS transistor MN101.

The drain electrode of the first NMOS transistor MN101 is connected with the data line node C, and the source electrode of the first NMOS transistor MN101 is connected with the bit line node A.

A feedback circuit is arranged between the gate of the first NMOS transistor MN101 and the bit line node a, and the feedback circuit is composed of an inverter 102.

An input terminal of the inverter 102 is connected to the bit line node a, and an output terminal of the inverter 102 is connected to a gate of the first NMOS transistor MN101 as a feedback node B.

The voltage of the feedback node B is the inverse signal of the bit line node A. When the voltage of the node A is smaller, the voltage of the node B is larger; when the voltage of node a is large, the voltage of node B is small. But the node B high-low level transition is not abrupt, but has a flip region located near the clamp voltage Vclamp. When the voltage of the node A is greater than the voltage Vclamp, the voltage of the node B can be turned to a low level; and when the voltage of node a is less than Vclamp, the voltage of node B will flip to a high level. In fig. 1, after the precharge, the voltage at the node a is clamped to the clamp voltage Vclamp. The first NMOS transistor MN101 is also called a clamp (clamp) transistor (transistor).

When the memory cell 101 is located in the memory array of the flash memory and is read, the memory cell 101 to be read, that is, the selected memory cell 101, needs to be selected by the decoder 105. Decoder 105 is a column decoder and selects a bit line from a plurality of bit lines, which is connected to the drain of the selected memory cell 101. In fig. 1, the decoder 105 is represented by an NMOS transistor MN102, and the decoding signal YA is input to the control terminal of the decoder 105.

Upon reading, the bit line node A is connected to the selected memory cell 101, the voltage of the bit line node A being determined by the memory state of the memory cell 101.

A current source Iref is connected between the data line node C and a power supply voltage Vdd, the current of which is used as a reference current for comparison with the cell current of the memory cell 101; at the time of reading, a first output voltage is formed at the data line node C by comparing the current of the current source Iref and the cell current.

The sense amplifier circuit further comprises an output unit 102; the first output voltage is input to the input terminal of the output unit 102 and outputs a second output voltage Sout at the output terminal of the output unit 102. In fig. 1, the output unit 102 includes a comparator.

The first output voltage is connected to a first input terminal, i.e., the + terminal, of the comparator.

The second input end, namely the end, of the comparator is connected with the reference voltage Vref.

The output end of the comparator outputs the second output voltage Sout.

As shown in fig. 1, the read current of the memory cell 101 is taken from the drain, so that the read current is drain-side read (Drainsensing structure. Since the drain of the memory cell 101 is connected to the bit line, the decoder 105 selects the bit line to which the drain of the memory cell 101 is connected during the read, the drain voltage VD of the memory cell 101 is the bit line voltage vbl. The source of the memory cell 101 is grounded.

In this drain-side reading method, the read current of the memory cell 101 is affected by the source-drain voltage Vds, which is the difference between VD and ground, in addition to the memory state. However, in the conventional circuit, vds may fluctuate, for example, the voltage of the bit line node a may be affected by the fluctuation of the power supply voltage of the inverter 102, and the voltage of the bit line node a may be affected by VD, and finally, vds may be affected.

As the size of the memory cell 101 decreases with scaling, the effect of Vds on the source drain current, i.e., the read current, of the memory cell 101 becomes larger and larger, and eventually the read speed and 0/1 window are affected. The 0/1 window is a window of a range of threshold voltages when the memory states of the memory cell 101 are 1 and 0, and the threshold voltages correspond to the read currents, so that the window of threshold voltages also corresponds to a range of read currents when the memory states are 1 and 0.

In fig. 1, the memory cell 101 employs a dual split gate floating gate device, which includes two memory bits, the control gate of the memory bit to be read is grounded, the word line is connected to the word line read voltage VWLR, and the control gate of the memory bit not to be read is connected to the control gate read voltage VCGR.

Disclosure of Invention

The invention provides a circuit structure for reading a grounding end of a flash memory, which can read a storage unit of the flash memory by the grounding end, prevent the influence of the change of drain voltage on the reading current when the storage unit of the flash memory is read from a drain end of the storage unit of the flash memory, and further eliminate the limitation of the source drain voltage of the storage unit of the flash memory on the reading speed and a 0/1 window, thereby increasing the reading speed and the 0/1 window.

The circuit structure for reading the grounding end of the flash memory provided by the invention comprises the following components: a first current path and a second current path that are mirror images of each other.

A selected memory cell of the flash memory is located on the first current path.

The drain of the selected memory cell is connected to a first voltage, which is a fixed voltage.

The source of the selected memory cell is connected to the input side circuit of the current mirror and the transistor connected through the diode of the input side circuit of the current mirror is grounded and forms a cell current in the first current path.

The second current path comprises a mirror side circuit of the current mirror, and the mirror side circuit of the current mirror forms a unit mirror current and outputs the unit mirror current at an output end of the second current path; the cell mirror current is proportional to the cell current.

The unit mirror current is connected to the sense amplifier.

A further improvement is that the source electrode of the selected memory cell is connected with the input side circuit of the current mirror through a column decoding circuit; the control end of the column decoding signal circuit is connected with a column decoding signal, and the connection between the source electrode of the selected storage unit and the input side circuit of the current mirror is realized under the selection of the column decoding signal.

Further improvement is that the method further comprises: a first charge pump, the first voltage being provided by the first charge pump.

Further improvement is that the method further comprises: a source follower.

The output end of the first charge pump is connected with the input end of the source electrode follower, and the output end of the source electrode follower outputs the first voltage.

The source follower is composed of a first NMOS tube, the grid electrode of the first NMOS tube is an input end, and the source electrode of the first NMOS tube is an output end.

The drain electrode of the first NMOS tube is a power end and is connected to a power voltage.

The input side circuit of the current mirror comprises a second NMOS tube connected with a diode, the source electrode of the second NMOS tube is grounded, and the drain electrode and the grid electrode of the second NMOS tube are connected together and connected with the source electrode of the selected storage unit.

The mirror side circuit of the current mirror comprises a third NMOS tube, wherein the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is used as the output end of the second current path and outputs the unit mirror current.

The threshold voltage of the third NMOS tube is equal to that of the second NMOS tube.

The second NMOS transistor and the third NMOS transistor are native transistors.

The threshold voltage of the second NMOS tube is less than 0.2V and greater than 0V.

The further improvement is that the cell mirror current is greater than or equal to the cell current.

In a further improvement, the first voltage is 1V or more.

A further improvement is that the sense amplifier comprises a current comparator comprising a reference current, the reference current being compared with the cell mirror current to form a first output voltage.

A further improvement is that the sense amplifier further comprises a first output circuit, the first output voltage being connected to the first output voltage, the output of the first output circuit outputting a second output voltage.

A further improvement is that the first output circuit comprises an inverter.

In a further improvement, the flash memory comprises a plurality of memory cells, each memory cell forming a memory array, the selected memory cell being the memory cell selected from the memory array.

Each of the memory cells employs a split gate floating gate device.

The split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, a plurality of separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned on the top of the floating gate, and the floating gate is used as a storage bit.

The first and second source and drain regions of each memory cell are connected to a corresponding bit line.

The separation gate floating gate device is a double separation gate floating gate device, and the number of the first gate structures is two.

In a further improvement, the split gate floating gate device is an N-type device, and the first source drain region and the second source drain region are both composed of an N+ region.

The P-type doped channel region is located between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure respectively controls a region section of the covered channel region.

In the invention, the drain electrode of the selected memory cell is connected to the fixed first voltage, the source electrode of the selected memory cell is grounded through the input side circuit of the current mirror and forms a cell current in the first current path, the cell current forms a cell mirror current in the second current path mirrored through the current mirror, and the cell mirror current is input to the sense amplifier for reading.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a circuit diagram of a conventional sense amplifier circuit reading a memory cell of a flash memory;

FIG. 2 is a circuit diagram of a ground read of a flash memory according to an embodiment of the present invention.

Detailed Description

As shown in FIG. 2, a circuit structure diagram of a ground read of a flash memory according to an embodiment of the present invention is shown. The circuit structure for reading the grounding end of the flash memory comprises: a first current path 201 and a second current path that are mirror images of each other.

The selected memory cell 101 of the flash memory is located on the first current path 201. Of the memory cells 101 of the flash memory, only the selected memory cell 101 is shown in fig. 2.

The drain of the selected memory cell 101 is connected to a first voltage VD, which is a fixed voltage.

The source of the selected memory cell 101 is connected to the input side circuit 204 of the current mirror 203 and the transistor connected through the diode of the input side circuit 204 of the current mirror 203 is grounded and forms a cell current in the first current path 201.

The second current path includes a mirror side circuit 205 of the current mirror 203, and the mirror side circuit 205 of the current mirror 203 forms a unit mirror current and outputs the unit mirror current at an output terminal of the second current path; the cell mirror current is proportional to the cell current. In fig. 2, the second current path is a mirror side circuit 205 of the current mirror 203, and in other embodiments, the second current path can be modified as needed.

The cell mirror current is coupled to sense amplifier 208.

In the embodiment of the present invention, the source of the selected memory cell 101 is connected to the input side circuit 204 of the current mirror 203 through the column decoding circuit 206; the control terminal of the column decode signal circuit is connected to a column decode signal YA, and the connection between the source of the selected memory cell 101 and the input side circuit 204 of the current mirror 203 is realized under the selection of the column decode signal YA. In the array structure of the flash memory, the source of the selected memory cell 101 is connected to the bit line of the corresponding column, so that the column decoding circuit 206 connects the bit line connected to the source of the selected memory cell 101 to the input side circuit 204 of the current mirror 203.

In the embodiment of the invention, the method further comprises the following steps: a first charge pump 202, the first voltage VD being provided by the first charge pump 202.

Further comprises: source follower 207.

An output terminal of the first charge pump 202 is connected to an input terminal of the source follower 207, and an output terminal of the source follower 207 outputs the first voltage VD.

The source follower 207 is composed of a first NMOS transistor MN201, a gate of the first NMOS transistor MN201 is an input end, and a source of the first NMOS transistor MN201 is an output end.

The drain of the first NMOS transistor MN201 is a power terminal and is connected to a power voltage.

As can be seen from fig. 2, the output terminal of the first charge pump 202 outputs a voltage VR, which can be selected according to the need, but is fixed after VR is selected, so that the first voltage VD is also fixed, and therefore the drain of the selected memory cell 101 is an adjustable drain (regulated drain). In fig. 2, VD is smaller than VR by one threshold voltage of the first NMOS transistor MN 201.

The input side circuit 204 of the current mirror 203 includes a second NMOS transistor MN202 connected to a diode, where a source of the second NMOS transistor MN202 is grounded, and a drain and a gate of the second NMOS transistor MN202 are connected together and connected to a source of the selected memory cell 101.

The mirror side circuit 205 of the current mirror 203 includes a third NMOS transistor MN203, where a gate of the third NMOS transistor MN203 is connected to a gate of the second NMOS transistor MN202, a source of the second NMOS transistor MN202 is grounded, and a drain of the second NMOS transistor MN202 is used as an output end of the second current path and outputs the unit mirror current.

The threshold voltage of the third NMOS transistor MN203 is equal to the threshold voltage of the second NMOS transistor MN 202.

The second NMOS transistor MN202 and the third NMOS transistor MN203 both use native transistors. The threshold voltage of the native transistor is smaller, typically near 0V, than conventional transistors.

In some embodiments, the threshold voltage of the second NMOS transistor MN202 is 0.2V or less and greater than 0V. When the threshold voltage of the second NMOS transistor MN202 is 0.2V, the source voltage VS of the selected memory cell 101 is 0.2V.

In some embodiments, the first voltage VD is 1V or greater. If the first voltage VD is 1V and vs is 0.2V, then the source-drain voltage of the selected memory cell 101 is 0.8V, which is fixed, so that no adverse limitation is imposed on the source-drain current, i.e., cell current, of the selected memory cell 101. Thereby solving the technical problems existing in the prior art.

The cell mirror current is equal to or greater than the cell current.

The sense amplifier 208 includes a current comparator that includes a reference current Iref that is compared to the cell mirror current to form a first output voltage Vo.

The sense amplifier 208 further includes a first output circuit 209, the first output voltage Vo is connected to the first output voltage Vo, and an output terminal of the first output circuit 209 outputs a second output voltage Sout.

In some embodiments, the first output circuit 209 includes an inverter. In other embodiments, a comparator implementation can also be employed.

The flash memory comprises a plurality of memory cells 101, each memory cell 101 forms a memory array, and the selected memory cell 101 is the memory cell 101 selected from the memory array.

Each of the memory cells 101 employs a split gate floating gate device.

The split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, a plurality of separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned on the top of the floating gate, and the floating gate is used as a storage bit.

The first source drain region and the second source drain region of each of the memory cells 101 are connected to the corresponding bit line.

In some preferred embodiments, the split gate floating gate device is a dual split gate floating gate device and the number of first gate structures is two. The selected memory cell in fig. 2 includes two first gate structures, wherein the floating gate of the first gate structure with the control gate grounded is used as a memory bit to be read, and the control gate corresponding to the other memory bit needs to be connected to a control gate read voltage VCGR, where VCGR needs to ensure that the channel of the area covered by the first gate structure that does not need to be read is turned on. The second gate structure is connected to a word line, and the word line of the selected memory cell 101 is connected to a word line read voltage VWLR, which is required to ensure channel conduction in the area covered by the second gate structure.

The separation gate floating gate device is an N-type device, and the first source drain region and the second source drain region are both composed of an N+ region.

The P-type doped channel region is located between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure respectively controls a region section of the covered channel region.

In the embodiment of the invention, the drain electrode of the selected memory cell 101 is connected to the fixed first voltage VD, the source electrode of the selected memory cell 101 is grounded through the input side circuit 204 of the current mirror 203 and forms a cell current in the first current path 201, the cell current forms a cell mirror current in the second current path by mirroring through the current mirror 203, and the cell mirror current is input to the sense amplifier 208 for reading, so that the read current of the embodiment of the invention is not taken out from the drain electrode of the selected memory cell 101 but taken out through the mirror current of the cell current output by the source electrode of the selected memory cell 101, and the source electrode of the selected memory cell 101 is positioned at the grounded side, thus, the potential of the drain electrode and the source electrode of the selected memory cell 101 can be well fixed, the influence of the change of the voltage difference between the source electrode and the drain electrode of the selected memory cell 101 on the read current can be prevented, and the limitation of the source electrode of the memory cell 101 on the read speed and the 0/1 window can be eliminated, and the read speed and the 0/1 window can be increased, especially when the size of the memory cell 101 is reduced.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (17)

1. A circuit structure for reading a ground terminal of a flash memory, comprising: a first current path and a second current path that are mirror images of each other;

a selected memory cell of a flash memory is located on the first current path;

the drain electrode of the selected storage unit is connected with a first voltage, and the first voltage is a fixed voltage;

the source of the selected memory cell is connected to the input side circuit of the current mirror and the transistor connected through the diode of the input side circuit of the current mirror is grounded and forms a cell current in the first current path;

the second current path comprises a mirror side circuit of the current mirror, and the mirror side circuit of the current mirror forms a unit mirror current and outputs the unit mirror current at an output end of the second current path; the cell mirror current is proportional to the cell current;

the unit mirror current is connected to the sense amplifier.

2. The circuit structure for ground side reading of flash memory of claim 1, wherein: the source electrode of the selected memory cell is connected with the input side circuit of the current mirror through a column decoding circuit; the control end of the column decoding signal circuit is connected with a column decoding signal, and the connection between the source electrode of the selected storage unit and the input side circuit of the current mirror is realized under the selection of the column decoding signal.

3. The circuit structure for ground side reading of flash memory of claim 1, further comprising: a first charge pump, the first voltage being provided by the first charge pump.

4. The circuit structure for ground side reading of flash memory of claim 3, further comprising: a source follower;

the output end of the first charge pump is connected with the input end of the source electrode follower, and the output end of the source electrode follower outputs the first voltage.

5. The circuit structure for ground side reading of flash memory as in claim 4, wherein: the source follower consists of a first NMOS tube, wherein the grid electrode of the first NMOS tube is an input end, and the source electrode of the first NMOS tube is an output end;

the drain electrode of the first NMOS tube is a power end and is connected to a power voltage.

6. The circuit structure for ground side reading of flash memory of claim 1, wherein: the input side circuit of the current mirror comprises a second NMOS tube connected with a diode, wherein the source electrode of the second NMOS tube is grounded, and the drain electrode and the grid electrode of the second NMOS tube are connected together and connected with the source electrode of the selected storage unit;

the mirror side circuit of the current mirror comprises a third NMOS tube, wherein the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is used as the output end of the second current path and outputs the unit mirror current.

7. The circuit structure for ground side reading of flash memory as in claim 6, wherein: the threshold voltage of the third NMOS tube is equal to the threshold voltage of the second NMOS tube.

8. The circuit structure for ground side reading of flash memory as in claim 7, wherein: and the second NMOS tube and the third NMOS tube are both native transistors.

9. The circuit structure for ground side reading of flash memory as in claim 8, wherein: the threshold voltage of the second NMOS tube is below 0.2V and greater than 0V.

10. The circuit structure for ground side reading of flash memory as in claim 6, wherein: the cell mirror current is equal to or greater than the cell current.

11. The circuit structure for ground side reading of flash memory of claim 9, wherein: the first voltage is greater than or equal to 1V.

12. The circuit structure for ground side reading of flash memory of claim 1, wherein: the sense amplifier includes a current comparator including a reference current that is compared to the cell image current to form a first output voltage.

13. The circuit structure for ground side reading of flash memory of claim 12, wherein: the sense amplifier further includes a first output circuit, the first output voltage being connected to the first output voltage, an output of the first output circuit outputting a second output voltage.

14. The circuit structure for ground side reading of flash memory of claim 13, wherein: the first output circuit includes an inverter.

15. The circuit structure for ground side reading of flash memory of claim 13, wherein: the flash memory comprises a plurality of memory cells, wherein each memory cell forms a memory array, and the selected memory cell is the memory cell selected from the memory array;

each storage unit adopts a split gate floating gate device;

the split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, a plurality of separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned at the top of the floating gate, and the floating gate is used as a storage bit;

the first and second source and drain regions of each memory cell are connected to a corresponding bit line.

16. The programming control circuit for a flash memory of claim 15, wherein: the split gate floating gate device is a double split gate floating gate device, and the number of the first gate structures is two.

17. The programming control circuit for a flash memory of claim 15, wherein: the separation gate floating gate device is an N-type device, and the first source drain region and the second source drain region are both composed of an N+ region;

the P-type doped channel region is located between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure respectively controls a region section of the covered channel region.