CN117275535A - Sense amplifier circuit - Google Patents

Sense amplifier circuit Download PDF

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Publication number
CN117275535A
CN117275535A CN202311387397.XA CN202311387397A CN117275535A CN 117275535 A CN117275535 A CN 117275535A CN 202311387397 A CN202311387397 A CN 202311387397A CN 117275535 A CN117275535 A CN 117275535A
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CN
China
Prior art keywords
voltage
sense amplifier
amplifier circuit
nmos tube
bit line
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Pending
Application number
CN202311387397.XA
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Chinese (zh)
Inventor
杨光军
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202311387397.XA priority Critical patent/CN117275535A/en
Publication of CN117275535A publication Critical patent/CN117275535A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

The invention discloses a sense amplifier circuit, comprising: and a bit line adjusting unit connected between the bit line node and the data line node. The bit line adjusting unit comprises a first NMOS tube. A feedback circuit is arranged between the grid electrode of the first NMOS tube and the bit line node, the feedback circuit comprises a first inverter, the input end of the first inverter is connected with the bit line node, the output end of the first inverter is connected to the grid electrode of the first NMOS tube, and the grid electrode of the first NMOS tube is the feedback node. The power supply bias circuit comprises a charge pump and a source follower, wherein the charge pump provides a first voltage to an input end of the source follower, an output end of the source follower outputs a second voltage to a power end of the first inverter, and the second voltage follows the change of the first voltage so as to eliminate voltage fluctuation of the power end of the first inverter. The invention can reduce the influence of power supply noise on the reading result.

Description

Sense amplifier circuit
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a Sense Amplifier (SA) circuit.
Background
As shown in fig. 1, a circuit diagram of a conventional sense amplifier circuit is shown; the existing sense amplifier circuit includes: a bit line adjustment unit 101 connected between a bit line node a and a data line node C.
The bit line adjustment unit 101 includes a first NMOS transistor MN101.
The drain electrode of the first NMOS transistor MN101 is connected with the data line node C, and the source electrode of the first NMOS transistor MN101 is connected with the bit line node A.
A feedback circuit is arranged between the gate of the first NMOS transistor MN101 and the bit line node a, and the feedback circuit is composed of an inverter 103. The inverter 103 is a CMOS inverter, and includes an NMOS transistor MN102 and a PMOS transistor MP101, where the NMOS transistor MN102 is used as a pull-down transistor, and the PMOS transistor MP101 is used as a pull-up transistor.
An input terminal of the inverter 103 is connected to the bit line node a, and an output terminal of the inverter 103 is connected to a gate of the first NMOS transistor MN101 as a feedback node B.
The voltage of the feedback node B is the inverse signal of the bit line node A. When the voltage of the node A is smaller, the voltage of the node B is larger; when the voltage of node a is large, the voltage of node B is small. But the node B high-low level transition is not abrupt, but has a flip region located near the clamp voltage Vclamp. When the voltage of the node A is greater than the voltage Vclamp, the voltage of the node B can be turned to a low level; and when the voltage of node a is less than Vclamp, the voltage of node B will flip to a high level. In fig. 1, after the precharge, the voltage at the node a is clamped to the clamp voltage Vclamp. The first NMOS transistor MN101 is also called a clamp (clamp) transistor (transistor).
Upon reading, the bit line node A is connected to a selected memory cell (cell) 104, the voltage of the bit line node A is determined by the memory state of the memory cell 104,
a current source Iref is connected between the data line node C and a power supply voltage Vdd, the current of which is used as a reference current for comparison with the cell current of the memory cell 104; at the time of reading, a first output voltage is formed at the data line node C by comparing the current of the current source Iref and the cell current.
The sense amplifier circuit further comprises an output unit 102; the first output voltage is input to the input terminal of the output unit 102 and outputs a second output signal Soutb at the output terminal of the output unit 102. In fig. 1, the output unit 102 includes a comparator.
The first output voltage is connected to a first input terminal, i.e., the + terminal, of the comparator.
The second input end, namely the end, of the comparator is connected with the reference voltage Vref.
The output end of the comparator outputs the second output signal Soutb.
A plurality of the memory cells 104 form a memory array. A decoding circuit 105 is further connected between the source of the first NMOS transistor MN101 and the bit line node a; in the reading, the decoding circuit 105 selects the corresponding column of the memory cell 104, and the word line voltage Vwl selects the corresponding row of the memory cell 104, thereby realizing the selection of the memory cell 104. The decoding circuit 105 is composed of a plurality of switch plus decoding signals, only one NMOS transistor MN103 and two decoding signals YA and YB are shown in fig. 1.
The memory cell 104 is a nonvolatile memory cell, and a gate structure of the nonvolatile memory cell includes a floating gate; the storage states of the nonvolatile memory cell include an erased state and a programmed state.
When the non-volatile memory unit is an N-type device, the non-volatile memory unit comprises an N+ doped source region and a N+ doped drain region, and electrons are stored in the floating gate in the programming state; in the erased state, electrons stored in the floating gate are removed.
The non-volatile memory cell has a first threshold voltage in a programmed state, the cell current being a read '0' cell current.
The non-volatile memory cell has a second threshold voltage in the erased state, the cell current being a read '1' cell current.
The first threshold voltage is greater than the second threshold voltage, and the read '0' cell current is less than the read '1' cell current. The greater the cell current, the lower the voltage of the bit line node a.
The information stored in the memory cell 104 having a programmed state is '0', and when reading '0', the cell current is the cell current of reading '0', and the voltage of the bit line node a is higher; the voltage of the feedback node B after the inversion of the inverter 103 is low, so that the first NMOS MN101 is turned off.
In practice, however, the supply voltage Vdd has a ripple, i.e. noise, as shown by the ripple curve of the sign 106; the feedback node B is directly connected to the power supply voltage Vdd through the pull-up tube of the inverter 103, i.e., the PMOS tube MP 101. When the power supply voltage Vdd fluctuates, for example, when a large overshoot (overschot) occurs, the PMOS transistor MP101 is turned on, so that the voltage of the feedback node B also follows the power supply voltage Vdd, and the current of the first NMOS transistor MN101 increases, the voltage of the data line node C decreases, the voltage of the data line node C also fluctuates as shown by a reference 107, and when the fluctuation is severe, if the voltage of the data line node C decreases below the reference voltage Vref, a flip occurs, resulting in a read '0' failure (fail).
Disclosure of Invention
The invention provides a sense amplifier circuit which can reduce the influence of power supply noise on a reading result.
The sense amplifier circuit provided by the invention comprises: and a bit line adjusting unit connected between the bit line node and the data line node.
The bit line adjustment unit includes a first NMOS tube.
The drain electrode of the first NMOS tube is connected with the data line node, and the source electrode of the first NMOS tube is connected with the bit line node.
The feedback circuit comprises a first inverter, wherein the input end of the first inverter is connected with the bit line node, the output end of the first inverter is connected to the grid electrode of the first NMOS tube, and the grid electrode of the first NMOS tube is a feedback node.
The power supply bias circuit comprises a charge pump and a source follower, wherein the charge pump provides a first voltage to an input end of the source follower, an output end of the source follower outputs a second voltage to a power end of the first inverter, and the second voltage follows the change of the first voltage so as to eliminate voltage fluctuation of the power end of the first inverter.
A further improvement is that the power supply terminal of the source follower is connected to a power supply voltage.
In a further improvement, the source follower includes a second NMOS transistor.
The grid electrode of the second NMOS tube is used as the input end of the source electrode follower, the source electrode of the second NMOS tube is used as the output end of the source electrode follower, and the drain electrode of the second NMOS tube is used as the power supply end of the source electrode follower.
A further improvement is that the bit line node is connected to a selected memory cell during reading.
The further improvement is that the first inverter is a CMOS inverter and comprises a third NMOS tube and a first PMOS tube.
And the grid electrode of the third NMOS tube and the grid electrode of the first PMOS tube are both connected with the bit line node.
And the source electrode of the third NMOS tube is grounded.
And the drain electrode of the third NMOS tube and the drain electrode of the first PMOS tube are both connected with the feedback node.
And the source electrode of the first PMOS tube is used as a power supply end of the first inverter.
A first current source is connected between the data line node and a power supply voltage, and the current of the first current source is used as a reference current for comparison with the cell current of the memory cell; in reading, a first output voltage is formed at the data line node by comparing the current of the first current source with the cell current.
A further improvement is that the sense amplifier circuit further comprises an output unit; the first output voltage is input to an input terminal of the output unit and outputs a second output voltage at an output terminal of the output unit.
A further improvement is that the output unit comprises a comparator.
The first output voltage is connected to a first input of the comparator.
The second input end of the comparator is connected with a reference voltage.
The output end of the comparator outputs the second output voltage.
A further improvement is that the memory cell is a non-volatile memory cell.
A further improvement is that a plurality of said memory cells form a memory array.
A decoding circuit is also connected between the source electrode of the first NMOS tube and the bit line node; and during reading, selecting the corresponding storage unit through the decoding circuit.
A further improvement is that the grid structure of the nonvolatile memory unit comprises a floating gate; the storage states of the nonvolatile memory cell include an erased state and a programmed state.
The non-volatile memory cell has a first threshold voltage in a programmed state, the cell current being a first cell current.
The non-volatile memory cell has a second threshold voltage in an erased state, the cell current being a second cell current.
The first threshold voltage is greater than the second threshold voltage, and the first cell current is less than the second cell current.
The greater the cell current, the lower the voltage of the bit line node.
The non-volatile memory cell is an N-type device and comprises a source region and a drain region which are doped with N < + >, and electrons are stored in the floating gate in the programming state; in the erased state, electrons stored in the floating gate are removed.
A further improvement is that the memory array is formed as part of a flash memory.
The flash memory is provided with a circuit which needs to adopt a third voltage, and the third voltage is larger than the power supply voltage.
The third voltage is also provided by the charge pump, enabling the charge pump sharing.
A further improvement is that a first resistor is connected between the output of the first voltage of the charge pump and the input of the source follower.
A further improvement is that the third voltage is equal to the first voltage.
Aiming at the problems that when the power supply end of the first inverter of the feedback circuit is connected with the power supply voltage, the voltage of the feedback node is easy to turn over due to the fluctuation of the power supply voltage, and then the reading result is turned over in the sensitive amplifier, the invention particularly provides the power supply bias circuit for supplying power to the power supply end of the first inverter, and the power supply bias circuit consists of a charge pump and a source follower, so that a stable power supply can be provided for the power supply end of the first inverter, the adverse influence of the fluctuation of the power supply voltage on the output end of the first inverter is prevented, and the problem that the reading result is turned over due to the fluctuation of the power supply voltage is prevented, so that the influence of power supply noise on the reading result is reduced.
In addition, in the flash memory, the charge pump is originally arranged for providing high voltage higher than power supply voltage, so the charge pump in the power supply bias circuit does not need to be additionally arranged, and the charge pump can be realized by utilizing the charge pump existing in the flash memory, so the sharing of the charge pump can be realized, and the additional cost is not required to be increased.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a circuit diagram of a prior art sense amplifier circuit;
fig. 2 is a circuit diagram of a sense amplifier circuit in accordance with an embodiment of the present invention.
Detailed Description
As shown in fig. 2, a circuit diagram of a sense amplifier circuit according to an embodiment of the present invention; the sensitive amplifier circuit of the embodiment of the invention comprises: and a bit line adjusting unit 201 connected between the bit line node a and the data line node C.
The bit line adjustment unit 201 includes a first NMOS transistor MN201.
The drain electrode of the first NMOS transistor MN201 is connected to the data line node C, and the source electrode of the first NMOS transistor MN201 is connected to the bit line node a.
A feedback circuit is arranged between the gate of the first NMOS transistor MN201 and the bit line node a, the feedback circuit includes a first inverter 203, an input end of the first inverter 203 is connected to the bit line node a, an output end of the first inverter 203 is connected to the gate of the first NMOS transistor MN201, and the gate of the first NMOS transistor MN201 is a feedback node B.
In the embodiment of the present invention, the first inverter 203 is a CMOS inverter, and includes a third NMOS transistor MN202 and a first PMOS transistor MP201.
The gate of the third NMOS transistor MN202 and the gate of the first PMOS transistor MP201 are both connected to the bit line node a.
The source of the third NMOS transistor MN202 is grounded.
The drain electrode of the third NMOS transistor MN202 and the drain electrode of the first PMOS transistor MP201 are both connected to the feedback node B.
The source of the first PMOS MP201 is used as the power supply terminal of the first inverter 203.
The power bias circuit 301 includes a charge pump 302 and a source follower, the charge pump 302 provides a first voltage V1 to an input terminal of the source follower, an output terminal of the source follower outputs a second voltage V2 to a power terminal of the first inverter 203, and the second voltage V2 follows a change of the first voltage V1 to eliminate a voltage fluctuation of the power terminal of the first inverter 203.
The power supply terminal of the source follower is connected with a power supply voltage Vdd.
In the embodiment of the present invention, the source follower includes a second NMOS transistor MN301.
The gate of the second NMOS transistor MN301 is used as the input end of the source follower, the source of the second NMOS transistor MN301 is used as the output end of the source follower, and the drain of the second NMOS transistor MN301 is used as the power end of the source follower.
The bit line node a is connected to the selected memory cell 204 during reading.
A first current source Iref is connected between the data line node C and a power supply voltage Vdd, the current of which is used as a reference current for comparison with the cell current of the memory cell 204; in reading, a first output voltage is formed at the data line node C by comparing the current of the first current source Iref with the cell current.
The sense amplifier circuit further includes an output unit; the first output voltage is input to an input terminal of the output unit and outputs a second output voltage Soutb at an output terminal of the output unit.
In some embodiments, the output unit includes a comparator 202.
The first output voltage is connected to a first input of the comparator 202.
A second input of the comparator 202 is connected to a reference voltage Vref.
The output terminal of the comparator 202 outputs the second output voltage Soutb.
The memory unit 204 is a nonvolatile memory unit 204.
A plurality of the memory cells 204 form a memory array.
A decoding circuit 205 is further connected between the source of the first NMOS transistor MN201 and the bit line node a; in the reading process, the corresponding memory cell 204 is selected by the decoding circuit 205.
The gate structure of the nonvolatile memory cell 204 includes a floating gate; the storage states of the nonvolatile memory cell 204 include an erased state and a programmed state.
The non-volatile memory cell 204 has a first threshold voltage in a programmed state, the cell current being a first cell current.
The non-volatile memory cell 204 has a second threshold voltage in the erased state, the cell current being a second cell current.
The first threshold voltage is greater than the second threshold voltage, and the first cell current is less than the second cell current.
The greater the cell current, the lower the voltage of the bit line node a.
The non-volatile memory cell 204 is an N-type device, and includes an n+ doped source region and a drain region, where electrons are stored in the floating gate in the programming state; in the erased state, electrons stored in the floating gate are removed.
The memory array is formed as part of a flash memory.
The flash memory has a circuit 303 therein that requires a common charge pump as shown in fig. 2 that employs a third voltage that is greater than the supply voltage Vdd. In some embodiments, the third voltage is equal to the first voltage V1. In other embodiments, it can also be: the third voltage is not equal to the first voltage V1.
The third voltage is also provided by the charge pump 302, enabling the charge pump 302 to share.
In some embodiments, a first resistor R301 is connected between the output of the first voltage V1 of the charge pump 302 and the input of the source follower.
Aiming at the problem that when the power supply end of the first inverter 203 of the feedback circuit is connected with the power supply voltage Vdd, the voltage of the feedback node B is easy to overturn due to the fluctuation of the power supply voltage Vdd, and then the reading result is overturned, the embodiment of the invention particularly provides the power supply bias circuit 301 for supplying power to the power supply end of the first inverter 203, and the power supply bias circuit 301 is composed of the charge pump 302 and the source follower, so that a stable power supply can be provided for the power supply end of the first inverter 203, the adverse influence of the fluctuation of the power supply voltage Vdd on the output end of the first inverter 203 is prevented, and the problem of the overturn of the reading result caused by the fluctuation of the power supply voltage Vdd is prevented, so that the influence of power supply noise on the reading result is reduced.
In addition, in the flash memory, the charge pump 302 is originally provided for providing a high voltage higher than the power supply voltage Vdd, so that the charge pump 302 in the power supply bias circuit 301 according to the embodiment of the present invention is not required to be additionally provided, and the charge pump 302 existing in the flash memory is utilized, so that the embodiment of the present invention can realize sharing of the charge pump 302, and additional cost is not required to be increased.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (15)

1. A sense amplifier circuit, comprising: a bit line adjustment unit connected between the bit line node and the data line node;
the bit line adjusting unit comprises a first NMOS tube;
the drain electrode of the first NMOS tube is connected with the data line node, and the source electrode of the first NMOS tube is connected with the bit line node;
a feedback circuit is arranged between the grid electrode of the first NMOS tube and the bit line node, the feedback circuit comprises a first inverter, the input end of the first inverter is connected with the bit line node, the output end of the first inverter is connected to the grid electrode of the first NMOS tube, and the grid electrode of the first NMOS tube is a feedback node;
the power supply bias circuit comprises a charge pump and a source follower, wherein the charge pump provides a first voltage to an input end of the source follower, an output end of the source follower outputs a second voltage to a power end of the first inverter, and the second voltage follows the change of the first voltage so as to eliminate voltage fluctuation of the power end of the first inverter.
2. The sense amplifier circuit of claim 1 wherein: and the power supply end of the source follower is connected with a power supply voltage.
3. The sense amplifier circuit of claim 2 wherein: the source follower comprises a second NMOS tube;
the grid electrode of the second NMOS tube is used as the input end of the source electrode follower, the source electrode of the second NMOS tube is used as the output end of the source electrode follower, and the drain electrode of the second NMOS tube is used as the power supply end of the source electrode follower.
4. The sense amplifier circuit of claim 1 wherein: the bit line node is connected to a selected memory cell during a read.
5. The sense amplifier circuit of claim 4 wherein: the first inverter is a CMOS inverter and comprises a third NMOS tube and a first PMOS tube;
the grid electrode of the third NMOS tube and the grid electrode of the first PMOS tube are connected with the bit line node;
the source electrode of the third NMOS tube is grounded;
the drain electrode of the third NMOS tube and the drain electrode of the first PMOS tube are both connected with the feedback node;
and the source electrode of the first PMOS tube is used as a power supply end of the first inverter.
6. The sense amplifier circuit of claim 4 wherein: a first current source is connected between the data line node and a power supply voltage, and the current of the first current source is used as a reference current for comparison with the cell current of the memory cell; in reading, a first output voltage is formed at the data line node by comparing the current of the first current source with the cell current.
7. The sense amplifier circuit of claim 6 wherein: the sense amplifier circuit further includes an output unit; the first output voltage is input to an input terminal of the output unit and outputs a second output voltage at an output terminal of the output unit.
8. The sense amplifier circuit of claim 7 wherein: the output unit includes a comparator;
the first output voltage is connected to a first input of the comparator;
the second input end of the comparator is connected with a reference voltage;
the output end of the comparator outputs the second output voltage.
9. The sense amplifier circuit of claim 6 wherein: the memory cell is a non-volatile memory cell.
10. The sense amplifier circuit of claim 9 wherein: a plurality of storage units form a storage array;
a decoding circuit is also connected between the source electrode of the first NMOS tube and the bit line node; and during reading, selecting the corresponding storage unit through the decoding circuit.
11. The sense amplifier circuit of claim 9 wherein: the grid structure of the nonvolatile memory unit comprises a floating gate; the storage state of the nonvolatile memory unit comprises an erasing state and a programming state;
the non-volatile memory cell has a first threshold voltage in a programmed state, the cell current being a first cell current;
the non-volatile memory cell has a second threshold voltage in an erased state, the cell current being a second cell current;
the first threshold voltage is greater than the second threshold voltage, and the first cell current is less than the second cell current;
the greater the cell current, the lower the voltage of the bit line node.
12. The sense amplifier circuit of claim 11 wherein: the non-volatile memory unit is an N-type device and comprises an N+ doped source region and a drain region, and electrons are stored in the floating gate in the programming state; in the erased state, electrons stored in the floating gate are removed.
13. The sense amplifier circuit of claim 10 wherein: the memory array is used as a constituent part of the flash memory;
the flash memory is provided with a circuit needing to adopt a third voltage, and the third voltage is larger than the power supply voltage;
the third voltage is also provided by the charge pump, enabling the charge pump sharing.
14. The sense amplifier circuit of claim 13 wherein: a first resistor is connected between the output end of the first voltage of the charge pump and the input end of the source follower.
15. The sense amplifier circuit of claim 14 wherein: the third voltage is equal to the first voltage.
CN202311387397.XA 2023-10-25 2023-10-25 Sense amplifier circuit Pending CN117275535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311387397.XA CN117275535A (en) 2023-10-25 2023-10-25 Sense amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311387397.XA CN117275535A (en) 2023-10-25 2023-10-25 Sense amplifier circuit

Publications (1)

Publication Number Publication Date
CN117275535A true CN117275535A (en) 2023-12-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311387397.XA Pending CN117275535A (en) 2023-10-25 2023-10-25 Sense amplifier circuit

Country Status (1)

Country Link
CN (1) CN117275535A (en)

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