CN117291923A - Chip packaging quality evaluation method and system - Google Patents
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Abstract
The application discloses a chip packaging quality evaluation method and system, comprising the following steps: acquiring a first quality coefficient of a target chip; the target chip is a chip subjected to vibration test; acquiring a second quality coefficient of the target chip corresponding to the welding spot position; constructing a quality evaluation function according to the first quality coefficient and the second quality coefficient; according to the quality evaluation function, the packaging quality information of the target chip is obtained, and the packaging quality evaluation method and device have the advantages of improving accuracy and comprehensiveness of packaging quality evaluation.
Description
Technical Field
The present disclosure relates to the field of semiconductor quality inspection, and in particular, to a method and a system for evaluating chip package quality.
Background
The chip package refers to a semiconductor integrated circuit chip mounting shell, and the chip is laid out, adhered and connected on a frame by a series of technologies, and a wiring terminal is led out and fixed through plastic insulating medium in a potting way, so that an integral three-dimensional structure is formed.
The chip is required to be detected and evaluated for packaging quality after packaging, so that the normal work of the chip in the following transportation, installation and use processes can be ensured, and meanwhile, the reliability and stability of the semiconductor device can be improved. The existing chip packaging quality evaluation method mainly depends on manual visual detection, lacks of standardization, has the problem of large manual error, and is not accurate and comprehensive in evaluation of the chip packaging quality.
Disclosure of Invention
The main purpose of the application is to provide a chip packaging quality evaluation method and system, which aims to solve the technical problem of lower accuracy of the existing chip packaging quality evaluation method.
In order to achieve the above object, the present application provides a method for evaluating the quality of chip package, including the steps of:
acquiring a first quality coefficient of a target chip; the target chip is a chip subjected to vibration test;
acquiring a second quality coefficient of the target chip corresponding to the welding spot position;
constructing a quality evaluation function according to the first quality coefficient and the second quality coefficient;
and acquiring the packaging quality information of the target chip according to the quality evaluation function.
Optionally, acquiring the first quality coefficient of the target chip includes:
obtaining the release coefficient rho of the target chip 1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the release coefficient ρ 1 =1 or 0, when ρ 1 When=1, it indicates that the target chip has no obvious loosening condition, when ρ 1 When the number is=0, the target chip is obviously loosened;
obtaining the warping degree WD of the target chip;
according to the release systemNumber ρ 1 And the warp WD is used for obtaining a first quality coefficient of the target chip; wherein the first mass coefficient is ρ 1 ·WD。
Optionally according to the release coefficient ρ 1 And after the step of obtaining the first quality coefficient of the target chip, the warp WD further includes:
detecting whether the first quality coefficient meets a first qualification condition; wherein, the first qualification condition is: 0 < ρ 1 ·WD≤E 1 ，E 1 The warpage is a qualified value of the chip after vibration test;
and if the first quality coefficient is detected to not meet the first qualification condition, identifying the packaging quality of the target chip as disqualification.
Optionally, obtaining the warp WD of the target chip includes:
acquiring a first image of the target chip based on a first viewing angle; the first visual angle is a visual angle perpendicular to the thickness direction of the target chip;
extracting a first contour feature of a corresponding target chip in the first image;
according to the first contour feature, obtaining a single-corner tilting height h of the target chip;
acquiring a second image of the target chip based on a second viewing angle; wherein the second viewing angle is a viewing angle perpendicular to the first viewing angle;
extracting a second contour feature of a corresponding target chip in the second image;
obtaining the diagonal line length c of the target chip according to the second contour characteristic;
obtaining the warping degree WD of the target chip according to the single-angle warping height h and the diagonal line length c; wherein, the expression of the warp WD is:
WD=h/2c。
optionally, obtaining a second quality coefficient of the target chip corresponding to the solder joint position includes:
obtaining crack coefficient rho of corresponding welding spot in target chip 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the crack coefficient ρ 2 =1 or 0, when ρ 2 When=1, it indicates that the target chip has no obvious crack defect, when ρ 2 When=0, it indicates that the target chip has obvious crack defect;
obtaining an offset coefficient e of a corresponding welding spot in a target chip; the offset coefficient e is the number of offset welding spots;
according to the crack coefficient ρ 2 And the offset coefficient e is used for obtaining a second quality coefficient of the target chip; wherein the second mass coefficient is ρ 2 ·e。
Optionally according to the crack coefficient ρ 2 And the offset coefficient e, after the step of obtaining the second quality coefficient of the target chip, further includes:
detecting whether the second quality coefficient meets a second qualification condition; wherein, the second qualification condition is: 0 < ρ 2 ·e≤E 2 ，E 2 The allowable number of offset pads in the target chip;
and if the second quality coefficient is detected to not meet the second qualification condition, identifying the packaging quality of the target chip as disqualification.
Optionally, obtaining the offset coefficient e of the corresponding solder joint in the target chip includes:
acquiring a third image of the target chip based on a third viewing angle; the third view angle is a view angle facing one surface of the target chip, which is provided with a plurality of welding spots;
extracting outline features of a plurality of corresponding welding spots in a third image;
extracting the center points of the outline features of the welding spots;
constructing a reference grid; the reference grid is formed by connecting center points of a plurality of welding spots which are not subjected to position deviation in the vertical direction and the horizontal direction at the same time;
identifying a number of center points that deviate from the intersection points of the reference grid;
the number of identified center points is taken as the offset coefficient e.
Optionally, the expression of the quality evaluation function is:
Q=ε 1 ·ρ 1 ·WD+ε 2 ·ρ 2 ·e
wherein Q is a quality evaluation coefficient ε 1 For the first conversion factor epsilon 2 Is the first conversion coefficient, and epsilon 1 And epsilon 2 Are all constant.
Optionally, obtaining package quality information of the target chip according to the quality evaluation function includes:
acquiring a quality evaluation coefficient Q according to the quality evaluation function;
detecting whether the quality evaluation coefficient Q meets a third qualification condition; wherein, the third qualification condition is: q is more than 0 and less than or equal to Q ', Q' is a qualified threshold of the chip packaging quality;
and if the detection quality evaluation coefficient Q meets the third qualification condition, identifying the packaging quality of the target chip as qualified.
In order to achieve the above object, the present application further provides a chip package quality evaluation system, including:
the first acquisition module is used for acquiring a first quality coefficient of the target chip; the target chip is a chip subjected to vibration test;
the second acquisition module is used for acquiring a second quality coefficient of the welding spot position corresponding to the target chip;
the function construction module is used for constructing a quality evaluation function according to the first quality coefficient and the second quality coefficient;
and the third acquisition module is used for acquiring the packaging quality information of the target chip according to the quality evaluation function.
To achieve the above object, the present application further provides a computer device, which includes a memory and a processor, where the memory stores a computer program, and the processor executes the computer program to implement the above method.
To achieve the above object, the present application further provides a computer readable storage medium, on which a computer program is stored, and a processor executes the computer program to implement the above method.
The beneficial effects that this application can realize are as follows:
according to the method, the first quality coefficient of the target chip after the vibration test is obtained, and the second quality coefficient of the target chip corresponding to the welding spot position is combined, wherein the vibration test can comprehensively evaluate the reliability and stability of the chip, the welding spot defect can influence the packaging reliability and even lead the electronic product to fail, so that the quality evaluation function is constructed by combining the two relatively targeted reference points, the function can effectively guide the packaging quality evaluation of the chip, and the method has guidance and reference properties, and improves the accuracy of the packaging quality evaluation of the chip.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
Fig. 1 is a flow chart of a method for evaluating chip package quality in an embodiment of the present application;
FIG. 2 is a schematic illustration of a first image acquired in an embodiment of the present application;
FIG. 3 is a schematic illustration of a second image acquired in an embodiment of the present application;
fig. 4 is a schematic diagram of a third image acquired in an embodiment of the present application.
The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are merely used to explain the relative positional relationship between the components, the movement condition, and the like in a specific posture, and if the specific posture is changed, the directional indicator is correspondingly changed.
In the present application, unless explicitly specified and limited otherwise, the terms "coupled," "secured," and the like are to be construed broadly, and for example, "secured" may be either permanently attached or removably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" as it appears throughout includes three parallel schemes, for example "A and/or B", including the A scheme, or the B scheme, or the scheme where A and B are satisfied simultaneously. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.
Example 1
Referring to fig. 1-4, the present embodiment provides a chip package quality evaluation method, which includes the following steps:
acquiring a first quality coefficient of a target chip; the target chip is a chip subjected to vibration test;
acquiring a second quality coefficient of the target chip corresponding to the welding spot position;
constructing a quality evaluation function according to the first quality coefficient and the second quality coefficient;
and acquiring the packaging quality information of the target chip according to the quality evaluation function.
In this embodiment, by acquiring the first quality coefficient of the target chip after the vibration test and combining the second quality coefficient of the target chip corresponding to the solder joint position, the vibration test can comprehensively evaluate the reliability and stability of the chip, and the solder joint defect can affect the packaging reliability and even make the electronic product fail, so that the quality evaluation function is constructed by combining the two relatively targeted reference points, and the function can effectively guide the packaging quality evaluation of the chip, has better guidance and reference, and improves the accuracy of the packaging quality evaluation of the chip.
It should be noted that, the target chip mainly refers to a packaged chip to be detected; the formation of the welding spot defect is mainly formed in the packaging process, and the vibration test has little influence on the welding spot defect, so that the calculation of the first quality coefficient and the second quality coefficient can be carried out in no sequence, when the second quality coefficient is obtained by calculation, the second quality coefficient of the target chip aiming at the welding spot position can be calculated first, then the first quality coefficient can be calculated after the vibration test is carried out on the target chip, and the calculation of the second quality coefficient of the welding spot position can be carried out on the chip after the vibration test is carried out after the first quality coefficient is obtained by calculation; the vibration test includes a vibration test using at least one of random vibration, acceleration test, sinusoidal vibration, classical impact pulse test, impact response spectrum test, and road transportation test, preferably having stress; in performing the vibration test, various vibration test parameters such as vibration frequency, vibration amplitude, vibration time, etc. need to be considered, and the selection of these parameters should be determined according to the characteristics and the use environment of the semiconductor device; the equipment used for vibration test comprises a vibration table, a vibration testing machine, a vibration sensor and the like; vibration test standards are also referred to in vibration test, and refer to a series of specifications and standards which are followed when a semiconductor device is subjected to vibration test, and the standards are generally established by international organization for standardization (ISO), electronic industry standardization (IEC) and other organizations to ensure the accuracy and reliability of test results, and the first quality coefficient can be generated according to the test results.
As an alternative embodiment, obtaining the first quality coefficient of the target chip includes:
obtaining the release coefficient rho of the target chip 1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the release coefficient ρ 1 =1 or 0, when ρ 1 When=1, it indicates that the target chip has no obvious loosening condition, when ρ 1 When the number is=0, the target chip is obviously loosened;
obtaining the warping degree WD of the target chip;
according to the release coefficient ρ 1 And the warp WD is used for obtaining a first quality coefficient of the target chip; wherein the first mass coefficient is ρ 1 ·WD。
In the embodiment, after the chip is subjected to vibration test, the most obvious defects are that the parts are loosened and warped, the chip warpage can cause the coplanarity and the position degree change of the chip, so that the coplanarity and the position degree of the FC chip welding inside the chip and the chip leading-out end are out of question, the chip of the ceramic substrate generally requires the flatness of the flip-chip bonding pad to be less than or equal to 30 mu m, and the position degree to be less than or equal to 80 mu m, so that the warpage of the chip needs to be detected, the defects of the two are comprehensively considered, and the loosening coefficient rho is set for the loosening condition of the parts 1 Meanwhile, warp WD is set for the warp defect, and the product ρ of the warp WD and the warp defect is obtained 1 WD is used as a first quality coefficient, when the components in the chip are obviously loosened, ρ is given 1 When the first quality coefficient is 0 and the parts in the chip have no obvious loosening condition, rho is given 1 The first quality coefficient is the actual value of the warp WD, and the first quality coefficient with strong pertinence and guidance can be obtained, and the first quality coefficient can represent the quality qualification degree of the chip after the vibration test, so that the embodiment realizes the comprehensive quantization treatment of the loosening and the warp defect of the component, and is more scientific and standard.
If the release coefficient ρ of the target chip is obtained 1 When the chip is in the range of 0, namely when the chip is obviously loosened, the defect is a serious defect, and at the moment, the chip can be directly verified to be a defective product, so that the calculation of the warping degree WD of the next step is not needed, the detection process is reduced, and the working efficiency is improved; the judgment of the loosening condition of the chip parts is visual, so the judgment of the loosening condition can be judged by means of manual visual observationThe accuracy is higher by judging by using a machine vision technology; similarly, the calculation of the warp WD may also be implemented by machine vision techniques.
As an alternative embodiment, the release coefficient ρ is based on 1 And after the step of obtaining the first quality coefficient of the target chip, the warp WD further includes:
detecting whether the first quality coefficient meets a first qualification condition; wherein, the first qualification condition is: 0 < ρ 1 ·WD≤E 1 ，E 1 The warpage is a qualified value of the chip after vibration test;
and if the first quality coefficient is detected to not meet the first qualification condition, identifying the packaging quality of the target chip as disqualification.
In this embodiment, after the first quality coefficient is obtained by calculation, it is further verified whether the first quality coefficient satisfies the first qualification condition, if the first quality coefficient ρ 1 Wd=0, then the release coefficient ρ is demonstrated 1 =0, so that the first mass coefficient should be greater than 0, and after no significant loosening, the first mass coefficient is the warp WD, which should be lower than the predetermined warp fit value E 1 Here the warp fit value E 1 Setting according to specific chip characteristics, if the first quality coefficient is detected to not meet the first qualification condition, directly identifying the packaging quality of the target chip as unqualified, and not needing to carry out the next step, reducing the detection procedure, reducing the data processing pressure, at the moment, reworking the chip (if reworking cannot be carried out, the chip is directly scrapped), and entering the next step until the first qualification condition is met.
As an alternative embodiment, obtaining the warp WD of the target chip includes:
acquiring a first image of the target chip based on a first viewing angle; the first visual angle is a visual angle perpendicular to the thickness direction of the target chip;
extracting a first contour feature of a corresponding target chip in the first image;
according to the first contour feature, obtaining a single-corner tilting height h of the target chip;
acquiring a second image of the target chip based on a second viewing angle; wherein the second viewing angle is a viewing angle perpendicular to the first viewing angle;
extracting a second contour feature of a corresponding target chip in the second image;
obtaining the diagonal line length c of the target chip according to the second contour characteristic;
obtaining the warping degree WD of the target chip according to the single-angle warping height h and the diagonal line length c; wherein, the expression of the warp WD is:
WD=h/2c。
in this embodiment, when calculating the warp WD, a first image and a second image of the chip may be obtained by a CCD camera, and then the contour features corresponding to the chip may be extracted, and a single angle warp height h and a diagonal length c may be calculated by using a mathematical geometry relationship, where when calculating the diagonal length c, the chip length and width are set to be a and b, respectively, and then c may be obtained by using the pythagorean theorem 2 =a 2 +b 2 And c can be obtained, and finally, the value of the warping degree WD can be obtained by calculating according to the warping degree WD calculation formula.
The first image and the second image are black-white images, and the corresponding original images are collected, and after a series of image processing (including gray processing, binarization processing and the like), black-white clear images can be obtained, so that the identification and extraction of contour features are facilitated.
As an alternative embodiment, obtaining the second quality coefficient of the target chip corresponding to the solder joint position includes:
obtaining crack coefficient rho of corresponding welding spot in target chip 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the crack coefficient ρ 2 =1 or 0, when ρ 2 When=1, it indicates that the target chip has no obvious crack defect, when ρ 2 When=0, it indicates that the target chip has obvious crack defect;
obtaining an offset coefficient e of a corresponding welding spot in a target chip; the offset coefficient e is the number of offset welding spots;
according to the cracksCoefficient ρ 2 And the offset coefficient e is used for obtaining a second quality coefficient of the target chip; wherein the second mass coefficient is ρ 2 ·e。
In this embodiment, in the chip package structure, the solder joint defect is also one of the key factors affecting the chip package quality, and the solder joint crack defect and the solder joint offset are the most representative defect types among the solder joint defects, so this embodiment quantifies the solder joint crack defect and the solder joint offset, and uses the crack coefficient and the offset coefficient as index data, respectively, wherein the solder joint crack is a substantial defect, if there is an obvious crack defect, the chip is directly determined to be a defective product, and here the product ρ of the crack coefficient and the offset coefficient is taken as the product ρ 2 E as a second quality coefficient, giving ρ when there is a significant crack defect 2 =0, the second mass coefficient is 0, when no obvious crack defect exists, ρ is given 2 The second quality coefficient is calculated to obtain the second quality coefficient, which can represent the quality qualification degree of the chip welding spot.
When the defects of the welding spots are tested, the welding spots can be tested in a reflow soldering and temperature circulation mode, and then the cracks and the offset conditions of the welding spots are detected after the testing; when the number of offset welding spots is calculated, the welding spot offset is not a major defect, according to the process specification, the welding spots exceeding the preset offset can be used as offset welding spots, and welding spots within the preset offset range can be used as qualified welding spots, namely, certain offset is allowed.
As an alternative embodiment, according to the crack coefficient ρ 2 And the offset coefficient e, after the step of obtaining the second quality coefficient of the target chip, further includes:
detecting whether the second quality coefficient meets a second qualification condition; wherein, the second qualification condition is: 0 < ρ 2 ·e≤E 2 ，E 2 The allowable number of offset pads in the target chip;
and if the second quality coefficient is detected to not meet the second qualification condition, identifying the packaging quality of the target chip as disqualification.
In this embodiment, after the second quality coefficient is obtained by calculation, it is also necessary to verify whether the second quality coefficient satisfies the second qualification condition, if ρ 2 E=0, then it proves that there are significant crack defects, so the second mass coefficient must be greater than 0, only at ρ 2 In the case of =1, the second mass coefficient is greater than 0, and the calculated offset coefficient E is the second mass coefficient, so that an allowable quantity value E of an offset welding point is set 2 Only if the second quality coefficient is equal to or lower than the value, the qualification standard is reached, if the second qualification condition is not met, the packaging quality of the target chip can be directly identified as unqualified, reworking treatment (if reworking cannot be performed, the target chip is directly scrapped) is needed until the second qualification condition is met.
As an alternative embodiment, obtaining the offset coefficient e of the corresponding solder joint in the target chip includes:
acquiring a third image of the target chip based on a third viewing angle; the third view angle is a view angle facing one surface of the target chip, which is provided with a plurality of welding spots;
extracting outline features of a plurality of corresponding welding spots in a third image;
extracting the center points of the outline features of the welding spots;
constructing a reference grid; the reference grid is formed by connecting center points of a plurality of welding spots which are not subjected to position deviation in the vertical direction and the horizontal direction at the same time;
identifying a number of center points that deviate from the intersection points of the reference grid;
the number of identified center points is taken as the offset coefficient e.
In this embodiment, when calculating the offset coefficient e of the welding spot, the machine vision recognition technology is also used to obtain a third image of the target chip, where the third image includes contour features of a plurality of welding spots, and because the welding spots are generally arranged vertically and horizontally, a reference grid can be constructed by connecting the center points of the welding spots that do not have position offset in the vertical direction and the horizontal direction at the same time, and the reference grid can be used as a reference standard, and the offset coefficient e can be quickly and accurately calculated by extracting the center points of the contour features of the welding spots and then identifying the number of center points that are not on the intersecting points on the reference grid.
It should be noted that, an offset may be preset, and a center point that deviates from the intersection point of the reference grid and exceeds the offset may be used as the identification object, and may be used as the qualified welding spot within the offset range, where the offset may be specifically set according to the process requirement; similarly, the third image should also be a black-and-white image obtained after image processing, so as to facilitate feature recognition and extraction.
As an alternative embodiment, the expression of the quality evaluation function is:
Q=ε 1 ·ρ 1 ·WD+ε 2 ·ρ 2 ·e
wherein Q is a quality evaluation coefficient ε 1 For the first conversion factor epsilon 2 Is the first conversion coefficient, and epsilon 1 And epsilon 2 Are all constant.
In the present embodiment, the quality evaluation function includes two quality indexes of different dimensions of the first quality coefficient and the second quality coefficient, but since the first quality coefficient and the second quality coefficient belong to different unit quality indexes, one conversion coefficient ε is respectively assigned 1 And epsilon 2 (conversion coefficient ε) 1 And epsilon 2 According to the specific setting of the technological condition), the first quality coefficient and the second quality coefficient are subjected to the same-magnitude superposition, so that a final quality evaluation function is obtained, the evaluation of the chip packaging quality can be effectively guided according to the quality evaluation function, and a scientific, effective and relatively representative evaluation system is formed.
As an alternative embodiment, obtaining package quality information of the target chip according to the quality evaluation function includes:
acquiring a quality evaluation coefficient Q according to the quality evaluation function;
detecting whether the quality evaluation coefficient Q meets a third qualification condition; wherein, the third qualification condition is: q is more than 0 and less than or equal to Q ', Q' is a qualified threshold of the chip packaging quality;
and if the detection quality evaluation coefficient Q meets the third qualification condition, identifying the packaging quality of the target chip as qualified.
In this embodiment, after the quality evaluation coefficient Q is obtained by calculation according to the quality evaluation function, a qualification threshold Q '(set according to the process requirement) of the packaging quality is further set, when both the warpage of the chip and the solder joint offset have defects to a certain extent, and both the first quality coefficient and the second quality coefficient meet the qualification condition, the defects of both the first quality coefficient and the second quality coefficient may have a great influence on the subsequent quality of the chip by superposition, so that after the two different types of defects are quantitatively superposed to obtain the quality evaluation coefficient Q, the quality evaluation coefficient Q is considered, and when the Q is more than 0 and less than or equal to Q', the packaging quality of the chip is verified to really meet qualification combination, thereby further improving the accuracy of the evaluation of the packaging quality of the chip.
Example 2
Based on the same inventive concept as the foregoing embodiment, this embodiment further provides a chip package quality evaluation system, including:
the first acquisition module is used for acquiring a first quality coefficient of the target chip; the target chip is a chip subjected to vibration test;
the second acquisition module is used for acquiring a second quality coefficient of the welding spot position corresponding to the target chip;
the function construction module is used for constructing a quality evaluation function according to the first quality coefficient and the second quality coefficient;
and the third acquisition module is used for acquiring the packaging quality information of the target chip according to the quality evaluation function.
The explanation and examples of each module in the apparatus of this embodiment may refer to the method of the foregoing embodiment, and will not be repeated here.
Example 3
Based on the same inventive concept as the previous embodiments, this embodiment provides a computer device, which includes a memory and a processor, where the memory stores a computer program, and the processor executes the computer program to implement the above method.
Example 4
Based on the same inventive concept as the previous embodiments, this embodiment provides a computer readable storage medium, on which a computer program is stored, and a processor executes the computer program to implement the above method.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.
Claims (10)
1. The chip packaging quality evaluation method is characterized by comprising the following steps of:
acquiring a first quality coefficient of a target chip; the target chip is a chip subjected to vibration test;
acquiring a second quality coefficient of the target chip corresponding to the welding spot position;
constructing a quality evaluation function according to the first quality coefficient and the second quality coefficient;
and acquiring the packaging quality information of the target chip according to the quality evaluation function.
2. The method for evaluating the package quality of a chip according to claim 1, wherein said obtaining the first quality coefficient of the target chip comprises:
obtaining the release coefficient rho of the target chip 1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the release coefficient ρ 1 =1 or 0, when ρ 1 When=1, the target chip has no obvious loosening condition, when ρ 1 When the target chip is=0, the target chip has obvious loosening condition;
obtaining the warping degree WD of the target chip;
according to the release coefficient ρ 1 The warp WD acquires a first quality coefficient of the target chip; wherein the first quality coefficient is ρ 1 ·WD。
3. The chip package quality evaluation method according to claim 2Characterized in that said method is based on said release coefficient ρ 1 And after the step of obtaining the first quality coefficient of the target chip, the warp WD further includes:
detecting whether the first quality coefficient meets a first qualification condition; wherein, the first qualification condition is: 0 < ρ 1 ·WD≤E 1 ，E 1 The warpage is a qualified value of the chip after vibration test;
and if the first quality coefficient is detected to not meet the first qualification condition, identifying that the packaging quality of the target chip is unqualified.
4. The method for evaluating the package quality of a chip according to claim 2, wherein said obtaining the warp WD of the target chip comprises:
acquiring a first image of the target chip based on a first viewing angle; the first visual angle is a visual angle perpendicular to the thickness direction of the target chip;
extracting a first contour feature corresponding to the target chip in the first image;
acquiring a single-angle tilting height h of the target chip according to the first contour characteristic;
acquiring a second image of the target chip based on a second viewing angle; wherein the second viewing angle is a viewing angle perpendicular to the first viewing angle;
extracting a second contour feature corresponding to the target chip in the second image;
obtaining the diagonal line length c of the target chip according to the second contour features;
obtaining the warping degree WD of the target chip according to the single angle raising height h and the diagonal line length c; wherein, the expression of the warp WD is:
WD=h/2c。
5. the method for evaluating the packaging quality of a chip according to any one of claims 2 to 4, wherein the obtaining the second quality coefficient of the target chip corresponding to the solder joint position includes:
obtaining crack coefficient rho of corresponding welding spots in the target chip 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the crack coefficient ρ 2 =1 or 0, when ρ 2 When=1, it indicates that the target chip has no obvious crack defect, when ρ 2 When=0, it indicates that the target chip has a significant crack defect;
obtaining an offset coefficient e of a corresponding welding spot in the target chip; the offset coefficient e is the number of offset welding spots;
according to the crack coefficient ρ 2 The offset coefficient e is used for obtaining a second quality coefficient of the target chip; wherein the second mass coefficient is ρ 2 ·e。
6. The method for evaluating the quality of a chip package according to claim 5, wherein said step of determining said crack coefficient ρ 2 And the offset coefficient e, after the step of obtaining the second quality coefficient of the target chip, further includes:
detecting whether the second quality coefficient meets a second qualification condition; wherein, the second qualification condition is: 0 < ρ 2 ·e≤E 2 ，E 2 The allowable number of offset welding spots in the target chip is set;
and if the second quality coefficient is detected to not meet the second qualification condition, identifying that the packaging quality of the target chip is unqualified.
7. The method for evaluating the packaging quality of a chip as claimed in claim 5, wherein said obtaining the offset coefficient e of the corresponding solder joint in the target chip comprises:
acquiring a third image of the target chip based on a third viewing angle; the third view angle is a view angle facing one surface of the target chip, which is provided with a plurality of welding spots;
extracting outline features of a plurality of corresponding welding spots in the third image;
extracting the center points of the outline features of a plurality of welding spots;
constructing a reference grid; the reference grid is formed by connecting center points of a plurality of welding spots which are not subjected to position deviation in the vertical direction and the horizontal direction at the same time;
identifying a number of the center points that deviate from the intersection points of the reference grid;
the number of the identified center points is taken as an offset coefficient e.
8. The method for evaluating the quality of a chip package according to claim 5, wherein the expression of the quality evaluation function is:
Q=ε 1 ·ρ 1 ·WD+ε 2 ·ρ 2 ·e
wherein Q is a quality evaluation coefficient ε 1 For the first conversion factor epsilon 2 Is the first conversion coefficient, and epsilon 1 And epsilon 2 Are all constant.
9. The method for evaluating the package quality of a chip according to claim 8, wherein said obtaining the package quality information of the target chip according to the quality evaluation function comprises:
acquiring a quality evaluation coefficient Q according to the quality evaluation function;
detecting whether the quality evaluation coefficient Q meets a third qualification condition; wherein, the third qualification condition is: q is more than 0 and less than or equal to Q ', Q' is a qualified threshold of the chip packaging quality;
and if the quality evaluation coefficient Q is detected to meet a third qualification condition, recognizing that the packaging quality of the target chip is qualified.
10. A chip package quality evaluation system, comprising:
the first acquisition module is used for acquiring a first quality coefficient of the target chip; the target chip is a chip subjected to vibration test;
the second acquisition module is used for acquiring a second quality coefficient of the welding spot position corresponding to the target chip;
the function construction module is used for constructing a quality evaluation function according to the first quality coefficient and the second quality coefficient;
and the third acquisition module is used for acquiring the packaging quality information of the target chip according to the quality evaluation function.
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