CN117291917A - Intelligent test system and method for low-power-consumption equipment based on artificial intelligence - Google Patents

Intelligent test system and method for low-power-consumption equipment based on artificial intelligence Download PDF

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CN117291917A
CN117291917A CN202311579030.8A CN202311579030A CN117291917A CN 117291917 A CN117291917 A CN 117291917A CN 202311579030 A CN202311579030 A CN 202311579030A CN 117291917 A CN117291917 A CN 117291917A
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test
chip
node
chain
wafer
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CN117291917B (en
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刘伟
付强
汤小敏
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Changzhou Manwang Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D21/00—Measuring or testing not otherwise provided for
    • G01D21/02—Measuring two or more variables by means not covered by a single other subclass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/50—Information retrieval; Database structures therefor; File system structures therefor of still image data
    • G06F16/53—Querying
    • G06F16/538—Presentation of query results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/50—Information retrieval; Database structures therefor; File system structures therefor of still image data
    • G06F16/58—Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually
    • G06F16/583—Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually using metadata automatically derived from the content
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/60—Analysis of geometric attributes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/70—Determining position or orientation of objects or cameras
    • G06T7/73—Determining position or orientation of objects or cameras using feature-based methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10132—Ultrasound image
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Abstract

The invention discloses an intelligent test system and method for low-power-consumption equipment based on artificial intelligence, and belongs to the field of intelligent test of equipment. According to the invention, the test energy influence states of different chips are analyzed to form the test chains, the node selection indexes of the intersecting nodes of the different test chains are analyzed, the test analysis model is constructed, the optimal test sequence is formed, the energy loss is reduced, and the wafer test efficiency is improved.

Description

Intelligent test system and method for low-power-consumption equipment based on artificial intelligence
Technical Field
The invention relates to the field of intelligent testing of equipment, in particular to an intelligent testing system and method for low-power-consumption equipment based on artificial intelligence.
Background
In the manufacturing process of the semiconductor device, the test is an important link for ensuring the delivery quality of the device, and through the test, some defective products or products with unqualified performances generated in the manufacturing process can be selected, or through the test, the performance parameters of the device are obtained, and the products can be classified. The probe test is a very important test item in the silicon chip test, and the probe test uses a probe card to be contacted with a pressure welding point on a wafer so as to transmit an electric signal, the probe card is contacted with a test contact pressure welding point on the wafer through a probe, and a test machine sends the test electric signal to be input to a crystal grain on the wafer through the probe and the pressure welding point contacted with the probe, so that test data are obtained.
However, existing wafer probe tests are often performed by a fixed test route, such as row-by-row or column-by-column testing, and require repeated lifting of the probe to a specified height each time the chip is tested; there is also a method for customizing a test path, and chinese patent publication No. CN116581051a discloses a method and apparatus for testing a wafer, where in the prior art, a wafer test apparatus has a defect that it is difficult to save energy consumption of the test apparatus when a probe tests a wafer, and repeated lifting of the probe causes an increase in energy consumption in the wafer probe test, resulting in energy waste in the wafer probe test, and low energy use efficiency in the wafer probe test. Meanwhile, the custom test path has the condition of repeated test on a certain chip in the wafer, so that the condition of energy waste is caused.
It is therefore necessary to manage the paths of the probe tests, avoid retesting, and minimize the energy loss during wafer probe testing. Therefore, there is a need for an artificial intelligence based low power consumption device intelligent test system and method.
Disclosure of Invention
The invention aims to provide an intelligent test system and method for low-power-consumption equipment based on artificial intelligence, which are used for solving the problems in the background technology.
In order to solve the technical problems, the invention provides the following technical scheme: an intelligent test method for low-power consumption equipment based on artificial intelligence comprises the following steps:
s1, acquiring information of a wafer probe test device and data information of each test wafer corresponding to the wafer probe test device, and numbering each test wafer;
s2, monitoring the surface images of each test wafer in real time through ultrasonic waves, acquiring chip data information of the surface of the test wafer, and analyzing the influence states of the test energy sources of different chips to form a test chain;
s3, analyzing node selection indexes of the intersecting nodes to the test chains by combining the intersecting node information of the different test chains, and constructing a test analysis model to obtain node selection indexes of comprehensive test schemes and corresponding change schemes corresponding to the different test chains so as to form a new test chain;
s4, analyzing the energy loss condition between the starting node and the ending node of any test chain according to the test chain formed in the step S3, forming an optimal test sequence, and displaying through display equipment.
Further, in step S1, the wafer probe test apparatus information includes energy consumption data during a history test of the wafer probe test apparatus,
the number of the a test wafer is recorded as。
Further, in step S2, the following steps are included:
s201, placing the wafer in a plane rectangular coordinate system, wherein the coordinate system is preset by a related technician to obtain each chip in the waferForm a set of position coordinate information of (a)Wherein n is represented as the number of chips, +.>Position coordinate information expressed as an nth chip;
an ultrasonic sensor is arranged on the wafer probe test equipment, an image of the surface of the wafer is obtained, the height value of each chip in the wafer is obtained, and a set is formedWherein->The height value of the nth chip is represented, and a difference value formed by the distance from the ultrasonic sensor to the preset position of the lower layer of the wafer and the distance from the ultrasonic sensor to the test position of the upper layer of the wafer is obtained through the ultrasonic sensor and is used as the height value of the chip;
s202, obtaining the average energy loss of the probe in a unit distance moving in the horizontal plane as follows according to the energy loss data of the wafer probe test equipment during the historical testThe average energy loss per unit distance of the probe moving in the horizontal plane is obtained by dividing the total energy loss monitored when the probe moves in the horizontal direction by the total moving distance in the preset time, and the average energy loss per unit distance of the probe moving vertically downwards is +.>The average loss of the energy source per unit distance of the probe moving vertically downwards is obtained by dividing the total loss of the energy source monitored when the probe moves vertically downwards by the total distance of the downward movement within a preset time, and the average loss of the energy source per unit distance of the probe moving vertically upwards is +.>Unit distance of probe moving vertically upwardThe average energy loss is obtained by dividing the total energy loss monitored when the probe moves vertically upwards by the total upward movement distance in a preset time, and the shortest path distance between any two chips is obtained through a shortest path algorithm, wherein the shortest path algorithm is used for calculating the shortest path from one node to all other nodes, and is mainly characterized in that the shortest path is expanded layer by taking a starting point as a center until the shortest path is expanded to an end point;
s203, for the ith chip and the jth chip, testing the loss value by the following formulaAnd (3) performing calculation:
；
wherein,expressed as shortest path distance between the ith chip and the jth chip, +.>Height value denoted as i-th chip, ">A height value denoted as j-th chip;
the chip with the largest height value in the wafer is used as a first test chip, the test loss index between the chip with the largest height value and other chips is calculated according to the fact that the height of the chip is from large to small, and the corresponding chip with the smallest test loss index is selected as a second test chip;
s204, repeating the step S203, and selecting the test chips until the selected test chips and all chips meet the following relationship:
；
wherein,expressed as a standard height, which is preset by the skilled person,
forming a test chain by taking the selected chip as a node；
S205, repeating the steps S203-S204 according to the height value of the chip from large to small to form a test chain set
Wherein m is expressed as the number of test chains, < >>Denoted as the mth test chain.
Further, in step S3, the following steps are included:
s301, for the r test chain and the S test chain,，/>intersecting nodes form a set->Wherein c is expressed as the number of intersecting nodes, +.>Denoted as c-th intersecting node information;
s302, in the r test chain, for the intersecting nodes，/>The previous node is marked +.>The latter node is marked +.>The pair not passing through the intersection node is +.>Energy loss value->And (3) performing calculation:
；
wherein,denoted as the r test strand passes the crossing node +.>Is summed up from the measured loss values between the nodes analyzed in step S203,/->Represented as the previous node b and the intersecting node +.>Shortest path distance between ∈>Expressed as intersecting node +.>And the latter node->Shortest path distance between ∈>Represented as node b and node->The shortest path distance between them.
Further, in step S3,
s303, repeating the step S302 in the S test chain to obtain a node which does not pass through the intersectionEnergy loss value->The s-th test chain passes through the crossing node +.>The total energy loss value of (2) is +.>；
Constructing a test analysis model, selecting indexes for nodes by the following formulaAnd (3) performing calculation:
；
when (when)When (i.e.)>Indicating that the r test chain passes through the crossing node +.>The s-th test chain does not pass through the crossing node +.>The total energy loss of the test chain is larger than or equal to the sum of the energy loss of the (r) test chain without passing through an intersection node +.>The s-th test chain passes through the crossing node +.>If the total energy loss of the (2) is not detected, judging that the (r) th test chain does not pass through the crossing node +.>The s-th test chain passes through the crossing node +.>The method comprises the steps of carrying out a first treatment on the surface of the On the contrary, when->When (i.e.)>Indicating that the r test chain passes through the intersecting nodeThe s-th test chain does not pass through the crossing node +.>The total energy loss of the test chain is smaller than the energy loss of the (r) test chain without crossing the node +.>The s-th test chain passes through the crossing node +.>If the total energy loss of the (2) is determined that the (r) th test chain passes through the crossing node +.>The s-th test chain does not pass through the crossing node +.>；
S304, repeating the steps S302-S303 on all the intersecting nodes in the set B, and performing calculation analysis on the selection indexes of the intersecting nodes to form a new test chain;
s305, repeating the steps S301-S304 for all the test chains, and judging the intersecting nodes of all the test chains to form a new test chain setWherein->Denoted as mth adjusted test chain.
Further, in step S4, the following steps are included:
s401, combining the analysis result in the step S3, selecting a test chain with the largest chip height value in the wafer as a first test chain, and marking a chip corresponding to the last node of the test chain as u;
after removing the first test strand, the remaining test strands form a setWherein->Denoted as the m-1 th adjusted test chain after removal of the first test chain;
s402, for test chains，/>The chip corresponding to the first node is denoted v and the index +.>And (3) performing calculation:
；
wherein,expressed as the height value of the chip v, +.>Expressed as the height value of the chip u, +.>Represented as a chipv shortest path distance between chip u;
for chip u and setCalculating and comparing the test chain selection indexes among the first nodes of all the test chains, and selecting the corresponding test chain with the smallest test chain selection index as the second test chain;
s403, repeating the steps S401-S402 on the chip corresponding to the first node of the second test chain, and selecting the next test chain;
s404, repeating the steps S401-S403 on all the test chains in the set K until all the test chains form the optimal test sequence, displaying related technicians through display equipment, and maximally reducing energy loss in the probe test process.
An artificial intelligence based low power consumption device intelligent test system, the low power consumption device intelligent test system comprising: the system comprises a test monitoring module, a database, a test analysis module and a terminal feedback module;
the output end of the test monitoring module is connected with the input end of the database, the output end of the database is connected with the input end of the test analysis module, the input end of the terminal feedback module is connected with the output end of the test analysis module, and the input end of the database is connected with the output end of the test analysis module;
the test monitoring module is used for monitoring real-time data of the wafer probe test, the database is used for intelligently managing collected data and analysis results, the test analysis module is used for analyzing energy loss of the wafer probe test and analyzing the optimal test sequence of the probe test, and the terminal feedback module is used for displaying analysis results of the probe test for related technicians through the display equipment.
Further, the test monitoring module comprises an ultrasonic acquisition unit and an energy consumption acquisition unit, wherein the ultrasonic acquisition unit is used for monitoring the surface images of each test wafer in real time through an ultrasonic sensor to acquire chip data information of the surfaces of the test wafers, and the energy consumption acquisition unit is used for acquiring the energy consumption condition of the probe test equipment in real time and acquiring the energy consumption of the probe in mobile use.
Further, the database comprises a data sharing unit and a data management unit, wherein the data sharing unit is used for carrying out data sharing on the test equipment, for unused probe test equipment, historical shared data of other equipment with the same function can be called, the use efficiency of the probe test equipment is improved, the robustness of the system is improved, the data management unit is used for carrying out encryption storage on collected data and analysis results through an encryption module, the encryption module is a module or a component for encrypting the data, the confidentiality and the integrity of the data are generally protected, the safety of the data is guaranteed, and information leakage or tampering is avoided.
Further, the test analysis module comprises a chip selection unit and a node judgment unit, wherein the chip selection unit is used for selecting chips forming a test chain, analyzing test influence states of different chips and analyzing energy loss conditions, and the node judgment unit is used for constructing a test analysis model according to the formed test chain, analyzing the test chain where the intersecting nodes are located to form an optimal test chain, avoiding repeated test conditions and reducing energy loss.
Further, the terminal feedback module comprises a first display unit and a second display unit, wherein the first display unit is used for displaying the analyzed test route result and the real-time image of the probe test for the relevant technicians, the relevant technicians are convenient to quickly understand the whole test process, the relevant technicians cannot know the abnormal reasons when the probe test is abnormal, and the second display unit is used for displaying the energy loss data in the test process for the relevant technicians, and when the energy loss value is abnormal, the relevant technicians are convenient to quickly overhaul.
Compared with the prior art, the invention has the following beneficial effects:
the invention obtains the chip height value in the test wafer through the ultrasonic sensor, the ultrasonic ranging technology does not depend on light rays, is insensitive to illumination and color, can be used in environments with insufficient illumination or complex color, is insensitive to electromagnetic fields, can be used in environments with electromagnetic interference, and has the characteristics of high precision, low cost, strong penetrability and the like; analyzing the influence states of the test energy sources of different chips, analyzing the energy source loss when the probe tests the chips, and starting to test the chips with large height values from high to low to form a test chain, so that the lifting frequency of the probe is reduced, and the energy source loss is reduced; the node selection indexes of the intersecting nodes of different test chains are analyzed, a test analysis model is constructed, the situation that chips are repeatedly tested is avoided, the test chain selection indexes among different test chains are analyzed, an optimal test sequence is formed, all the chips in a wafer can be tested, energy loss can be reduced to the greatest extent, and the efficiency of wafer testing is improved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a flow chart of steps of an intelligent testing method for low power consumption equipment based on artificial intelligence of the invention;
FIG. 2 is a schematic diagram of the module composition of the intelligent test system for the low-power-consumption equipment based on artificial intelligence.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides the technical scheme that: an intelligent testing method of low-power consumption equipment based on artificial intelligence, which is shown in fig. 1 as a step flow chart, comprises the following steps:
s1, acquiring information of a wafer probe test device and data information of each test wafer corresponding to the wafer probe test device, and numbering each test wafer;
in step S1, the wafer probe test apparatus information includes energy consumption data of the wafer probe test apparatus during the history test,
the number of the a test wafer is recorded as。
S2, monitoring the surface images of each test wafer in real time through ultrasonic waves, acquiring chip data information of the surface of the test wafer, and analyzing the influence states of the test energy sources of different chips to form a test chain;
in step S2, the following steps are included:
s201, placing the wafer in a plane rectangular coordinate system, wherein the coordinate system is preset by a related technician, for example, the plane rectangular coordinate system is built by taking the midpoint of the wafer as the origin, and the like, and the position coordinate information of each chip in the wafer is obtained to form a setWherein n is represented as the number of chips, +.>Position coordinate information expressed as an nth chip;
an ultrasonic sensor is arranged on the wafer probe test equipment, an image of the surface of the wafer is obtained, the height value of each chip in the wafer is obtained, and a set is formedWherein->The height value expressed as an nth chip is used for acquiring the super through the ultrasonic sensorThe difference value formed by the distance from the acoustic wave sensor to the preset position of the lower layer of the wafer and the distance from the ultrasonic sensor to the test position of the upper layer of the wafer is used as the height value of the chip;
s202, obtaining the average energy loss of the probe in a unit distance moving in the horizontal plane as follows according to the energy loss data of the wafer probe test equipment during the historical testThe average energy loss per unit distance of the probe moving in the horizontal plane is obtained by dividing the total energy loss monitored when the probe moves in the horizontal direction by the total moving distance in the preset time, and the average energy loss per unit distance of the probe moving vertically downwards is +.>The average loss of the energy source per unit distance of the probe moving vertically downwards is obtained by dividing the total loss of the energy source monitored when the probe moves vertically downwards by the total distance of the downward movement within a preset time, and the average loss of the energy source per unit distance of the probe moving vertically upwards is +.>The average energy loss of the probe in a unit distance of vertical upward movement is obtained by dividing the total energy loss monitored when the probe moves vertically upward by the total upward movement distance in a preset time, and the shortest path distance between any two chips is obtained through a shortest path algorithm, wherein the shortest path algorithm is used for calculating the shortest path from one node to all other nodes, and is mainly characterized in that the shortest path is expanded layer by layer with the starting point as the center until the shortest path is expanded to the end point, such as dijkstra algorithm, floyd algorithm, A-type algorithm and the like;
s203, for the ith chip and the jth chip, testing the loss value by the following formulaAnd (3) performing calculation:
；
wherein,expressed as shortest path distance between the ith chip and the jth chip, +.>Height value denoted as i-th chip, ">A height value denoted as j-th chip;
the chip with the largest height value in the wafer is used as a first test chip, the test loss index between the chip with the largest height value and other chips is calculated according to the fact that the height of the chip is from large to small, and the corresponding chip with the smallest test loss index is selected as a second test chip;
s204, repeating the step S203, and selecting the test chips until the selected test chips and all chips meet the following relationship:
；
wherein,expressed as a standard height, which is preset by the skilled person,
forming a test chain by taking the selected chip as a node；
S205, repeating the steps S203-S204 according to the height value of the chip from large to small to form a test chain set
Wherein m is expressed as the number of test chains, < >>Denoted as the mth test chain.
S3, analyzing node selection indexes of the intersecting nodes to the test chains by combining the intersecting node information of the different test chains, and constructing a test analysis model to obtain node selection indexes of comprehensive test schemes and corresponding change schemes corresponding to the different test chains so as to form a new test chain;
in step S3, the following steps are included:
s301, for the r test chain and the S test chain,，/>intersecting nodes form a set->Wherein c is expressed as the number of intersecting nodes, +.>Denoted as c-th intersecting node information;
s302, in the r test chain, for the intersecting nodes，/>The previous node is marked +.>The latter node is marked +.>The pair not passing through the intersection node is +.>Energy loss value->And (3) performing calculation:
；
wherein,denoted as the r test strand passes the crossing node +.>Is summed up from the measured loss values between the nodes analyzed in step S203,/->Represented as the previous node b and the intersecting node +.>Shortest path distance between ∈>Expressed as intersecting node +.>And the latter node->Shortest path distance between ∈>Represented as node b and node->The shortest path distance between them.
S303, repeating the step S302 in the S test chain to obtain a node which does not pass through the intersectionEnergy loss value->The s-th test chain passes through the crossing node +.>Energy source of (a)Total loss value +.>；
Constructing a test analysis model, selecting indexes for nodes by the following formulaAnd (3) performing calculation:
；
when (when)When (i.e.)>Indicating that the r test chain passes through the crossing node +.>The s-th test chain does not pass through the crossing node +.>The total energy loss of the test chain is larger than or equal to the sum of the energy loss of the (r) test chain without passing through an intersection node +.>The s-th test chain passes through the crossing node +.>If the total energy loss of the (2) is not detected, judging that the (r) th test chain does not pass through the crossing node +.>The s-th test chain passes through the crossing node +.>The method comprises the steps of carrying out a first treatment on the surface of the On the contrary, when->When (i.e.)>Indicating that the r test chain passes through the intersecting nodeThe s-th test chain does not pass through the crossing node +.>The total energy loss of the test chain is smaller than the energy loss of the (r) test chain without crossing the node +.>The s-th test chain passes through the crossing node +.>If the total energy loss of the (2) is determined that the (r) th test chain passes through the crossing node +.>The s-th test chain does not pass through the crossing node +.>；
S304, repeating the steps S302-S303 on all the intersecting nodes in the set B, and performing calculation analysis on the selection indexes of the intersecting nodes to form a new test chain;
s305, repeating the steps S301-S304 for all the test chains, and judging the intersecting nodes of all the test chains to form a new test chain setWherein->Denoted as mth adjusted test chain.
S4, analyzing the energy loss condition between the starting node and the ending node of any test chain according to the test chain formed in the step S3, forming an optimal test sequence, and displaying through display equipment.
In step S4, the following steps are included:
s401, combining the analysis result in the step S3, selecting a test chain with the largest chip height value in the wafer as a first test chain, and marking a chip corresponding to the last node of the test chain as u;
after removing the first test strand, the remaining test strands form a setWherein->Denoted as the m-1 th adjusted test chain after removal of the first test chain;
s402, for test chains，/>The chip corresponding to the first node is denoted v and the index +.>And (3) performing calculation:
；
wherein,expressed as the height value of the chip v, +.>Expressed as the height value of the chip u, +.>Represented as the shortest path distance between chip v and chip u;
for chip u and setThe test chain selection indexes among the first nodes of all the test chains are calculated and compared, and the test chain selection index with the smallest selection index is selectedThe corresponding test chain is the second test chain;
s403, repeating the steps S401-S402 on the chip corresponding to the first node of the second test chain, and selecting the next test chain;
s404, repeating the steps S401-S403 on all the test chains in the set K until the test chains form the optimal test sequence, displaying related technicians, such as a display screen or a mobile phone, through display equipment, so that the energy loss in the probe test process is reduced to the greatest extent.
Fig. 2 is a schematic diagram of module composition, and the low-power-consumption device intelligent test system based on artificial intelligence includes: the system comprises a test monitoring module, a database, a test analysis module and a terminal feedback module;
the output end of the test monitoring module is connected with the input end of the database, the output end of the database is connected with the input end of the test analysis module, the input end of the terminal feedback module is connected with the output end of the test analysis module, and the input end of the database is connected with the output end of the test analysis module;
the test monitoring module is used for monitoring real-time data of the wafer probe test, the database is used for intelligently managing collected data and analysis results, the test analysis module is used for analyzing energy loss of the wafer probe test and analyzing the optimal test sequence of the probe test, and the terminal feedback module is used for displaying analysis results of the probe test for related technicians through display equipment, such as a display large screen or a mobile phone.
The test monitoring module comprises an ultrasonic acquisition unit and an energy consumption acquisition unit, wherein the ultrasonic acquisition unit is used for monitoring the surface images of each test wafer in real time through an ultrasonic sensor to acquire chip data information of the surfaces of the test wafers, and the energy consumption acquisition unit is used for acquiring the energy consumption condition of the probe test equipment in real time and acquiring the energy consumption of the probe in mobile use.
The database comprises a data sharing unit and a data management unit, wherein the data sharing unit is used for carrying out data sharing on the test equipment, for unused probe test equipment, historical shared data of other equipment with the same function can be called, the use efficiency of the probe test equipment is improved, the robustness of the system is improved, the data management unit is used for carrying out encryption storage on collected data and analysis results through an encryption module, the encryption module is a module or a component for encrypting the data, and the encryption module is usually used for protecting confidentiality and integrity of the data, such as a BIOS encryption module, an OS encryption module, a network encryption module and the like, so that the safety of the data is ensured, and information leakage or tampering is avoided.
The test analysis module comprises a chip selection unit and a node judgment unit, wherein the chip selection unit is used for selecting chips forming a test chain, analyzing test influence states of different chips and analyzing energy loss conditions, and the node judgment unit is used for constructing a test analysis model according to the formed test chain, analyzing the test chain where the intersected nodes are located to form an optimal test chain, avoiding repeated test conditions and reducing energy loss.
The terminal feedback module comprises a first display unit and a second display unit, wherein the first display unit is used for displaying an analyzed test route result and a real-time image of a probe test for related technicians, the related technicians are convenient to quickly understand the whole test process, the related technicians cannot know the reason of the abnormality when the probe test is abnormal, and the second display unit is used for displaying energy loss data in the test process for the related technicians, and is convenient for the related technicians to quickly overhaul when the energy loss value is abnormal.
Example 1:
if three chips a, b and c are present, the height values are respectively，/>，/>Selecting the chip a as a first test chip; average loss of energy per unit distance of probe movement in horizontal plane +.>Energy average loss per unit distance moving vertically downwards +.>Average loss of energy per unit distance of probe moving vertically upwards +.>Shortest path distance between chip a and chip b +.>Shortest path distance between chip a and chip c +.>Then
，
，
At this time, the liquid crystal display device,the energy loss of the probe from the chip a to the chip b is larger than that of the probe from the chip a to the chip c, so that the chip c is selected as a second test chip;
if two test chains i and j have an intersecting node k, the energy loss total value of the ith test chain passing through the intersecting node kEnergy loss value without passing through intersection node k
；
Total value of energy loss of jth test chain through crossing node kEnergy loss value +.>Node selection index
，/>，
The method is characterized in that the total energy loss of the ith test chain passing through the intersecting node k is larger than that of the jth test chain not passing through the intersecting node k, and the ith test chain not passing through the intersecting node k and the jth test chain passing through the intersecting node k are judged.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. An intelligent test method for low-power consumption equipment based on artificial intelligence is characterized by comprising the following steps: comprises the following steps:
s1, acquiring information of a wafer probe test device and data information of each test wafer corresponding to the wafer probe test device, and numbering each test wafer;
s2, monitoring the surface images of each test wafer in real time through ultrasonic waves, acquiring chip data information of the surface of the test wafer, and analyzing the influence states of the test energy sources of different chips to form a test chain;
s3, analyzing node selection indexes of the intersecting nodes to the test chains by combining the intersecting node information of the different test chains, and constructing a test analysis model to obtain node selection indexes of comprehensive test schemes and corresponding change schemes corresponding to the different test chains so as to form a new test chain;
s4, analyzing the energy loss condition between the starting node and the ending node of any test chain according to the test chain formed in the step S3, forming an optimal test sequence, and displaying through display equipment.
2. The intelligent test method for the low-power-consumption equipment based on artificial intelligence as claimed in claim 1, wherein the method comprises the following steps: in step S1, the wafer probe test apparatus information includes energy consumption data of the wafer probe test apparatus during the history test,
the number of the a test wafer is recorded as。
3. The intelligent test method for the low-power-consumption equipment based on artificial intelligence as claimed in claim 2, wherein the method comprises the following steps: in step S2, the following steps are included:
s201, placing the wafer in a plane rectangular coordinate system, and acquiring position coordinate information of each chip in the wafer to form a setWherein n is represented as the number of chips, +.>Position coordinate information expressed as an nth chip;
an ultrasonic sensor is arranged on the wafer probe test equipment, an image of the surface of the wafer is obtained, the height value of each chip in the wafer is obtained, and a set is formedWherein->A height value denoted as nth chip;
s202, obtaining the average energy loss of the probe in a unit distance moving in the horizontal plane as follows according to the energy loss data of the wafer probe test equipment during the historical testThe average energy loss per unit distance of the probe moving vertically downwards is +.>The average energy loss per unit distance of the probe moving vertically upwards is +.>Acquiring the shortest path distance between any chips through a shortest path algorithm;
s203, for the ith chip and the jth chip, testing the loss value by the following formulaAnd (3) performing calculation:
；
wherein,expressed as shortest path distance between the ith chip and the jth chip, +.>Height value denoted as i-th chip, ">A height value denoted as j-th chip;
the chip with the largest height value in the wafer is used as a first test chip, the test loss index between the chip with the largest height value and other chips is calculated according to the fact that the height of the chip is from large to small, and the corresponding chip with the smallest test loss index is selected as a second test chip;
s204, repeating the step S203, and selecting the test chips until the selected test chips and all chips meet the following relationship:
；
wherein,represented by the standard height of the height-adjustable device,
forming a test chain by taking the selected chip as a node；
S205, repeating the steps S203-S204 according to the height value of the chip from large to small to form a test chain set
Wherein m is expressed as the number of test chains, < >>Denoted as the mth test chain.
4. The intelligent test method for the low-power-consumption equipment based on artificial intelligence according to claim 3, wherein the intelligent test method comprises the following steps of: in step S3, the following steps are included:
s301, for the r test chain and the S test chain, intersecting nodes form a set
Wherein c is expressed as the number of intersecting nodes, +.>Denoted as c-th intersecting node information;
s302, in the r test chain, for the intersecting nodesThe previous node is marked +.>The latter node is marked +.>The pair not passing through the intersection node is +.>Energy loss value->And (3) performing calculation:
；
wherein,denoted as the r test strand passes the crossing node +.>Energy consumption sum of>Represented as the previous node b and the intersecting node +.>Shortest path distance between ∈>Expressed as intersecting node +.>And the latter node->Shortest path distance between ∈>Represented as node b and node->The shortest path distance between them.
5. The intelligent test method for the low-power-consumption equipment based on artificial intelligence as claimed in claim 4, wherein the method comprises the following steps: in the step S3 of the process,
s303, repeating the step S302 in the S test chain to obtain a node which does not pass through the intersectionEnergy loss value->The s-th test chain passes through the crossing node +.>The total energy loss value of (2) is +.>；
Constructing a test analysis model, selecting indexes for nodes by the following formulaAnd (3) performing calculation:
；
when (when)When the test chain is judged to not pass through the crossing node +.>The s-th test chain passes through the crossing node +.>The method comprises the steps of carrying out a first treatment on the surface of the On the contrary, when->When the test chain is judged to pass through the crossing node +.>The s-th test chain does not pass through the crossing node +.>；
S304, repeating the steps S302-S303 on all the intersecting nodes in the set B, and performing calculation analysis on the selection indexes of the intersecting nodes to form a new test chain;
s305, repeating the steps S301-S304 for all the test chains, and judging the intersecting nodes of all the test chains to form a new test chain setWherein->Denoted as mth adjusted test chain.
6. The intelligent test method for the low-power-consumption equipment based on artificial intelligence according to claim 5, wherein the intelligent test method comprises the following steps of: in step S4, the following steps are included:
s401, combining the analysis result in the step S3, selecting a test chain with the largest chip height value in the wafer as a first test chain, and marking a chip corresponding to the last node of the test chain as u;
after removing the first test strand, the remaining test strands form a setWherein, the method comprises the steps of, wherein,denoted as the m-1 th adjusted test chain after removal of the first test chain;
s402, for test chainsThe chip corresponding to the first node is denoted as v, and the index is selected for the test chain by the following formulaAnd (3) performing calculation:
；
wherein,expressed as the height value of the chip v, +.>Expressed as the height value of the chip u, +.>Represented as the shortest path distance between chip v and chip u;
for chip u and setCalculating and comparing the test chain selection indexes among the first nodes of all the test chains, and selecting the corresponding test chain with the smallest test chain selection index as the second test chain;
s403, repeating the steps S401-S402 on the chip corresponding to the first node of the second test chain, and selecting the next test chain;
s404, repeating the steps S401-S403 for all the test chains in the set K until all the test chains form the optimal test sequence, and displaying the test sequences to related technicians through display equipment.
7. An intelligent test system of low-power consumption equipment based on artificial intelligence, its characterized in that: the intelligent test system of the low-power consumption equipment comprises: the system comprises a test monitoring module, a database, a test analysis module and a terminal feedback module;
the output end of the test monitoring module is connected with the input end of the database, the output end of the database is connected with the input end of the test analysis module, the input end of the terminal feedback module is connected with the output end of the test analysis module, and the input end of the database is connected with the output end of the test analysis module;
the test monitoring module is used for monitoring real-time data of the wafer probe test, the database is used for intelligently managing collected data and analysis results, the test analysis module is used for analyzing energy loss of the wafer probe test and analyzing the optimal test sequence of the probe test, and the terminal feedback module is used for displaying analysis results of the probe test for related technicians through the display equipment.
8. The intelligent test system for the low-power consumption equipment based on the artificial intelligence as claimed in claim 7, wherein: the test monitoring module comprises an ultrasonic acquisition unit and an energy consumption acquisition unit, wherein the ultrasonic acquisition unit is used for monitoring the surface images of each test wafer in real time through an ultrasonic sensor to acquire chip data information of the surface of the test wafer, and the energy consumption acquisition unit is used for acquiring the energy consumption condition of the probe test equipment in real time and acquiring the energy consumption of the probe in mobile use;
the database comprises a data sharing unit and a data management unit, wherein the data sharing unit is used for carrying out data sharing on the test equipment, historical shared data of other equipment with the same function can be called for unused probe test equipment, and the data management unit is used for carrying out encryption storage on collected data and analysis results through the encryption module.
9. The intelligent test system for the low-power consumption equipment based on the artificial intelligence as claimed in claim 8, wherein: the test analysis module comprises a chip selection unit and a node judgment unit, wherein the chip selection unit is used for selecting chips forming a test chain, analyzing test influence states of different chips and analyzing energy loss conditions, and the node judgment unit is used for constructing a test analysis model according to the formed test chain, analyzing the test chain where the intersected nodes are located and forming an optimal test chain.
10. The intelligent test system for the low-power consumption equipment based on the artificial intelligence as claimed in claim 7, wherein: the terminal feedback module comprises a first display unit and a second display unit, wherein the first display unit is used for displaying the analyzed test route result and the real-time image of the probe test for related technicians, and the second display unit is used for displaying the energy loss data in the test process for the related technicians.
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