CN117290287A - TileLink consistency protocol verification device - Google Patents
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Abstract
The invention discloses a TileLink consistency protocol verification device, which comprises: the virtual interface module is used for carrying out signal interaction with the unit to be verified; the driving module is used for sending a verification message to the virtual interface module; a sequencer module for sending the messages extracted from the send queue to the driver module; sending the message extracted from the receiving queue to a test sequence module; receiving a message sent by a monitor module and storing the message into a receiving queue and a log queue respectively; receiving a message sent by a test sequence module and storing the message into a sending sequence and the log queue respectively; the test sequence module is used for performing TileLink consistency protocol processing on the received message by adopting a callback function; and the monitor module is used for collecting the electric signals of the virtual interface module and forming a message. The invention supports the complete TileLink protocol, is suitable for CPU consistency, equipment consistency and mixed scenes thereof, simplifies the deployment of verification environment and the design and development of complex verification test excitation, and shortens the research and development period.
Description
Technical Field
The invention relates to the technical field of simulation verification, in particular to a TileLink consistency protocol verification device.
Background
TileLink is a chip-level interconnect standard that allows multiple masters to access memory and other slaves in a memory-mapped fashion that supports coherency. The design goal of TileLink is to provide a high-speed, scalable on-chip interconnect with low latency and high throughput transfer for systems on chip to connect general purpose multiprocessors, coprocessors, accelerators, DMA, and various types of simple or complex devices. Summarizing, tileLink is:
a free open tightly coupled, low latency SoC bus;
other ISAs are also supported for RISC-V (open source instruction set architecture) design;
a system for providing physical addressing and sharing memory;
can be used to build extensible, hierarchical and point-to-point networks;
providing consistent access to any number of cached or non-cached masters;
supporting all communication requirements from a single simple peripheral to a high throughput complex multi-peripheral;
meanwhile, the method also has the following important characteristics:
the memory sharing system with cache consistency supports a consistency protocol compatible with MOESI;
for any SoC system that adheres to this protocol, it can be verified that no deadlock is guaranteed;
using out-of-order concurrent operations to increase throughput;
the fully decoupled communication interface is used, so that the register can be inserted to optimize the time sequence;
transparent self-adaption of bus width and automatic segmentation of burst transmission sequences;
signal decoding optimized for power consumption;
however, in the simulation verification work, there is no matched verification component, especially a device supporting CPU and DMA consistency protocol verification at the same time.
Disclosure of Invention
The invention aims at solving the problems existing in the prior art, and provides a TileLink consistency protocol verification device which is used for solving the problem that the support of simulation verification on the TileLink consistency protocol verification is lacking in the prior art and realizing the TileLink consistency protocol verification which simultaneously supports a CPU and a DMA.
As shown in fig. 1, the present invention provides a TileLink consistency protocol verification apparatus, including:
the virtual interface module is used for carrying out signal interaction of TileLink consistency protocol verification with the unit to be verified;
the driving module is used for sending a verification message to the virtual interface module;
a sequencer module for sending messages extracted from the send queue to the driver module; sending the message extracted from the receiving queue to a test sequence module; receiving a message sent by a monitor module and storing the message into the receiving queue and the log queue respectively; receiving a message sent by a test sequence module and storing the message into the sending sequence and the log queue respectively;
the test sequence module is used for performing TileLink consistency protocol processing on the received message by adopting a callback function;
the monitor module is used for collecting the electric signals of the virtual interface module and forming a message;
specifically, the virtual interface module realizes the support of physical channels of TL-UL protocol, TL-UH protocol and TL-C protocol, and provides a connection interface between the unit to be verified and the TileLink consistency protocol verification device. One of the physical channels of the TL-UL protocol, the TL-UH protocol, and the TL-C protocol may be selected by a configuration module. The device is provided with a TileLink A, B, C, D and E input and output paths for all physical channels, TL-C for consistent upstream design DUT connections and TL-UL/UH for connection access paths.
The drive module receives and transmits the consistency message for verification to the physical channel of TileLink, for example, receives and transmits the consistency message conforming to TileLink1.8.0-1.8.1 specification through the physical channel of TL-C. Messages are fetched from the transmit queues of the sequencer module and level signals are driven to the virtual interface module. And the sequencer module is used for buffering, transferring and scheduling the consistent messages in the device and comprises an acceptance queue, a sending queue and a log queue.
And a test sequence module for implementing the consistency protocol processing logic, such as logic processing compliant with the tilelink1.8.0-1.8.1 consistency specification. Processing a message received from a sequencer receiving queue, sending the message of queue filling transmission to the sequencer, and simultaneously filling the message of transmission or receiving to a log queue, wherein the message comprises a Cache analog data structure for storing TTag and CacheLine data; and the configuration of the delay beat number and the consistency return mode is realized by combining a queue buffer method with a configuration file. The consistency request is suspended in the queue, enters a consistency processing callback function in an out-of-order or sequential manner through configuration decision, determines the simulation beat number through configurable processing delay in a consistency component, and can send IO requests with various granularities from an A channel according to TileLinkUL specification by a test sequence module, receive the IO requests in a D channel and be used for developing IO access/traversal excitation by the test sequence module.
And the monitor module is used for collecting the electric signals of the virtual interface module, forming a message and recording the protocol processing process.
According to the technical scheme, through data interaction among the virtual interface module, the driving module, the sequencer module and the test sequence module and adoption of the callback function to perform TileLink consistency protocol verification on interaction data, support of TileLink consistency protocol verification simulation verification is achieved, a complete protocol is supported, and the method is applicable to CPU consistency, equipment consistency and mixed scenes thereof, so that deployment of a verification environment and design development of complex verification test excitation are simplified, and a research and development period is shortened.
Optionally, the test sequence module is provided with a Cache simulation Data structure for storing a TTag array and a Data array, wherein the TTag array stores the consistency state of a Cache line address in a Cache; the Data array stores specific Data of a CacheLine address.
Specifically, the coherency state includes: nothing, trunk, tip, branch, toB, toT, toN, etc.
Optionally, the callback function is adopted to perform TileLink consistency protocol processing on the received message, and the method further comprises the following steps:
the callback function captures a message input into the A channel;
converting the message of the input A channel into a Probe request, forwarding the Probe request through the input B channel, and registering a mark of an address of the Probe request in a TTag array of the Cache simulation data structure as a consistency state of the Probe request;
according to the consistency state of the Probe request, the input C channel sends out a corresponding Probe ack, and then sends a read or write request to the output A channel;
receiving an acknowledgement message sent by an output D channel; when the confirmed message is Access AckData, storing the Access AckData into a Data array in the Cache simulation Data structure, and updating the TTag state of the Cache line corresponding to the address of the Access AckData in the Cache simulation Data structure;
and returning the confirmation message sent by the output D channel to the unit to be verified through the input D channel.
Specifically, the callback function may be an access request for enhancing authority to the input a channel, for example, the unit to be verified (such as a multiprocessor, a coprocessor, an accelerator and a DMA device) may also be a read-write request, for example, a Get/Put request sent by the DMA device.
And converting the message input into the A channel into a Probe request, forwarding the Probe request through the B channel, and marking the address of the Probe request into a specific intermediate state or a final state according to a data specific state (None, trunk, tip, branch) and a Probe request type in a TTag array of the Cache analog data structure and according to a TileLink consistency specification.
And converting the message of the A channel into a Probe request corresponding to the consistency state according to the consistency state of the input A channel, and updating the address of the Probe request to be marked in a TTag array. For example, converting the Acquire request of the NtoB into the Probe request of the toB, and registering the mark of the address of the Probe request in the TTag array of the Cache simulation data structure as toB; converting the NtoT acquisition request into a toT Probe request, and registering the mark of the address of the Probe request in a TTag array of a Cache simulation data structure as toT; the Acquire request of toT is converted into a Probe request of TtoT, and the tag of the address of the Probe request in the TTag array of the Cache emulation data structure is registered as toT or the like. The converted Probe request is forwarded to a unit to be verified or a core unit (DTU CPU) and the like through an input B channel.
After the device forwards the Probe request through the input B channel, the input C channel sends out a corresponding Probe ack according to the consistency state of the Probe request. That is, the device waits for a reply message for a Probe request sent from the input C channel by the unit to be authenticated or by the DTU CPU.
After the callback function captures the acknowledgement message sent by the input C channel, a read-write request is sent to the output a channel, for example, a Put or Get request is sent to a memory controller connected to the output a channel.
Receiving an acknowledgement message sent by an output D channel; the input D-channel will generate different sourceid to distinguish the returns to the DUT CPU or device according to different request sources and operations, i.e., multiplexing the D-channel by sourceid arbitration.
When the confirmed message is Access AckData, storing the Access AckData into a Data array in the Cache simulation Data structure, and updating the TTag state of the Cache line corresponding to the address of the Access AckData in the Cache simulation Data structure; for example, after receiving the AccessAckData when the DTU CPU reads and misses, the TTag state of the CacheLine corresponding to the address of the AccessAckData in the Cache analog data structure is updated to B.
Optionally, converting the message of the a channel into a Probe request, further includes:
if the message is an Accuire request of NtoB, converting the message into a Probe request of toB;
if the message is an Accuire request of BtoT or NtoT, converting the message into a Probe request of toT;
if the message is a Get request, converting the message into a Probe request of toB;
if the message is PutFullData, putPartialData, arithmeticData and LogicalData, converting the message into toN Probe request;
if the message is a Hint request, if the message is read pre-fetch, the message is converted into a Probe request of toB; if it is a write prefetch, the message is converted into a Probe request of toN.
Optionally, according to the consistency state of the Probe request, the input C channel sends out a corresponding ProbeAck, and further includes:
when the consistency state of the Probe request is ToB, the callback function sends out a ProbeAck of toB and BtoB, ntoN, probeAckData from an input C channel according to the local data state;
when the consistency state of the Probe request is ToN, the callback function sends out a ProbeAck of BtoN and NtoN from an input C channel;
when the consistency state of the Probe request is toT, a BtoN, ntoN, ttoN ProbeAck is sent out from the input C channel.
Specifically, when the consistency state of the Probe request is ToB, toB (device read), btoB (cpu read hit clean), ntoN (cpu read miss), probeAckData (cpu read hit dirty) ProbeAck is sent from the input C channel.
When the consistency state of the Probe request is ToN, btoN (write hit cleaning) is sent out from the input C channel, and a ProbeAck (write miss) of NtoN.
When the consistency state of the Probe request is toT, btoN (write hit clean), ntoN (write miss), tto N (write hit dirty) is issued from the input C channel.
Optionally, the callback functions include a reduced mode callback function and a complex simulation mode callback function;
the simplified mode callback function is only used for verifying a TileLink consistency protocol of the DMA device;
the complex simulation mode callback function is used for processing a TileLink consistency protocol of equipment and a simulation secondary cache.
Optionally, in the reduced mode, no CPU validation unit is required, no Probe request is forwarded, and no update of the Cache emulation data structure is performed.
The consistency verification flow of the DMA device can be independently completed without participation of a CPU verification unit through the simplified mode.
Optionally, the device further includes a configuration module, configured to configure physical channel selection of TL-UL interface, TL-UH interface, and TL-C interface in the virtual interface module; and the method is also used for configuring the selection of a simplified mode or a complex mode of the callback function in the test sequence module.
Specifically, the configuration module is also used for configuring the delay beat number of hit/miss of the analog Cache, the consistency return mode and the address data bit width; the Cache hit mode comprises hit and miss, and the consistency return mode comprises sequential return and out-of-order return. The return response delay and request order in the configuration reduced mode are also supported.
The configuration module is further configured to configure the response delay and request sequence in the reduced mode, for example, the response delay and request sequence can be configured into a sequence, a reverse sequence and a random shuffling mode.
Optionally, in the reduced mode, a set of TileLink Master interfaces is also provided, and the supporting cpu_read function and cpu_write function are encapsulated.
Specifically, the reduced mode provides a set of TileLink Master interfaces in addition to modeling the coherency responses for a miss, and encapsulates the supporting cpu_read, cpu_write functions for replacing DUT CPU functions in the reduced mode.
Optionally, a clock block is used for describing a TileLink full-protocol physical channel and is used for simulating various configurable sampling moments, and meanwhile, the device has a consistency secondary cache simulation function facing DUT CPU consistency design verification or a consistency upstream device simulation function facing DMA devices.
Compared with the prior art, the invention has the beneficial effects that:
(1) According to the invention, through data interaction among the virtual interface module, the driving module, the sequencer module and the test sequence module and adopting the callback function to perform TileLink consistency protocol verification on interaction data, the support of TileLink consistency protocol verification simulation verification is realized, a complete protocol is supported, and the method is applicable to CPU consistency, equipment consistency and mixed scenes thereof, so that verification environment deployment is simplified, and research and development period is shortened.
(2) According to the invention, the A, B, C, D channel processing flow is optimized through the callback function, so that the transaction processing flow in various scenes is optimized, and the coverage rate driven protocol-related simulation verification work is improved.
(3) The invention configures the virtual interface module and the test sequence module by setting the configuration module, provides flexible and configurable delay and simplified modes, can be configured to generate a large number of random demand type messages, and simplifies coverage rate excitation production.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a TileLink consistency protocol verification device according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an application scenario of a TileLink consistency protocol verification apparatus in a multi-core consistency system according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an application scenario when the TileLink consistency protocol verification device according to the embodiment of the present invention is used as a function of a simulation CPU;
FIG. 4 is a schematic diagram of a processing flow in the case of a read miss of a single core DTU CPU according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a processing flow in the case of a write miss of a single core DTU CPU according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a processing flow during single core DTU CPU write hit cleaning according to an embodiment of the invention;
FIG. 7 is a schematic diagram of a processing flow when a single core DTU CPU write hit is dirty according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a process flow in a simplified mode of DUT DMA device read misses in accordance with an embodiment of the invention;
FIG. 9 is a schematic diagram of a process flow in a DUT DMA device read miss complex mode in accordance with an embodiment of the invention;
FIG. 10 is a schematic diagram of a process flow in a simplified mode of DUT DMA device write misses in accordance with an embodiment of the invention;
FIG. 11 is a schematic diagram of a process flow in a DUT DMA device write miss complex mode in accordance with an embodiment of the invention;
FIG. 12 is a schematic flow diagram of a process for DUT DMA device reading a hit in complex mode and a hit dirty in the core, in accordance with an embodiment of the present invention;
FIG. 13 is a schematic diagram of a process flow for a DUT DMA device read hit in a complex mode and hit dirty locally in accordance with an embodiment of the present invention;
FIG. 14 is a schematic diagram of a process flow for a DUT DMA device read hit in a complex mode and hit local cleaning in accordance with an embodiment of the present invention;
FIG. 15 is a schematic diagram of a process flow for DUT DMA device read hit in complex mode and hit core cleaning in accordance with an embodiment of the present invention;
FIG. 16 is a schematic diagram of a process flow for a DUT DMA device write hit in complex mode and hit local or core cleaning in accordance with an embodiment of the present invention;
FIG. 17 is a flow chart of a process for a DUT DMA device in write hit complex mode and with a hit dirty in the core, according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on embodiments of the present invention, are within the scope of the present invention.
As shown in fig. 1, the present embodiment provides a TileLink consistency protocol verification apparatus, which is presented as a standardized verification IP of general verification methodology (Universal Verification Methodology, UVM) and is composed of standardized UVM components. The device comprises:
Virtual-InterFace module (Virtual-InterFace) in which a mod port is used to distinguish TL-C from TL-UL physical channels, wherein TL-C physical channels are compatible with TL-UH, TL-C corresponds to an input channel, and TL-UL corresponds to an output channel.
Configuration module (config): the physical channel selection is used for configuring a TL-UL interface, a TL-UH interface and a TL-C interface in the virtual interface module; and the method is also used for configuring the selection of a simplified mode or a complex mode of the callback function in the test sequence module. The method is also used for configuring the delay beat number of hit/miss of the analog Cache, the consistency return mode and the address data bit width; the Cache hit mode comprises hit and miss, and the consistency return mode comprises sequential return and out-of-order return.
Drive module (Driver): for receiving and transmitting coherence messages (TL-items) to the physical channels of the TL-C.
Callback function module (Callback): the callback function comprises a simplified mode callback function and a complex simulation mode callback function, the simplified mode callback function supports DMA consistency simulation, and the complex simulation mode callback function supports a consistency protocol processing flow of equipment and a simulation secondary cache. In the reduced mode, no Probe request is forwarded, and no matter what circumstances, the miss is handled uniformly.
The Agent can be configured into a Master mode or a Slave mode according to the TL-config file, and the Driver is responsible for processing the TL-item transmitted from the interface, and combines with a callback to organize a corresponding message sent to the corresponding interface according to the request type of the corresponding consistency protocol in the item.
Tables 1, 2 and 3 are respectively three channel message handling correspondence tables of Callback.
Table 1CallbackC channel message handling
In the Callback, for the transform ProbeAck type, a special source id is indicated for forwarding arbitration, toB is 2 in the source id high 3, and tot is 3 in the source id high 3.
Table 2CallbackA channel message handling
Table 3Callback B channel message handling
Specifically, the device adopts a clock block to describe a TileLink full-protocol physical channel. The system is used for simulating various configurable sampling moments, and simultaneously has a consistency secondary cache (cache) simulation function facing to the consistency design verification of a DUT CPU (CPU to be designed) or a consistency upstream equipment simulation function facing to DMA equipment.
As an alternative embodiment, the apparatus further comprises a coherence protocol process Monitor module (Monitor) for recording protocol processes.
Specifically, the callback parameters corresponding to the simplified mode or the complex simulation mode are selected through the configuration parameters of the consistency protocol configuration module to simulate the Cache hit mode. In Monitor, the data transmitted on each channel is captured in real time, and according to the protocol standard, the condition that the protocol is not met is described by using an ascert.
Specifically, the implementation mode of simulating the hit/miss of the CPU Cache is as follows: selecting a callback function for simplifying or complicated simulation of two modes by using configuration parameters, wherein the callback function for simplifying the mode never hits against a Probe request of the equipment and does not need a cache simulation structure; the complex simulation mode callback function builds a TTag array and a Mem array based on the associated array, wherein the TTag array stores the consistency state (Nothing, trunk, tip and Branch) of the cache line address in the cache, and the Mem array stores specific data of the cache line address.
Specifically, the configuration of the delay beat number and the consistency return mode is realized by combining a queue buffer method with a configuration file.
The coherence requests are suspended from the queue, enter the coherence processing callback function in an out-of-order or sequential order by configuration decisions, and determine the number of simulated beats by configurable processing delays in the coherence component.
Specifically, the reduced mode does not require DUT DPU coordination, and the reduced mode supports configuration return response delays and request order.
The reduced mode may be used independently without requiring DUT CPU coordination, may support configuration return response delay, may also support configuration request order, and may be configured in order, reverse order, random shuffle mode.
Specifically, the input D channel of the TileLink channel generates different source ids to distinguish returns to the DUT CPU or DMA device according to different request sources and operations.
Among the input TileLink channels, the input D channel generates different sourceids to distinguish the returns to the DUT CPU or device according to different request sources and operations, i.e., the D channel is multiplexed by sourceid arbitration.
Specifically, in the simplified mode, a set of TileLink Master interfaces is also provided, and the cpu_read function and the cpu_write function that are matched are encapsulated. In addition to simulating the consistency response of the miss, the chemical mode also provides a set of TileLink Master interfaces, and encapsulates the matched CPU_read and CPU_write functions for simplifying the mode to replace the DUT CPU functions.
FIG. 2 shows the device used for CPU consistency design verification, in which case the answer response of the off-chip consistency component to the CPU consistency request can be completed and a secondary Cache simulation capability is provided.
Fig. 3 shows that the device is used for simulating the consistency behavior of the CPUDMA, and is configured into a simplified mode in the scene, so that the delay of each stage and the packet returning sequence of the access request of the equipment under the consistency protocol flow can be flexibly configured.
The processing logic for performing consistency verification under different conditions based on the device of the embodiment is as follows:
(1) Single core DUT CPU read misses:
as shown in fig. 4, the callback function captures the acquisition request of the NtoB sent by the DUT CPU to the device input a channel (in.a, the same applies below);
the callback function converts the Acquire request into a Probe request of toB, sends the Probe request to the DUT CPU through a B channel, and registers a mark of a Probe request address in TTag as toB;
the device waits for a ProbeAck of BtoB of an opcode sent by a C channel (in.c, the same applies below) of the DUT CPU, and after receiving the ProbeAck, the device sends a read request to an output A channel (out.a, the same applies below);
the device waits for an AccessAckData sent by an output D channel (out.d); after receiving the Access AckData, the device sends the Access AckData state to the Mem array, and marks the TTag state of the CacheLine corresponding to the address in the array as B;
the device returns the AccessAckData to the DUT CPU through the input D channel (in.d, supra) of the DUT CPU.
(2) Single core DUT CPU write misses:
as shown in fig. 5, the callback function captures the acquisition request of the NtoT sent by the DUT CPU to the device input a channel;
the callback function converts the Acquire request into a Probe request of toT, sends the Probe request to the DUT CPU through the B channel, and registers a mark of a Probe request address in TTag as toN;
the device waits for the opcode which is NtoN ProbeAck and is sent by the C channel of the DUT CPU, and the device sends a write request to the output A channel;
the device waits for outputting the Access AckData sent by the D channel, and returns the Access AckData to the DUT CPU after receiving the Access AckData, and marks the TTag state of the CacheLine corresponding to the Access AckData address as N.
(3) Single core DUT CPU write hits:
as shown in fig. 6, in the write hit cleaning case:
the callback function captures an Acquire request of BtoT sent by the DUT CPU to the device input A channel;
the callback function converts the Acquire request into a Probe request of BtoT, sends the Probe request to the DUT CPU through a B channel, and registers a mark of a Probe request address in TTag as toN;
the device waits for the opcode sent by the C channel of the DUT CPU to be the ProbeAck of BtoN, and the callback function captures the ProbeAck, and the device sends a write request to the output A channel;
the device waits for outputting an Access ack sent by the D channel, returns DUT CPUAccessAckData from the input D channel, and changes TTag in the device into TinC;
as shown in fig. 7, in the case of a write hit dirty:
the device captures the acquisition request of toT sent by the DUT CPU to the device input A channel;
the device converts the Acquire request into a Probe request of Tto, and sends the Probe request to the DUT CPU through the B channel, and simultaneously registers the mark of the Probe request address in TTag as toN;
the device waits for a ProbeAck with the opcode of TtoN sent by a C channel of the DUT CPU, captures the ProbeAck by a callback function, waits until ReleaseData in an input A channel and sends a write request to an output A channel;
the device waits for an AccessAck of the output D channel, returns DUT CUP ReleaseAck from the input D channel, and changes the corresponding address TTag of the device to N.
(4) Single core DUT CPU read hits:
under the condition that the DUT CPU reads the hit device, the device does not respond and is processed by primary cache consistency logic inside the DUT CPU.
(5) DUT DMA device read miss:
the DUT DMA device initiates get requests through the input A channel, the callback function captures, queries Tcache model misses, and then separates into two cases:
as shown in fig. 8, configured in a simplified mode: accessing the target address to an output A channel, not registering the local Tcache and TTag, waiting until the D channel is accessAckData, and returning to the DUT DMA device through the input D channel;
as shown in fig. 9, the configuration is a complex simulation: registering a target address TTag as toB, initiating a Probe request of toB to an input B channel, waiting for a DUT CPU to come from an Nton Probe ack of an input C channel, accessing the target address to an output A channel, waiting for an accessAckData of an output D channel, registering TTag as B after data arrives, storing Mem, and finally returning the data to the DUT DMA device to the input D channel.
(6) DUT DMA device write miss:
DUT DMA equipment initiates get requests through input a channel, callback functions capture, and then fall into two cases:
as shown in fig. 10, configured in a simplified mode: directly initiating a read data request to an output A channel, waiting for an output D channel Access DataAck, and directly returning data to an input D channel after the read data request arrives;
as shown in fig. 11, the configuration is a complex pattern: registering a target address TTag as toT, sending toT Probe request to an input B channel, waiting for a DUT CPU to come from an Nton Probe ack of an input C channel, writing access memory to the address to an output A channel, writing data into a local Mem, waiting for an output D channel Access ack, returning the Access ack to the input D channel, and finally changing the local map TTag to T.
(7) DUT DMA device read hits (complex simulation):
as shown in fig. 12, the hit is dirty at the core: the DUT DMA equipment initiates a get request through an input A channel, a callback function is used for capturing, a local TTag is queried and marked as TinC, a Probe request of tob is sent to an input B channel, a DUT CPU is waited for from a probeAckData of an input C channel, then the DUT CPU is written back to ddr from an output A channel, after the writing of an output D channel is completed ack, reading of the address is initiated from the output A channel, and after the reading of the output D channel is completed, the accessDataAck is returned to the input D channel;
as shown in fig. 13, the hit dirty is local to the device: the DUT DMA equipment initiates get requests through an input A channel, a callback function captures, queries a local TTag mark as T, sends a Probe request of toN to an input B channel, waits for the Probe ack of the DUT CPU from the input channel, writes back the address data from the output A channel, waits until an output D channel writes back the ack, sends out get requests from the output A channel, waits until the output D channel returns data, and returns data to the input D channel;
as shown in fig. 14, the hit device cleans locally: the DUT DMA equipment initiates a get request through an input A channel, a callback function captures, a local TTag is queried to be marked as B, and an Access DataAck with data is returned to an input D channel;
as shown in fig. 15, hit core clean: the DUT DMA device initiates get request through the input A channel, captures the callback function, inquires the local TTag marked as I miss, initiates toB Probe request to the input B channel, waits for the DUT CPU to initiate access to the address from the BtoB Probe ack of the input C channel, then initiates access to the address from the output A channel, waits for the Access DataAck of the output D channel, and outputs the Access DataAck to the input D channel to return to the device after receiving the access DataAck.
(8) DUT DMA device write hits (complex simulation):
the DUT DMA device initiates a put request through an input A channel, and a callback function captures and inquires about a local TTag:
as shown in fig. 16, mark B (hit core or device clean): and sending a Probe request of toT to an input B channel, marking TTag of a local corresponding address as toT, storing data, waiting for a Probe ack of BtoN of a DUT CPU, initiating a ddr writing operation to an output A channel, and returning a successful writing Access ack from the input D channel to the device after waiting for the Access ack of the output D channel, and changing the local TTag as T.
As shown in fig. 17, labeled TinC (hit core): registering the address with a mark toI, sending toT Probe request to the input B channel, waiting for the ReleaseData reply of the DUT CPU, writing back to the output A channel according to the mask, waiting for writing back the Access ack of the output D channel, and returning the ReleaseAck to the input D channel for the DUT CPU.
Marked T (hit device local dirty): the mark of the registered local address is toI, after the local Mem is written according to the mask, the data is taken out and written back to the output A channel, the writing back of the output D channel is waited for, and then the AccessAck is returned to the input D channel.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A TileLink consistency protocol verification apparatus, comprising:
the virtual interface module is used for carrying out signal interaction of TileLink consistency protocol verification with the unit to be verified;
the driving module is used for sending a verification message to the virtual interface module;
a sequencer module for sending messages extracted from the send queue to the driver module; sending the message extracted from the receiving queue to a test sequence module; receiving a message sent by a monitor module and storing the message into the receiving queue and the log queue respectively; receiving a message sent by a test sequence module and storing the message into the sending sequence and the log queue respectively;
the test sequence module is used for performing TileLink consistency protocol processing on the received message by adopting a callback function and actively simulating the CPU to send out an IO request based on the TileLink protocol;
and the monitor module is used for collecting the electric signals of the virtual interface module, forming a message and asserting the validity of the protocol.
2. The TileLink consistency protocol verification device according to claim 1, wherein the test sequence module is provided with a Cache simulation Data structure for storing a TTag array and a Data array, and the TTag array stores a consistency state of a CacheLine address in a Cache; the Data array stores specific Data of a CacheLine address.
3. The TileLink consistency protocol verification apparatus according to claim 2, wherein the test sequence module is specifically configured to:
capturing a message input into the A channel by adopting the callback function;
converting the message of the input A channel into a Probe request, forwarding the Probe request through the input B channel, and registering a mark of an address of the Probe request in a TTag array of the Cache simulation data structure as a consistency state of the Probe request;
according to the consistency state of the Probe request, the input C channel sends out a corresponding Probe ack, and then sends a read or write request to the output A channel;
receiving an acknowledgement message sent by an output D channel; when the confirmed message is Access AckData, storing the Access AckData into a Data array in the Cache simulation Data structure, and updating the TTag state of the Cache line corresponding to the address of the Access AckData in the Cache simulation Data structure;
and returning the confirmation message sent by the output D channel to the unit to be verified through the input D channel.
4. The TileLink consistency protocol verification apparatus according to claim 3, wherein the converting the message of the a channel into a Probe request further comprises:
if the message is an Accuire request of NtoB, converting the message into a Probe request of toB;
if the message is an Accuire request of BtoT or NtoT, converting the message into a Probe request of toT;
if the message is a Get request, converting the message into a Probe request of toB;
if the message is PutFullData, putPartialData, arithmeticData and LogicalData, converting the message into toN Probe request;
if the message is a Hint request, if the message is read pre-fetch, the message is converted into a Probe request of toB; if it is a write prefetch, the message is converted into a Probe request of toN.
5. The TileLink consistency protocol verification apparatus according to claim 3, wherein the input C channel issues a corresponding ProbeAck according to a consistency state of the Probe request, further comprising:
when the consistency state of the Probe request is ToB, the callback function sends out a ProbeAck of toB and BtoB, ntoN, probeAckData from an input C channel according to the local data state;
when the consistency state of the Probe request is ToN, the callback function sends out a ProbeAck of BtoN and NtoN from an input C channel;
when the consistency state of the Probe request is toT, a BtoN, ntoN, ttoN ProbeAck is sent out from the input C channel.
6. The TileLink consistency protocol verification apparatus of claim 1, wherein the callback functions include a reduced mode callback function and a complex simulated mode callback function;
the simplified mode callback function is only used for verifying a TileLink consistency protocol of the DMA device;
the complex simulation mode callback function is used for processing a TileLink consistency protocol of equipment and a simulation secondary cache.
7. The TileLink consistency protocol verification apparatus according to claim 4, wherein in the reduced mode, no CPU verification unit is required, no Probe request is forwarded, and no update of the Cache analog data structure is performed.
8. The TileLink consistency protocol verification apparatus according to claim 1, further comprising a configuration module configured to configure physical channel selection of TL-UL, TL-UH, and TL-C interfaces in the virtual interface module; and the method is also used for configuring the selection of a simplified mode or a complex mode of the callback function in the test sequence module.
9. The TileLink consistency protocol verification apparatus according to claim 6, wherein in the reduced mode, a set of TileLink Master interfaces is further provided, and the cpu_read function and the cpu_write function are encapsulated.
10. The TileLink consistency protocol verification device according to claim 6, wherein a block is used to describe a TileLink full protocol physical channel for simulating various configurable sampling moments, and the device has a consistency secondary cache simulation function facing to DUT CPU consistency design verification or a consistency upstream device simulation function facing to DMA devices.
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