CN117278031A - ADC system noise model circuit based on time interleaving assembly line - Google Patents
ADC system noise model circuit based on time interleaving assembly line Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
Abstract
The invention discloses a noise model circuit based on a time interleaving assembly line ADC system, which relates to the technical field of integrated circuits and comprises an isolation amplifier noise model, a reference circuit noise model and a time interleaving assembly line ADC model; the noise model of the isolation amplifier is composed of an operational amplifier and an external feedback structure, and is used for processing thermal noise of the operational amplifier and a feedback network thereof; the reference circuit noise model is used for processing thermal noise and quantization noise generated by the reference circuit; the time interleaving assembly line ADC model comprises a time interleaving circuit and an assembly line ADC, and is used for processing noise generated by a sampling structure and an operational amplifier; the invention structurally not only comprises the traditional ADC structure, but also innovatively considers the influence of the isolation amplifier and the power supply, and has better guiding function for constructing a highly integrated ADC system.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a noise model circuit of an ADC system based on a time interleaving assembly line.
Background
Noise is the most dominant factor affecting high-speed and high-precision ADCs, and research into power consumption and the presence of noise required by circuits has begun from the advent of integrated circuits. As the feature sizes of devices enter deep submicron, the impact of noise in CMOS circuits, particularly digital-to-analog hybrid circuits, on circuit performance becomes more and more pronounced, and noise problems have begun to rise to another bottleneck problem. The study of the low noise problem of the digital-analog hybrid circuit involves three parts, a noise source, a coupling medium and a receiving part (a circuit sensitive to noise, etc.). Therefore, the noise reduction approach is to try to remove, reduce or convert any one or more of the three above, where the noise source is the inherent noise of the device and the interference noise is composed of thermal noise and 1/f noise, and the inherent noise of the CMOS device mainly includes thermal noise and 1/f noise, while the interference noise in the circuit has more sources, and the crosstalk noise of the signal, the substrate coupling noise, the voltage drop of the power supply, the ground bounce noise, and the charge distribution effect, i.e. the charge sharing noise, all affect the performance of the digital-analog hybrid circuit.
Noise sensitive circuits are referred to in the digital-to-analog hybrid circuit mainly as analog circuit parts. With the rapid development of CMOS very large scale integrated circuit fabrication technology, modern communications are continuously increasing the signal frequency and accuracy requirements. ADCs using clock-alternating and SAR structures no longer meet design requirements in terms of accuracy performance. The superposition requirement of a Pipeline (Pipeline) structure and a clock alternation technology becomes urgent, and a designer combines the pipeline+clock alternation structure or other novel structures such as a composite structure and clock alternation, so that the selection of the high-speed and high-precision ADC design becomes diversified. The research direction of the current high-speed high-precision ADC is that the resolution is more than 10 bits, and the sampling rate is of the order of GHz. The high-speed high-precision ADC has wide application range, in particular to a high-performance ADC design technology, and the high-precision design technology is required for coping with pulse signals. In response to agile signals, ADCs require development of high-speed sampling techniques. Therefore, the most critical problem in developing a high-speed ADC is to establish an accurate noise model, so that the noise model can effectively serve the design work of the ADC, and the dynamic performance of the ADC can be accurately estimated at the beginning of engineering.
In the prior art, the high-speed ADC has various structures, noise has randomness, the amplitude of the noise can not be predicted, the average power of the noise can only be predicted to represent the noise, the noise analysis is simplified by using an auxiliary theorem, and the corresponding noise is mathematically modeled. In complex ADC systems, it is difficult to try to abstract out the model of the noise and the noise sources are very large.
Disclosure of Invention
The invention aims to provide a noise model circuit of an ADC system based on a time interleaving pipeline, which aims to effectively serve the performance evaluation of the ADC and reduce errors caused by noise when researching a high-speed ADC.
In order to solve the technical problems, the invention provides a time interleaving pipeline ADC system noise model circuit, which comprises an isolation amplifier noise model, a reference circuit noise model and a time interleaving pipeline ADC model;
the noise model of the isolation amplifier is composed of an operational amplifier and an external feedback structure, and is used for processing thermal noise of the operational amplifier and a feedback network thereof;
the reference circuit noise model is used for processing quantization noise generated by the reference circuit;
the time interleaving assembly line ADC model comprises a time interleaving circuit and an assembly line ADC, and is used for processing noise generated by a sampling structure and an operational amplifier;
the pipelined ADC comprises a clock generation circuit, a pipelined conversion structure, a delay alignment register array and a digital correction circuit, and the total noise model of the first-stage pipelined structure is calculated by carrying out noise analysis on the first-stage pipelined structure.
Preferably, the clock generating circuit is configured to generate two groups of phase non-overlapping clock control signals, control a multi-stage pipeline of the pipeline conversion structure, and make the circuits work alternately by using different time sequences;
the pipeline conversion structure is used for dividing the conversion operation into multiple stages, converting each stage to obtain a positioned digital output bit to form a pipeline working mode, and mainly processing thermal noise and flicker noise generated by a sampling hold circuit and an operational amplifier of each stage;
the delay alignment register array adjusts and synchronizes output data of each level of pipeline conversion structure;
the digital correction circuit corrects the conversion result by using the redundancy bits.
Preferably, the pipeline conversion structure of each stage comprises a sub MDAC and a sub ADC; the MDAC comprises a sample hold circuit and a sub-DAC for realizing digital-to-analog conversion, subtraction, amplification and sample hold functions.
Preferably, the sample hold circuit is used for collecting the analog signal input by the ADC circuit, and holding the sampling value until the next clock period comes, and then supplying the sampling value to the post-stage circuit for quantization processing;
the sub-DAC is used for converting digital output codes in the pipeline conversion structure of each stage into analog signals.
Preferably, the sample-hold circuit is equivalent to a switched capacitor circuit, the switched capacitor circuit includes a sampling capacitor Cs1, a feedback capacitor Cf1, an operational amplifier OTA, and equivalent noise of the sample-hold circuit is as follows:
in the middle ofkIs BoltzThe man-constant is used to determine the number of the cells,Tthe temperature is set to be the absolute temperature,C s1 for the capacitance value of the sampling capacitance Cs1,C f 1 the capacitance value of the feedback capacitor Cf 1;
the equivalent noise voltage of the operational amplifier OTA is:
（11）；
in the method, in the process of the invention,n f is a noise factor, is determined by the structure of the operational amplifier,C c1 the capacitance value is compensated for the miller of the operational amplifier,，kis a boltzmann constant,Tabsolute temperature.
Preferably, the pipelined ADC includes a plurality of pipelined stage circuits, the first stage circuit equivalent noise being calculated by:
in the method, in the process of the invention,n f representing the noise factor, is determined by the structure of the operational amplifier, gamma is the noise figure of the transistor,C c1 is the miller compensation capacitance value of the operational amplifier,，C s1 for the capacitance value of the sampling capacitance Cs1,C f 1 for the capacitance value of the feedback capacitance Cf1,kis a boltzmann constant,Tabsolute temperature>Is the equivalent noise voltage of the operational amplifier.
Preferably, the output noise of the isolation amplifier noise model is:
in the middle of，GainR is the gain of the amplifier 1 、R 2 Respectively is a resistor R 1 Resistance R 2 Is used for the resistance value of the (a),BW n for noise bandwidth, k is the boltzmann constant,R eq is a resistor R 1 Resistance R 2 Is used for the control of the resistance of the capacitor,T k is Kelvin temperature.
Compared with the related art, the invention has the following beneficial effects:
the high-speed ADC provided by the invention adopts a Pipeline (Pipeline) +time interleaving sampling structure, and meets the requirements of the high-speed ADC better. In the noise source of the high-speed ADC, the proportion of clock jitter is increased, and the proportion of the clock jitter is gradually increased along with the continuous rise of clock frequency, which is closely related to the thermal noise and the noise of a power supply, so that the invention structurally comprises the traditional ADC structure, creatively considers the influence of an isolation amplifier and the power supply, and has better guiding function for building a highly integrated ADC system. For noise analysis, a noise mechanism and an equivalent noise model are analyzed, a noise model of main noise in an integrated ADC system is established, specifically, the influence of the noise on the ADC is analyzed, and the performance of the high-speed high-precision ADC is better estimated.
Drawings
FIG. 1 is a diagram of an integrated ADC total noise equivalent model of the present invention;
FIG. 2 is a block diagram of a time-interleaved pipelined ADC of the present invention;
FIG. 3 is a block diagram of a single-pass pipelined ADC of the present invention;
FIG. 4 is a diagram of a noise equivalent model of a single-path pipelined ADC of the present invention;
FIG. 5 is a simulation result of ADC noise of a single-path pipeline according to the present invention;
FIG. 6 is a diagram of an equivalent model of the noise of an isolation amplifier circuit of the present invention;
FIG. 7 is a simulation result of the noise of the isolation amplifier circuit of the present invention;
FIG. 8 is a diagram of a reference circuit noise equivalent model of the present invention;
FIG. 9 is a simulation result of the noise of the reference circuit of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention; all other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1-9, a noise model circuit of an ADC system based on a time-interleaved pipeline includes a time-interleaved pipeline ADC model, an isolation amplifier noise model, and a reference circuit noise model.
The time interleaving assembly line ADC model mainly comprises a time interleaving circuit and an assembly line ADC; the noise model of the isolation amplifier mainly comprises an operational amplifier and an external feedback structure; the reference circuit noise model is generated during quantization of the reference voltage from the internal structure.
As shown in FIG. 2, the time-interleaved pipelined ADC model (TIADC) uses four single-channel pipelined ADCs (ADCs) with a sampling rate of fs/4 1 ~ADC 4 ) The back end outputs the output result MUX of the 4 sub-channel ADC to the output by the four-channel selection circuit under the control of the clock, so that the sampling rate of the whole time interleaving assembly line ADC model reaches fs, and the sampling rate of the whole system is improved.
Reference channel ADC in fig. 2 5 Is a reference channel ADC with the sampling rate of fs/3, and the reference channel ADC 5 The output result of (2) is provided to a digital background calibration circuit which performs the calibration by comparing the four sub-channel ADCs 1 ~ADC 4 And reference channel ADC 5 Digital signal processing is carried out on the output of the four-channel ADC 1 ~ADC 4 Is used as the output of the whole system. CK is the clock of the whole TIADC system, CK 1-CK 4 are the four-phase clock after CK is divided by four, CK5 is the clock after CK is divided by three, V ip And V in Respectively a positive input end and a negative input end of the whole TIADC system, V refp And V refn A positive reference voltage and a negative reference voltage, respectively.
The pipelined ADC is shown in FIG. 3, where the pre-sample hold circuit SHA inputs the analog signal V at the sampling clock in Sampling is carried out, and when a clock phase is to be maintained, a discretized signal is output to the first-Stage circuit Stage1. Meanwhile, the Stage1 circuit in the sampling clock phase samples the output result of the pre-sampling hold circuit SHA in the holding clock phase, the sub-ADC of the Stage converts the input signal to obtain the D1-bit coarse quantization result of the Stage1 circuit of the first Stage, the D1 is used for carrying out digital input of the sub-DAC of the Stage in the holding clock phase, the subtracting circuit realizes subtraction of the input signal of the Stage and the output of the sub-DAC, and the obtained difference value is the same as the working principle of the Stage2-Stage of the gain amplifier Stage.
As shown in fig. 4, the pipeline conversion structure of each stage includes a sub-MDAC and a sub-ADC, and the present invention takes noise from the sampling circuit and the operational amplifier into consideration. In the sampling circuit, the sampling circuit can be equivalent to a switched capacitor circuit, and comprises a sampling capacitor Cs1, a feedback capacitor Cf1 and an operational amplifier OTA, because of the influence of on-resistance of a switch, thermal noise voltages can exist on the sampling capacitor and the feedback capacitor, and the equivalent noise source voltages accumulated on the sampling capacitor are obtained according to a transistor noise model working in a linear region and an uncorrelated noise superposition principle:
（1）；
the first order approximation transfer function is: v
（2）；
In the method, in the process of the invention,kis a boltzmann constant,Tthe temperature is set to be the absolute temperature,C s1 for the capacitance value of the sampling capacitance Cs1,gds1 is the small signal admittance of switch S1 in the figure,gds2 is the small signal admittance of switch S2 in the figure.
Thus, the integrated noise voltage on the sampling capacitance is:
（3）；
in the method, in the process of the invention,C s1 is the capacitance value of the sampling capacitance Cs 1.
Similarly, the integral noise on the feedback capacitance is:
according to the uncorrelated noise superposition principle, the equivalent noise of the sample hold circuit is:
（5）；
the equation shows that the integrated noise voltage on the sampling capacitor and the feedback capacitor is independent of the on-resistance of the switch, and depends only on the magnitude of the capacitance value. This part of the noise voltage affects the sampling accuracy of the stages following the pipelined ADC by charge transfer.
The equivalent noise voltage of the operational amplifier OTA is calculated according to the following equation:
（6）；
for the noise power spectral density of the operational amplifier,G n for the purpose of the noise gain,BW n is the equivalent bandwidth of the noise. The operational amplifier OTA is approximated as a single-pole operational amplifier, and the power spectral density of the operational amplifier is as follows:
（7）；
in the method, in the process of the invention,g m is the transconductance of the field effect transistor;
the gain of noise can be expressed as:
（8）；
for a single-pole operational amplifier, the equivalent bandwidth of the noise is polarOf point frequencyThe equivalent noise bandwidth is:
（9）；
in the method, in the process of the invention,C c1 for the miller compensation capacitance of the operational amplifier,. Noise at the output end and the input end of the amplifying phase operational amplifier are respectively:
（10）；
（11）；
n f the noise factor is determined by the structure of the operational amplifier,γas the noise figure of the transistor,g m1 is the transconductance of the input tube of the amplifier. Noise and miller capacitance values of operational amplifiersC c1 In inverse proportion, the larger the Miller capacitance value is, the smaller the equivalent thermal noise is, but the gain bandwidth product of the operational amplifier is reduced, so that the value of the Miller capacitance needs to be balanced.
Because the actual circuit is a differential input, according to the uncorrelated noise superposition principle, the total thermal noise of the first-stage circuit is 2 times of that of the single-ended thermal noise, so the thermal noise of the first-stage circuit can be known by the following formula:
（12）；
according to the deduction of the thermal noise and corresponding parameters, the equivalent noise voltage of the first stage circuit can be obtained as follows:
（13）；
the root mean square effective value is 95.9uV.rmsThe integral noise of the ADC is obtained 287.7 by theoretical derivationuV.rms。The simulation result shown in FIG. 5 is single-ended equivalent noise, so the equivalent noise of the first stage circuit of the fully differential structure is 84.42uV.rmsThe actual noise of the ADC was 253.26uV.rms。
The noise model of the isolation amplifier is shown in fig. 6, and includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, and an operational amplifier, and the bandwidth is calculated as follows. The bandwidth of the feedback network is 1.33MHz, the bandwidth of the RC filter is 5.81MHz, the gain bandwidth product of the amplifier is limited to 1.82MHz, and the three parts together form a filter.
（14）；
（15）；
（16）；
（17）；
In the method, in the process of the invention,f c_feedback for the purpose of feeding back the bandwidth of the network,f c_ChargeBucket for the bandwidth of the RC-filter,Gainin order for the gain of the amplifier to be,f c_AMP for the gain bandwidth of the amplifier,GBWfor the gain-bandwidth product of the amplifier,C 1 is of the shape of,C 2 For the capacitance values of the feedback capacitance and the filter capacitance,R 1 、R 2 、R 3 the values of the resistors R1, R2 and R3 are respectively, and the filter is approximated to a second-order filter with a cutoff frequency of 1.33MHz due to the very close cutoff points of the operational amplifier and the feedback network, so that the calculation is simplified, and the noise band is calculated by considering that the position of each node gives more accurate resultsWide width ofBW n 1.62MHz.
（18）；
（19）；
In the method, in the process of the invention,f c_system for the cut-off frequency of the filter,K n is a coefficient of a second order filter.
In the calculation of feedback network noise, two resistors (R1, R2) are equivalent to a feedback resistor network by being connected in parallel, and then the thermal noise is calculated using the resistor, boltzmann constant, and kelvin temperature.
（20）
（21）；
In the method, in the process of the invention,kis a boltzmann constant,R eq in order to be an equivalent resistance,E nReq the noise spectrum density which is the equivalent resistance,T k is Kelvin temperature;
combining the feedback network noise with the operational amplifier noise, multiplying the total noise by the square root of the bandwidth, converting the spectral density to an input noise of 17.88uV.rms. Finally, multiplying this noise by the noise gain gives a noise of 196.7 for the isolation amplifieruV.rms。
（22）；
（23）；
（24）；
In the method, in the process of the invention,E n in order to isolate the noise spectrum of the amplifier,E n_in_Total for an isolated amplifier noise spectrum within the bandwidth,E n_Total in order to isolate the total noise voltage of the amplifier,E nAMP is the noise spectrum of the operational amplifier.
Simulation results of the isolation amplifier noise model are shown in fig. 7. Noise simulation requires that the amplifier be in a linear operating region to ensure correct results. The simulated noise spectral density and the integrated noise curve are seen on the right after simulation. The end of the total noise curve tends to flatten out, with a final convergence value of 174.83uV.rms. The total noise of the isolation amplifier was calculated to be 196.7uV.rms. The difference between these two numbers is because the simulation considers all nodes in the circuit more accurately.
Reference circuit noise model as shown in fig. 8, this model provides a voltage reference standard for the analog-to-digital converter quantization process.NBit ofADCDividing the reference voltage into 2 at the time of quantization N And quantifying the measured signal voltage.
Reference voltage noise is an additive process to noise generated by quantization. For input, when the voltage value of the input signal is higher, the total noise andADCthe direct current input voltage is proportional, and the reference voltage has a larger influence on the quantization process. Because ofV in /V REF The ratio increases so that when the ADC uses full scale input, its noise dominates the overall system noise. When the input voltage reaches the measurement fullness, the influence of the reference voltage source noise on the quantization process is maximized, but as long as it is still much smaller than 1/2LSBThe noise calculation is negligible and the simulation results are shown in fig. 9.
The equivalent noise of the invention is:
（25）；
calculating the SNR of the present invention requires a full range of rms noise input voltage ranges. The full scale range of the invention is 1.2V, and the full scale range corresponds to peak value input and needs to be converted into an effective value for calculation, and the following formula is shown in the specification:
（26）；
therefore, the signal-to-noise ratio of the invention is:
（27）；
in the method, in the process of the invention,V nADC is the total root mean square noise of the ADC,V nREF is the total root mean square noise of the reference circuit,E nAMP in order to isolate the overall root mean square noise of the amplifier,V FSR_ppk for the peak value of the full-scale input voltage,V FSR_rms for an effective value of the full scale input voltage,V ntotal equivalent noise of the system;
TABLE 1 data results for theoretical and actual models of the invention
As shown in Table 1, the present invention not only includes a pipelined ADC, but also incorporates a noise model of the reference circuit and isolation amplifier, the pipelined ADC used by the present invention has a full-width signal-to-noise ratio of 54.6dB and a system model has a signal-to-noise ratio of 61.6dB, because adding the isolation amplifier reduces noise in the signal path from the ground loop, thereby reducing the overall noise of the ADC system.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. A noise model circuit based on a time interleaving pipelined ADC system is characterized by comprising an isolation amplifier noise model, a reference circuit noise model and a time interleaving pipelined ADC model;
the noise model of the isolation amplifier is composed of an operational amplifier and an external feedback structure, and is used for processing thermal noise of the operational amplifier and a feedback network thereof;
the reference circuit noise model is used for processing quantization noise generated by the reference circuit;
the time interleaving assembly line ADC model comprises a time interleaving circuit and an assembly line ADC, and is used for processing noise generated by a sampling structure and an operational amplifier;
the pipelined ADC comprises a clock generation circuit, a pipelined conversion structure, a delay alignment register array and a digital correction circuit, and the total noise model of the first-stage pipelined structure is calculated by carrying out noise analysis on the first-stage pipelined structure.
2. The time interleaving pipeline ADC system noise model circuit according to claim 1, wherein the clock generating circuit is configured to generate two sets of phase non-overlapping clock control signals, control the multistage pipeline of the pipeline conversion structure, and make the circuits work alternately with different timings;
the pipeline conversion structure is used for dividing the conversion operation into multiple stages, converting each stage to obtain a positioned digital output bit to form a pipeline working mode, and mainly processing thermal noise generated by a sampling hold circuit and an operational amplifier of each stage;
the delay alignment register array adjusts and synchronizes output data of each level of pipeline conversion structure;
the digital correction circuit corrects the conversion result by using the redundancy bits.
3. The time-interleaved pipelined ADC system noise model circuit of claim 1, wherein the pipelined conversion structure of each stage comprises a sub-MDAC and a sub-ADC; the MDAC comprises a sample hold circuit and a sub-DAC for realizing digital-to-analog conversion, subtraction, amplification and sample hold functions.
4. The noise model circuit of the ADC system based on the time interleaving pipeline as claimed in claim 3, wherein the sample hold circuit is used for collecting analog signals input by the ADC circuit, and keeping sampling values until the next clock period comes, and then supplying the sampling values to a post-stage circuit for quantization processing; the sub-DAC is used for converting digital output codes in the pipeline conversion structure of each stage into analog signals.
5. A time-interleaved pipelined ADC system noise model circuit according to claim 3, wherein the sample-and-hold circuit is equivalently a switched capacitor circuit, and the switched capacitor circuit comprises a sampling capacitor Cs1, a feedback capacitor Cf1, an operational amplifier OTA, and the equivalent noise voltage of the sample-and-hold circuit is:
in the middle ofkIs a boltzmann constant,Tthe temperature is set to be the absolute temperature,C s1 for the capacitance value of the sampling capacitance Cs1,C f 1 the capacitance value of the feedback capacitor Cf 1;
the equivalent noise voltage of the operational amplifier OTA is:
in the method, in the process of the invention,n f is a noise factor, is determined by the structure of the operational amplifier,C c1 the capacitance value is compensated for the miller of the operational amplifier,，kis a boltzmann constant,Tabsolute temperature.
6. The time-interleaved pipelined ADC system noise model circuit of claim 1, wherein the pipelined ADC comprises a plurality of pipelined stage circuits, the first stage circuit equivalent noise being calculated by:
in the method, in the process of the invention,n f the noise factor is determined by the structure of the operational amplifier, gamma is the noise figure of the transistor,C c1 the capacitance value is compensated for the miller of the operational amplifier,，C s1 for the capacitance value of the sampling capacitance Cs1,C f 1 for the capacitance value of the feedback capacitance Cf1,kis a boltzmann constant,Tabsolute temperature>Is the equivalent noise voltage of the operational amplifier.
7. The time-interleaved pipelined ADC system noise model circuit of claim 1, wherein the equivalent output noise of the isolation amplifier noise model is:
in the method, in the process of the invention,Gainr is the gain of the amplifier 1 、R 2 Respectively is a resistor R 1 Resistance R 2 Is used for the resistance value of the (a),BW n for noise bandwidth, k is the boltzmann constant,R eq is a resistor R 1 Resistance R 2 Is used for the control of the resistance of the capacitor,T k in order to achieve a temperature of kelvin,E n_in_Total for noise voltages of the isolation circuits within the bandwidth,E n_Total in order to isolate the total noise voltage of the circuit,E nReq is the noise voltage of the equivalent resistance,E nAMP to isolate the operational amplifier from noise.
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