CN113839675B - Pipelined analog-to-digital converter based on non-50% duty cycle sampling clock - Google Patents
Pipelined analog-to-digital converter based on non-50% duty cycle sampling clock Download PDFInfo
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Abstract
The invention discloses a pipelined analog-to-digital converter based on a sampling clock with a duty ratio other than 50%, wherein the sum of duty ratios of two-phase clocks phi 1 and phi 2 is 1, and the power consumption current I of the ith sub-stage in the previous m-1 sub-stages D Adding the power consumption of the first m-1 sub-stages to obtain the total power consumption of the pipelined analog-to-digital converter, so as to obtain the relation between normalized power consumption and phi 2 duty ratio, the phi 2 duty ratio value when the normalized power consumption is the lowest and the phi 1 duty ratio value when the normalized power consumption is the lowest, and further obtain the duty ratio corresponding to the sampling clock when the pipelined analog-to-digital converter is the lowest. The invention does not depend on the manufacturing process, does not influence the existing sampling rate and resolution index, is compatible with the existing low-power-consumption design technology, does not need to change the internal architecture of the pipelined analog-to-digital converter, and can reduce the power consumption of the whole circuit by changing the duty ratio of the input sampling clock with tiny power consumption and area cost on the basis of the existing design.
Description
Technical Field
The invention relates to the technical field of analog-to-digital converters, in particular to a pipelined analog-to-digital converter based on a sampling clock with a duty ratio other than 50%.
Background
Analog-to-digital converters are core circuit modules widely used in the fields of communication, radars and the like, and in recent years, as communication bandwidths are larger and larger, data throughput rates are higher and higher, and the analog-to-digital converters are moving towards higher speeds and higher resolutions. Common analog-to-digital converter implementations are successive approximation (successive approximation register, SAR-ADC), oversampling Delta-Sigma ADC, pipelined (Pipeline ADC), etc. Among them, pipeline analog-to-digital converter has been an important place in the field of analog-to-digital converter design because of its easy implementation of high bandwidth and high resolution.
The greatest advantage of pipelined analog-to-digital converters is that the sampling rate is independent of the resolution, and higher resolution can be obtained by increasing the number of stages, while the sampling rate of each sub-stage remains unchanged. However, this architecture is also evident in that the sub-dac, subtractor and amplifier in each stage are typically implemented as a capacitive-add operational amplifier, the switches are controlled by two non-overlapping clocks Φ1 and Φ2, and Φ1 and Φ2 each occupy 50% duty cycle in conventional designs, and in high-sampling-rate, high-resolution pipelined analog-to-digital converters, the requirements of the first few sub-stage circuits on the gain bandwidth product ωu of the operational amplifier are very high, often consuming significant power consumption.
In view of the above problems, a new pipelined analog-to-digital converter based on a sampling clock with a duty cycle other than 50% is needed, which is not dependent on the manufacturing process, does not affect the existing sampling rate and resolution index, is compatible with the existing low-power design technology, does not need to change the internal architecture of the pipelined analog-to-digital converter, and can further reduce the power consumption of the whole circuit by changing the duty cycle of the input sampling clock with small power consumption and area cost only on the basis of the existing design.
Disclosure of Invention
It is an object of the present invention to provide a pipelined analog-to-digital converter based on a sampling clock with a duty cycle other than 50% to solve the above-mentioned problems.
In order to solve the technical problems, the invention provides the following technical scheme: a pipelined analog-to-digital converter based on a non-50% duty cycle sampling clock, comprising: m sub-stages and a digital correction module, m is a positive integer, each sub-stage except the m sub-stage includes: a sample hold circuit unit, a sub-digital-to-analog converter unit, a subtracter unit and an amplifier unit,
the sample-hold circuit unit is used for inputting the signal V to the sub-stage when the rising edge of the sampling clock arrives each time in Sampling and keeping the result of each sampling until the next sampling;
the sub-analog-digital converter unit is used for quantizing the result of each sampling and outputting an n-bit digital signal, wherein n bits are recorded as n-bits, and n is a positive number;
the sub-digital-to-analog converter unit is used for converting the n-bits digital signal into an analog signal and subtracting V from the analog signal through the subtracter unit in Obtaining a residual error signal;
the amplifier unit is used for amplifying the residual error signal by 2 (n-1) times to obtain an output signal V out As an input signal of the next sub-stage, the mth sub-stage does not need to amplify the residual error signal by an amplifier unit.
Further, the input signal V of the first sub-stage in For inputting analog signals, each sub-stage of the pipelined analog-to-digital converter simultaneously and parallelly works under the control of a sampling clock, wherein the sampling clock is used for providing clock signals for the pipelined analog-to-digital converter, the input analog signals are quantized step by step from a first sub-stage to an mth sub-stage, the quantization result of each sub-stage is calculated by a digital correction module, and finally, N bits of digital signals are output, and the N bits are recorded as N-bits;
the sub-digital-to-analog converter unit, the subtractor unit and the amplifier unit in each sub-stage except the m-th sub-stage are realized by a switched capacitor circuit, and the input signal of the switched capacitor circuit is marked as V in 1, the switched capacitor circuit comprises a first capacitor C 1 A second capacitor C 2 And an operational amplifier for controlling the first capacitor C by the first sampling clock and the second sampling clock 1 A second capacitor C 2 The connection relation of the two capacitors is that the first sampling clock is recorded as phi 1, the second sampling clock is recorded as phi 2, phi 1 and phi 2 are two-phase non-overlapping sampling clocks, the clock periods of phi 1 and phi 2 are both T, T is one sampling clock period of the pipelined analog-to-digital converter, the duty ratios of phi 1 and phi 2 are both between 0 and 1, the sum of the duty ratios of phi 1 and phi 2 is 1, and the duty ratios of phi 1 and phi 2 are adjusted to enable the power consumption of the pipelined analog-to-digital converter to be minimum.
Further, the switch capacitor circuit also comprises a first phi 1 switch, a second phi 1 switch, a third phi 1 switch, a first phi 2 switch, a second phi 2 switch and a three-input gating device,
the V is in 1 are respectively connected with the first end of the first phi 1 switch and the first end of the second phi 1 switch, and the second end of the first phi 1 switch is respectively connected with the first capacitor C 1 A first end of a first phi 2 switch is connected with the output end of the operational amplifier, a second end of the first phi 2 switch is connected with the first capacitor C 1 The second end of the third phi 1 switch is connected with the non-inverting input end of the operational amplifier, the second end of the third phi 1 switch is connected with the ground, the second end of the third phi 1 switch is connected with the second capacitor C 2 Is respectively connected with the second end of the second phi 1 switch and the second end of the second phi 2 switch, the second capacitor C 2 The second end of the second phi 2 switch is connected with the first end of the three-input gating device, the second end of the three-input gating device is connected with +Vref, the third end of the three-input gating device is connected with-Vref, the fourth end of the three-input gating device is connected with 0, and the fifth end of the three-input gating device is connected with the sub-analog-digital converter.
Further, the steps of obtaining the duty ratios corresponding to the phi 1 and phi 2 of the minimum power consumption of the pipelined analog-to-digital converter are as follows:
s1, obtaining an output signal V of an output end of an operational amplifier when clock signals corresponding to phi 1 and phi 2 of a switched capacitor circuit are in different states out V is obtained out The formula of variation with sampling time t and analyzing the obtained V out The variation formula along with the sampling time t obtains the product omega of the error epsilon of the output signal and the gain bandwidth of the operational amplifier u And the relation between the sampling time t;
s2, obtaining a gain bandwidth product omega according to the error epsilon of the output signal obtained in S1 and the condition which should be satisfied and related to the number of unquantized bits after the sub-level u Conditions to be satisfied;
s3, obtaining gain bandwidth product omega u ＝2π·g m /C L The g is m Is the transconductance value of the operational amplifier, C L For the load capacitance, the C L Is of the same size as the first capacitance C 1 And the circuit load of the next sub-stage is related and is according to g m And operational amplifier power consumption current I D Obtain the relation of gain bandwidth product and I D And according to the gain bandwidth product and the power consumption current I D The relation of (2) and the gain bandwidth product omega in S2 u The power consumption current I of the ith sub-level in the first m-1 sub-levels is obtained under the condition that the power consumption current I needs to be met D Is an expression of (2);
s4, the power consumption current I of the ith sub-level in the previous m-1 sub-levels in the S3 is 1 according to the sum of the duty ratios of phi 1 and phi 2 D The method comprises the steps of adding the power consumption of the first m-1 sub-stages to obtain the total power consumption of the pipelined analog-to-digital converter, wherein the sampling time t of each sub-stage is equal to the product of the duty ratio of the sampling clock of the sub-stage and the period of the sampling clock, the duty ratio of phi 2 is adjusted, so that the relation between normalized power consumption and the duty ratio of phi 2, the duty ratio value of phi 2 when the normalized power consumption is the lowest and the duty ratio value of phi 1 when the normalized power consumption is the lowest are obtained, the duty ratio corresponding to the sampling clock when the pipelined analog-to-digital converter is the lowest is obtained, and the normalized power consumption is the result of normalized processing by taking the total power consumption value when the duty ratio of phi 2 is 0.5 as a reference.
Furthermore, in the switched capacitor circuit of S1, the switched capacitor circuit is divided into a sampling mode and a feedback operation mode according to different signal states corresponding to phi 1 and phi 2,
when the signal state corresponding to phi 1 is high, the switched capacitor circuit is in a sampling mode, the first phi 1 switch, the second phi 1 switch and the third phi 1 switch are closed, the first phi 2 switch and the second phi 2 switch are opened, and at the moment, two input ends of the operational amplifier are connected with common mode voltage, V in 1 is sampled to a first capacitance C 1 And a second capacitor C 2 Applying;
when the signal state corresponding to phi 2 is high, the switched capacitor circuit is in a feedback operation mode, and the output of the operational amplifier passes through the first stageA capacitor C 1 And a second capacitor C 2 The feedback is connected to the negative input terminal of the operational amplifier, the second capacitor C 2 The first terminal is input +Vref, 0 or-Vref, and is specifically determined by the digital signal output by the sub-analog-to-digital converter.
Further, when the switched capacitor circuit is in a feedback operation mode,
output signal V of operational amplifier output end out Can be expressed as:
the V is x Is +Vref, 0 or-Vref, V x Depending on the n-bits digital signal output by the sub-analog-to-digital converter, said A cl = (first capacitance C 1 +second capacitance C 2 ) First capacitor C 1 ＝1/β＝2^(n-1)，A cl The ideal closed loop gain of the operational amplifier is the voltage amplification factor when the amplifying circuit with negative feedback is formed, n is the quantized bit number of the sub-stage, beta is the loop feedback coefficient, V sub Is the residual error signal, namely the equivalent input signal of the switched capacitor circuit at the moment;
approximating the operational amplifier as a single-pole system, then V out The formula of change with sampling time t:
in the feedback operation mode, the switched capacitor circuit must output a result close enough to an ideal value in a period when the corresponding sampling clock is at a high level, where the ideal value is a value when the error epsilon of the output signal is equal to 0, and the error epsilon of the output signal needs to satisfy the following conditions:
the N is r For the number of bits not yet quantized after this sub-level,
feedback coefficient β=1/(2≡1)), where n is the number of quantization bits of the present sub-level.
Further, the S2 is according toOmega, omega u ＝f u *2 pi, f is u Is the gain bandwidth product omega u The corresponding frequency is obtained f u The conditions to be satisfied are:
in each sub-stage of the pipelined analog-to-digital converter, wherein the first m-1 sub-stages comprise operational amplifiers, the mth sub-stage only quantizes its input signal, the gain-bandwidth product f of the ith sub-stage of the first m-1 sub-stages u i conditions to be satisfied:
the N is r i is the number of bits which are not quantized in the ith sub-level in the previous m-1 sub-levels, βi is the loop feedback coefficient of the ith sub-level in the previous m-1 sub-levels, and ti is the feedback operation time corresponding to the ith sub-level in the previous m-1 sub-levels.
Further, g in S3 m And power consumption current I D The relation of (2) is thatMu is carrier mobility, C ox For gate oxide capacitance, μ and C ox Are all technological parameters with fixed values, W and L are the gate width and the gate length of transconductance MOS in the operational amplifier, and the I is given that W and L are fixed and unchanged D Is regulated by changing the overdrive voltage Vdsat of the MOS; c (C) L Is of the same size as the first capacitance C 1 And the load of the next sub-stage circuit, when W and L of transconductance MOS in each sub-stage operational amplifier are fixed, each sub-stage operatesC in a computing amplifier L The same is also achieved, and the frequency f corresponding to the gain bandwidth product can be obtained u And I D The relation of (2) is:
the k is a constant, and the power consumption current I D And f u Is proportional to the square of the gain bandwidth product in the ith sub-stage of the first m-1 sub-stages, comprehensively considering the corresponding frequency f u I is the condition to be satisfied and the frequency and I corresponding to the gain bandwidth product D The relation of the power consumption current I of the ith sub-stage in m-1 sub-stages before the pipelined analog-to-digital converter can be obtained D Expression of i
Further, in the pipelined analog-to-digital converter, the switched capacitor circuits in each sub-stage circuit are alternately in a sampling mode and a feedback operation mode,
namely, when phi 1 is high level, the first sub-stage and the third sub-stage …, namely the 2j-1 sub-stage, the switched capacitor circuit is in a sampling mode; when phi 2 is high level, the first sub-stage and the third sub-stage …, namely the 2j-1 sub-stage, are in a feedback operation mode;
when phi 1 is high level, the second and fourth sub-stages …, 2i sub-stage are in feedback operation mode; the second and fourth sub-stages …, 2i sub-stage are in the sampling mode when phi 2 is high;
the j and i are positive integers,
the sum of the high level time of phi 1 and phi 2 is T, T is a fixed value under a specific sampling frequency, and changing the duty ratio of phi 2 is to change the sampling time ti of each sub-stage, thereby changing the power consumption of each sub-stage.
Further, the normalization processing method comprises the following steps: taking the total power consumption value when the duty ratio of phi 2 is 0.5 as a reference, dividing the total power consumption when the duty ratio of phi 2 is equal to other values between 0 and 1 by the total power consumption value when the duty ratio of phi 2 is 0.5, and obtaining the normalized power consumption corresponding to the duty ratio of phi 2.
Compared with the prior art, the invention has the following beneficial effects: the invention does not depend on the manufacturing process, does not influence the existing sampling rate and resolution index, is compatible with the existing low-power-consumption design technology, does not need to change the internal architecture of the pipelined analog-to-digital converter, and can further reduce the power consumption of the whole circuit by changing the duty ratio of the input sampling clock with tiny power consumption and area cost on the basis of the existing design.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a schematic diagram of the top-level architecture of a pipelined analog-to-digital converter of the present invention based on a non-50% duty cycle sampling clock;
FIG. 2 is a schematic diagram of the internal structure of each sub-stage of the pipelined analog-to-digital converter of the present invention based on a non-50% duty cycle sampling clock;
FIG. 3 is a schematic diagram of the switched capacitor circuit of each sub-stage of the pipelined analog-to-digital converter of the present invention based on a non-50% duty cycle sampling clock;
FIG. 4 is a schematic diagram of the timing of 50% duty cycles of each of φ 1 and φ 2 in a conventional design of a pipelined analog-to-digital converter based on a non-50% duty cycle sampling clock in accordance with the present invention;
FIG. 5 is a schematic diagram of a switch capacitor circuit of a pipelined analog-to-digital converter in sampling mode based on a non-50% duty cycle sampling clock;
FIG. 6 is a schematic diagram of a switch capacitor circuit of a pipelined analog-to-digital converter with a non-50% duty cycle sampling clock in a feedback mode of operation;
FIG. 7 is a schematic diagram of the relationship between normalized power consumption and duty cycle of φ 2 in a pipelined analog-to-digital converter of the present invention based on a non-50% duty cycle sampling clock;
FIG. 8 is the first 7N sub-stages of a common 8-stage 3-2-2-2-2-2-2-2 low power pipeline architecture for a non-50% duty cycle sampling clock-based pipelined analog-to-digital converter of the present invention r Schematic representation of the values of β and t.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-8, the present invention provides the following technical solutions: a pipelined analog-to-digital converter based on a non-50% duty cycle sampling clock, comprising: m sub-stages and a digital correction module, m is a positive integer, each sub-stage except the m sub-stage includes: a sample hold circuit unit, a sub-digital-to-analog converter unit, a subtracter unit and an amplifier unit,
the sample-hold circuit unit is used for inputting the signal V to the sub-stage when the rising edge of the sampling clock arrives each time in Sampling and keeping the result of each sampling until the next sampling;
the sub-analog-digital converter unit is used for quantizing the result of each sampling and outputting an n-bit digital signal, wherein n bits are recorded as n-bits, and n is a positive number;
the sub-digital-to-analog converter unit is used for converting the n-bits digital signal into an analog signal and subtracting V from the analog signal through the subtracter unit in Obtaining a residual error signal;
the amplifier unit is used for amplifying the residual error signal by 2 (n-1) times to obtain an output signal V out As an input signal of the next sub-stage, the mth sub-stage does not need to amplify the residual error signal by an amplifier unit.
Input signal V of the first sub-stage in For inputting analog signals, each sub-stage of the pipelined analog-to-digital converter simultaneously and parallelly works under the control of a sampling clock, wherein the sampling clock is used for providing clock signals for the pipelined analog-to-digital converter, the input analog signals are quantized step by step from a first sub-stage to an mth sub-stage, the quantization result of each sub-stage is calculated by a digital correction module, and finally, N bits of digital signals are output, and the N bits are recorded as N-bits;
the sub-digital-to-analog converter unit, the subtractor unit and the amplifier unit in each sub-stage except the m-th sub-stage are realized by a switched capacitor circuit, and the input signal of the switched capacitor circuit is marked as V in 1, the switched capacitor circuit comprises a first capacitor C 1 A second capacitor C 2 And an operational amplifier for controlling the first capacitor C by the first sampling clock and the second sampling clock 1 A second capacitor C 2 The connection relation of the two capacitors is that the first sampling clock is recorded as phi 1, the second sampling clock is recorded as phi 2, phi 1 and phi 2 are two-phase non-overlapping sampling clocks, the clock periods of phi 1 and phi 2 are both T, T is one sampling clock period of the pipelined analog-to-digital converter, the duty ratios of phi 1 and phi 2 are both between 0 and 1, the sum of the duty ratios of phi 1 and phi 2 is 1, and the duty ratios of phi 1 and phi 2 are adjusted to enable the power consumption of the pipelined analog-to-digital converter to be minimum.
The switch capacitor circuit also comprises a first phi 1 switch, a second phi 1 switch, a third phi 1 switch, a first phi 2 switch, a second phi 2 switch and a three-input gating device,
the V is in 1 are respectively connected with the first end of the first phi 1 switch and the first end of the second phi 1 switch, and the second end of the first phi 1 switch is respectively connected with the first capacitor C 1 A first end of a first phi 2 switch is connected with the output end of the operational amplifier, a second end of the first phi 2 switch is connected with the first capacitor C 1 The second end of the third phi 1 switch is connected with the non-inverting input end of the operational amplifier, the second end of the third phi 1 switch is connected with the ground, the second end of the third phi 1 switch is connected with the second capacitor C 2 Respectively with the second end of (a)The second end of the phi 1 switch is connected with the second end of the second phi 2 switch, and the second capacitor C 2 The second end of the second phi 2 switch is connected with the first end of the three-input gating device, the second end of the three-input gating device is connected with +Vref, the third end of the three-input gating device is connected with-Vref, the fourth end of the three-input gating device is connected with 0, and the fifth end of the three-input gating device is connected with the sub-analog-digital converter.
The steps of the duty ratios corresponding to phi 1 and phi 2 when the minimum power consumption of the pipelined analog-to-digital converter is obtained are as follows:
s1, obtaining an output signal V of an output end of an operational amplifier when clock signals corresponding to phi 1 and phi 2 of a switched capacitor circuit are in different states out V is obtained out The formula of variation with sampling time t and analyzing the obtained V out The variation formula along with the sampling time t obtains the product omega of the error epsilon of the output signal and the gain bandwidth of the operational amplifier u And the relation between the sampling time t;
s2, obtaining a gain bandwidth product omega according to the error epsilon of the output signal obtained in S1 and the condition which should be satisfied and related to the number of unquantized bits after the sub-level u Conditions to be satisfied;
s3, obtaining gain bandwidth product omega u ＝2π·g m /C L The g is m Is the transconductance value of the operational amplifier, C L For the load capacitance, the C L Is of the same size as the first capacitance C 1 And the circuit load of the next sub-stage is related and is according to g m And operational amplifier power consumption current I D Obtain the relation of gain bandwidth product and I D And according to the gain bandwidth product and the power consumption current I D The relation of (2) and the gain bandwidth product omega in S2 u The power consumption current I of the ith sub-level in the first m-1 sub-levels is obtained under the condition that the power consumption current I needs to be met D Is an expression of (2);
s4, the power consumption current I of the ith sub-level in the previous m-1 sub-levels in the S3 is 1 according to the sum of the duty ratios of phi 1 and phi 2 D Is added to the power consumption of the first m-1 sub-levelAnd (3) the total power consumption of the pipelined analog-to-digital converter is obtained, wherein the sampling time t of each sub-stage is equal to the product of the duty cycle of the sub-stage sampling clock and the sampling clock period, the duty cycle of phi 2 is adjusted, so that the relation between the normalized power consumption and the duty cycle of phi 2, the duty cycle value of phi 2 when the normalized power consumption is the lowest and the duty cycle value of phi 1 when the normalized power consumption is the lowest are obtained, and the normalized power consumption is the result of normalization processing by taking the total power consumption value of phi 2 when the duty cycle of phi 2 is 0.5 as a reference.
In the switch capacitor circuit of S1, the switch capacitor circuit is divided into a sampling mode and a feedback operation mode according to different signal states corresponding to phi 1 and phi 2,
when the signal state corresponding to phi 1 is high, the switched capacitor circuit is in a sampling mode, the first phi 1 switch, the second phi 1 switch and the third phi 1 switch are closed, the first phi 2 switch and the second phi 2 switch are opened, and at the moment, two input ends of the operational amplifier are connected with common mode voltage, V in 1 is sampled to a first capacitance C 1 And a second capacitor C 2 Applying;
when the signal state corresponding to phi 2 is high, the switched capacitor circuit is in a feedback operation mode, and the operational amplifier outputs through the first capacitor C 1 And a second capacitor C 2 The feedback is connected to the negative input terminal of the operational amplifier, the second capacitor C 2 The first terminal is input +Vref, 0 or-Vref, and is specifically determined by the digital signal output by the sub-analog-to-digital converter.
When the switched capacitor circuit is in a feedback mode of operation,
output signal V of operational amplifier output end out Can be expressed as:
the V is x Is +Vref, 0 or-Vref, V x Depending on the n-bits digital signal output by the sub-analog-to-digital converter, said A cl = (first capacitance C 1 +second capacitance C 2 ) First capacitor C 1 ＝1/β＝2^(n-1)，A cl The ideal closed loop gain of the operational amplifier is the voltage amplification factor when the amplifying circuit with negative feedback is formed, n is the quantized bit number of the sub-stage, beta is the loop feedback coefficient, V sub Is the residual error signal, namely the equivalent input signal of the switched capacitor circuit at the moment;
approximating the operational amplifier as a single-pole system, then V out The formula of change with sampling time t:
in the feedback operation mode, the switched capacitor circuit must output a result close enough to an ideal value in a period when the corresponding sampling clock is at a high level, where the ideal value is a value when the error epsilon of the output signal is equal to 0, and the error epsilon of the output signal needs to satisfy the following conditions:
The N is r For the number of bits not yet quantized after this sub-level,
feedback coefficient β=1/(2≡1)), where n is the number of quantization bits of the present sub-level.
Said S2 is according toOmega, omega u ＝f u *2 pi, f is u Is the gain bandwidth product omega u The corresponding frequency is obtained f u The conditions to be satisfied are:
in each sub-stage of a pipelined analog-to-digital converter, wherein the first m-1 sub-stages comprise operational amplifiers, the m-th sub-stage only performs the amount of the input signalThe gain bandwidth product f of the ith sub-stage of the first m-1 sub-stages u i conditions to be satisfied:
the N is r i is the number of bits which are not quantized in the ith sub-level in the previous m-1 sub-levels, βi is the loop feedback coefficient of the ith sub-level in the previous m-1 sub-levels, and ti is the feedback operation time corresponding to the ith sub-level in the previous m-1 sub-levels.
G in the S3 m And power consumption current I D The relation of (2) is thatMu is carrier mobility, C ox For gate oxide capacitance, μ and C ox Are all technological parameters with fixed values, W and L are the gate width and the gate length of transconductance MOS in the operational amplifier, and the I is given that W and L are fixed and unchanged D Is regulated by changing the overdrive voltage Vdsat of the MOS; c (C) L Is of the same size as the first capacitance C 1 And the load of the next sub-stage circuit is related, when W and L of transconductance MOS in each sub-stage operational amplifier are fixed, C in each sub-stage operational amplifier L The same is also achieved, and the frequency f corresponding to the gain bandwidth product can be obtained u And I D The relation of (2) is:
the k is a constant, and the power consumption current I D And f u Is proportional to the square of the gain bandwidth product in the ith sub-stage of the first m-1 sub-stages, comprehensively considering the corresponding frequency f u I is the condition to be satisfied and the frequency and I corresponding to the gain bandwidth product D The relation of the power consumption current I of the ith sub-stage in m-1 sub-stages before the pipelined analog-to-digital converter can be obtained D Expression of i
In the pipelined analog-to-digital converter, the switched capacitor circuits in each sub-stage circuit are alternately in a sampling mode and a feedback operation mode,
namely, when phi 1 is high level, the first sub-stage and the third sub-stage …, namely the 2j-1 sub-stage, the switched capacitor circuit is in a sampling mode; when phi 2 is high level, the first sub-stage and the third sub-stage …, namely the 2j-1 sub-stage, are in a feedback operation mode;
when phi 1 is high level, the second and fourth sub-stages …, 2i sub-stage are in feedback operation mode; the second and fourth sub-stages …, 2i sub-stage are in the sampling mode when phi 2 is high;
the j and i are positive integers,
the sum of the high level time of phi 1 and phi 2 is T, T is a fixed value under a specific sampling frequency, and changing the duty ratio of phi 2 is to change the sampling time ti of each sub-stage, thereby changing the power consumption of each sub-stage.
The normalization processing method comprises the following steps: taking the total power consumption value when the duty ratio of phi 2 is 0.5 as a reference, dividing the total power consumption when the duty ratio of phi 2 is equal to other values between 0 and 1 by the total power consumption value when the duty ratio of phi 2 is 0.5, and obtaining the normalized power consumption corresponding to the duty ratio of phi 2.
The top layer structure of the pipelined analog-to-digital converter is shown in fig. 1 and consists of m sub-stages and a digital correction module (Digital Error Correction), wherein the internal structure of each sub-stage is shown in fig. 2 and consists of a sample-hold amplifier (SHA), a sub-digital-to-analog converter (subadc), a sub-digital-to-analog converter (subac), a subtracter and an amplifier.
The operation of each sub-stage comprises the following 4 steps:
first, the sample-hold circuit unit outputs an input signal V in Sampling and keeping the result of each sampling until the next sampling;
the second step, the sub-analog-digital converter unit quantizes the result of each sampling and outputs an n-bits digital signal;
third, the sub-DAC unit converts the n-bits digital signal into an analog signal, which is combined with the held V in Subtracting to obtain Residual error signal (Residual signal);
Fourth, the amplifier unit amplifies the residual error signal by a factor of 2 (n-1), V out As input to the next stage, the above steps are repeated.
Since each sub-stage samples the Signal input from the previous sub-stage (the first sub-stage samples the input Analog Signal), each sub-stage of the pipelined Analog-to-digital converter operates in parallel under the control of the sampling clock in time sequence, and the input Analog Signal (Analog Signal) is quantized step by step from the first sub-stage to the m sub-stage, and the quantization result of each sub-stage is calculated by the digital correction module and then the N-bits digital Signal is finally output.
From the above analysis, it can be seen that the greatest advantage of the pipelined analog-to-digital converter is that the sampling rate is independent of the resolution, and that a higher resolution can be obtained by increasing the number of sub-stages, while the sampling rate of each sub-stage remains unchanged. However, this structural disadvantage is also evident, as follows: as shown in fig. 2, the sub-digital-to-analog converter unit, the subtractor unit and the amplifier unit in each sub-stage are implemented by a switch, a capacitor and an operational amplifier, and taking a 2-bit sub-digital-to-analog converter and a sub-digital-to-analog converter as an example, the specific implementation is shown in fig. 3, in which the switch is controlled by two non-overlapping clocks phi 1 and phi 2, and in the conventional design, phi 1 and phi 2 each occupy 50% of duty cycle, and the time sequence is shown in fig. 4. In practical designs, there is often a small non-overlapping time interval between the falling edge of φ 1 and the rising edge of φ 2 and between the falling edge of φ 2 and the rising edge of φ 1 to eliminate the effect of non-ideal characteristics of the switch, although this difference does not affect the discussion of the present invention in which the timing of φ 1 and φ 2 ignores the non-overlapping time interval. In fig. 4T is one sampling period of the analog-to-digital converter, i.e. the inverse of the sampling clock frequency Fs.
The switched capacitor circuit shown in FIG. 3 is in a sampling mode when φ 1 is high, the first φ 1 switch, the second φ 1 switch and the third φ 1 switch are closed, and the first φ 2 switch is openThe switch and the second phi 2 switch are opened, the circuit is simplified as shown in figure 5, at this time, the two input ends of the operational amplifier are connected with common mode voltage, V in 1 is sampled to a first capacitance C 1 And a second capacitor C 2 Applying; when phi 2 is high, the switched capacitor circuit is in a feedback operation mode, as shown in FIG. 6, in which the op-amp output passes through the first capacitor C 1 And a second capacitor C 2 The feedback is connected to the negative input terminal of the operational amplifier, the second capacitor C 2 The first end inputs +Vref, 0 or-Vref, and is specifically determined by a digital signal output by the sub-analog-digital converter; at this time, the output terminal V of the operational amplifier out Can be expressed as:
wherein V is x Is +Vref, 0 or-Vref, V x Depending on the digital signal output by the sub-A/D converter, A cl = (first capacitance C 1 +second capacitance C 2 ) First capacitor C 1 For this purpose, the ideal closed loop gain of the operational amplifier, n is the number of quantized bits of the present sub-stage, β is the loop feedback coefficient, V sub Is the residual error signal, namely the equivalent input signal of the switched capacitor circuit at the moment;
The analysis is based on the ideal infinity of the gain and bandwidth of the operational amplifier, taking into account the limited operating bandwidth of the actual operational amplifier, the output signal V out The ideal value obtained by (1) gradually approaches with the passage of the sampling time t, and if the operational amplifier is reasonably assumed to be a single-pole system, V out The variation with sampling time t can be expressed as follows:
wherein A is cl Is the ideal closed loop gain, omega of the operational amplifier u Is the gain bandwidth product of the operational amplifier, and beta is the loop feedback coefficient. As can be seen from the above discussion, the switched capacitor circuit operates in feedbackIn the mode, the result that is close enough to the ideal value must be output in the period of high level phi 2, the sampling time is T/2, and the error epsilon of the output signal needs to meet the following conditions in order not to deteriorate the signal-to-noise ratio of the whole analog-to-digital converter as can be seen from fig. 4:
wherein N is r As can be seen from analysis formula (3), in the pipelined analog-to-digital converter, N as the resolution increases, for the number of bits not yet quantized after this sub-stage r Will increase, especially the earlier sub-stage circuits, N r The larger; at high sampling rates, the sampling clock period T will be small; the feedback coefficient β=1/(2≡n-1)), where n is the number of quantization bits of the present stage and n is 2 at the minimum, β is 1/2 at the maximum, and it is impossible to make larger. To sum up, ε is required to satisfy equation (3), but can only be increased by increasing the gain-bandwidth product ω of the operational amplifier u Especially in high sampling rate, high resolution pipelined analog-to-digital converters, the first few sub-stage circuits multiply the operational amplifier gain bandwidth by ω u And often consume significant power.
The pipelined analog-to-digital converter can conveniently improve the resolution by only increasing the number of the sub-stage circuits on the basis that the working frequency of each sub-stage circuit is unchanged, but in the design of high sampling rate and high resolution, the first few sub-stage circuits have high requirements on the gain bandwidth product of the operational amplifier, occupy large power consumption and are not suitable for low-power consumption application scenes. Aiming at the problems, the prior published work always reduces the power consumption by optimizing the quantized bit number n of each sub-stage of the pipelined analog-to-digital converter or improving the structure of an operational amplifier, the invention does not depend on the manufacturing process, does not influence the prior sampling rate and resolution index, is compatible with the prior low-power design technology, does not need to change the internal architecture of the pipelined analog-to-digital converter, and can further reduce the power consumption of the whole circuit by changing the duty ratio of an input sampling clock with tiny power consumption and area cost on the basis of the prior design.
In each sub-stage circuit of the pipelined analog-to-digital converter, the more the preceding sub-stage is, the number of bits N that have not been quantized r The larger the requirement for the gain-bandwidth product of the operational amplifier is, the higher the requirement is, which is represented by the following formulas (3) and (d)
ω u ＝f u *2π (4)
Gain bandwidth product f of operational amplifier u The following requirements should be met:
especially for the operational amplifier in the first stage circuit, N r Maximum, f u And (2) the requirement of the first stage circuit is highest, the power consumption of the first stage circuit occupies the maximum proportion of the whole power consumption of the analog-digital converter, and then the power consumption is gradually decreased. N in (5) r And beta are both determined by the architecture of the pipelined analog-to-digital converter, and the low power designs published in the prior art are designed by optimizing N r And beta to reduce the sub-stage circuit pair f u And T is a fixed T/2 in the case of a conventional 50% duty cycle sampling clock. On the basis of inheriting the existing low-power consumption technology, the invention can achieve the aim of further reducing the power consumption of the whole circuit by changing the duty ratio of the sampling clock and adjusting the proportion of phi 1 and phi 2 to the total clock period T, namely adjusting T in the denominator of the formula (5). In the pipelined analog-to-digital converter, a switched capacitor circuit in each sub-stage circuit is alternately in a sampling mode and a feedback operation mode, namely, when a first sub-stage and a third sub-stage … (j is a positive integer) of a 2j-1 th sub-stage are in a high level, the switched capacitor circuit is in the sampling mode; when phi 2 is high level, the first and third sub-stages …, 2j-1 (j is a positive integer), and the switched capacitor circuit is in a feedback operation mode; when phi 1 is high level, the second and fourth sub-stages …, 2i sub-stage are in feedback operation mode; the second and fourth sub-stages …, 2i sub-stages are in the sampling mode when phi 2 is high. Since the sum of the high level widths of phi 1 and phi 2 is T, which is a fixed value at a specific sampling frequency, the first sub-stage and the third sub-stage are reduced by increasing the phi 2 duration When the gain bandwidth product requirement of the sub-stage …, namely the 2j-1 sub-stage, is reduced phi 1, the gain bandwidth product requirement of the second sub-stage and the fourth sub-stage …, namely the 2i sub-stage circuit is increased, and the optimal clock duty ratio corresponding to the lowest power consumption can be finally obtained through mathematical analysis on a specific pipelined analog-digital converter architecture.
Taking a 10-bit resolution pipelined analog-to-digital converter as an example, assuming a common 8-stage 3-2-2-2-2-2-2 low-power consumption pipelined structure, wherein the first 7 sub-stages comprise switched capacitor circuits, and the last sub-stage only quantizes the input signals, the gain-bandwidth product requirements of the operational amplifiers in the first 7 sub-stages are respectively:
each sub-stage N in formula (6) r The values of beta and t are shown in figure 8,
the gain-bandwidth product design expression of the single-pole operational amplifier is:
f u ＝g m /C L (7)
wherein g m Transconductance and power consumption current I of operational amplifier D The relation of (2) is:
wherein μ is carrier mobility, C ox The invention defaults that W and L of transconductance MOS in each sub-level operational amplifier are fixed and g is the same, and W and L are the technological parameters m Is regulated by changing the overdrive voltage VGS-VTH of the MOS; c (C) L Is a load capacitor, mainly related to the first capacitor C1 of the feedback capacitor and the load of the lower circuit, if W and L of the transconductance MOS in each sub-level operational amplifier are fixed, C L The sub-levels may also be considered identical. By combining equations (7) and (8), the gain-bandwidth product can be obtained as:
where k is a constant, the product f of the power consumption and gain bandwidth of the operational amplifier is known from equation (9) u In proportion to the square of (a), and taking into account both the formulas (6) and (9), the expression of the current consumed by the operational amplifier of each sub-stage of the pipelined analog-to-digital converter can be obtained:
by combining equation (10) with fig. 8, and considering that the sum of the high level widths of phi 1 and phi 2 is T, the relation between the total power consumption of the pipelined analog-to-digital converter and the duty cycle of phi 2 can be obtained, and further the relation between the normalized power consumption and the duty cycle of phi 2 is shown in fig. 7,
FIG. 7 is an ordinate of I in the formula (10) D 1、I D 2 to I D 7 each sub-level power consumption is added to obtain total power consumption, and then normalization processing is carried out by taking the total power consumption value when the duty ratio of phi 2 is 0.5 as a reference, so that under the traditional sampling clock with 50% duty ratio (the duty ratio of phi 2 is 0.5), the pipelined analog-digital converter cannot achieve the lowest power consumption, and when the duty ratio of phi 2 is 0.6, the lowest power consumption saves about 11% compared with the power consumption when the duty ratio of phi 2 is 0.5. The circuit with very mature duty ratio of the sampling clock can be realized, the power consumption and the area are very small, and the power consumption is negligible compared with the total power consumption of the pipelined analog-to-digital converter.
For pipeline analog-to-digital converters with other resolutions or other sub-level circuit architectures, the corresponding optimal sampling clock duty ratio can be obtained by simply repeating the analysis process so as to reduce the overall power consumption of the circuit.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A pipelined analog-to-digital converter based on a non-50% duty cycle sampling clock comprising: m sub-stages and a digital correction module, m is a positive integer, each sub-stage except the m sub-stage includes: a sample hold circuit unit, a sub-digital-to-analog converter unit, a subtracter unit and an amplifier unit,
the sample-hold circuit unit is used for inputting the signal V to the sub-stage when the rising edge of the sampling clock arrives each time in Sampling and keeping the result of each sampling until the next sampling;
the sub-analog-digital converter unit is used for quantizing the result of each sampling and outputting an n-bit digital signal, wherein n bits are recorded as n-bits, and n is a positive integer;
the sub-digital-to-analog converter unit is used for converting the n-bits digital signal into an analog signal and subtracting V from the analog signal through the subtracter unit in Obtaining a residual error signal;
the amplifier unit is used for amplifying the residual error signal by 2 (n-1) times to obtain an output signal V out As an input signal to the next sub-stage, the mth sub-stageThe stage does not need to amplify the residual error signal by an amplifier unit;
input signal V of the first sub-stage in For inputting analog signals, each sub-stage of the pipelined analog-to-digital converter simultaneously and parallelly works under the control of a sampling clock, wherein the sampling clock is used for providing clock signals for the pipelined analog-to-digital converter, the input analog signals are quantized step by step from a first sub-stage to an mth sub-stage, the quantization result of each sub-stage is calculated by a digital correction module, and finally, N bits of digital signals are output, and the N bits are recorded as N-bits;
the sub-digital-to-analog converter unit, the subtractor unit and the amplifier unit in each sub-stage except the m-th sub-stage are realized by a switched capacitor circuit, and the input signal of the switched capacitor circuit is marked as V in 1, the switched capacitor circuit comprises a first capacitor C 1 A second capacitor C 2 And an operational amplifier for controlling the first capacitor C by the first sampling clock and the second sampling clock 1 A second capacitor C 2 The connection relation of the two capacitors is that the first sampling clock is recorded as phi 1, the second sampling clock is recorded as phi 2, phi 1 and phi 2 are two-phase non-overlapping sampling clocks, the clock periods of phi 1 and phi 2 are both T, T is one sampling clock period of the pipelined analog-to-digital converter, the duty ratios of phi 1 and phi 2 are both between 0 and 1, the sum of the duty ratios of phi 1 and phi 2 is 1, and the duty ratios of phi 1 and phi 2 are adjusted to enable the power consumption of the pipelined analog-to-digital converter to be minimum;
The switch capacitor circuit also comprises a first phi 1 switch, a second phi 1 switch, a third phi 1 switch, a first phi 2 switch, a second phi 2 switch and a three-input gating device,
the V is in 1 are respectively connected with the first end of the first phi 1 switch and the first end of the second phi 1 switch, and the second end of the first phi 1 switch is respectively connected with the first capacitor C 1 A first end of a first phi 2 switch is connected with the output end of the operational amplifier, a second end of the first phi 2 switch is connected with the first capacitor C 1 Is respectively connected with the inverting input end of the operational amplifier and the first end of a third phi 1 switch, and the second end of the third phi 1 switch is connected with the operational amplifierA second terminal of the third phi 1 switch is connected to ground, and a second capacitor C 2 Is respectively connected with the second end of the second phi 1 switch and the second end of the second phi 2 switch, the second capacitor C 2 The second end of the second phi 2 switch is connected with the first end of a three-input gating device, the second end of the three-input gating device is connected with +Vref, the third end of the three-input gating device is connected with-Vref, the fourth end of the three-input gating device is connected with 0, and the fifth end of the three-input gating device is connected with a sub-analog-digital converter;
The steps of the duty ratios corresponding to phi 1 and phi 2 when the minimum power consumption of the pipelined analog-to-digital converter is obtained are as follows:
s1, obtaining an output signal V of an output end of an operational amplifier when clock signals corresponding to phi 1 and phi 2 of a switched capacitor circuit are in different states out V is obtained out The formula of variation with sampling time t and analyzing the obtained V out The variation formula along with the sampling time t obtains the product omega of the error epsilon of the output signal and the gain bandwidth of the operational amplifier u And the relation between the sampling time t;
s2, obtaining a gain bandwidth product omega according to the error epsilon of the output signal obtained in S1 and the condition which should be satisfied and related to the number of unquantized bits after the sub-level u Conditions to be satisfied;
s3, obtaining gain bandwidth product omega u ＝2π×g m /C L The g is m Is the transconductance value of the operational amplifier, C L For the load capacitance, the C L Is of the same size as the first capacitance C 1 And the circuit load of the next sub-stage is related and is according to g m And operational amplifier power consumption current I D Obtain the relation of gain bandwidth product and I D And according to the gain bandwidth product and the power consumption current I D The relation of (2) and the gain bandwidth product omega in S2 u The power consumption current I of the ith sub-level in the first m-1 sub-levels is obtained under the condition that the power consumption current I needs to be met D Is an expression of (2);
s4, duty cycle according to phi 1 and phi 2 The sum is 1 and the power consumption current I of the ith sub-level in the m-1 sub-levels before S3 D The method comprises the steps of adding the power consumption of the first m-1 sub-stages to obtain the total power consumption of the pipelined analog-to-digital converter, wherein the sampling time t of each sub-stage is equal to the product of the duty ratio of the sampling clock of the sub-stage and the period of the sampling clock, the duty ratio of phi 2 is adjusted, so that the relation between normalized power consumption and the duty ratio of phi 2, the duty ratio value of phi 2 when the normalized power consumption is the lowest and the duty ratio value of phi 1 when the normalized power consumption is the lowest are obtained, the duty ratio corresponding to the sampling clock when the pipelined analog-to-digital converter is the lowest is obtained, and the normalized power consumption is the result of normalized processing by taking the total power consumption value when the duty ratio of phi 2 is 0.5 as a reference.
2. The non-50% duty cycle sampling clock based pipelined analog-to-digital converter of claim 1, wherein: in the switch capacitor circuit of S1, the switch capacitor circuit is divided into a sampling mode and a feedback operation mode according to different signal states corresponding to phi 1 and phi 2,
when the signal state corresponding to phi 1 is high, the switched capacitor circuit is in a sampling mode, the first phi 1 switch, the second phi 1 switch and the third phi 1 switch are closed, the first phi 2 switch and the second phi 2 switch are opened, and at the moment, two input ends of the operational amplifier are connected with common mode voltage, V in 1 is sampled to a first capacitance C 1 And a second capacitor C 2 Applying;
when the signal state corresponding to phi 2 is high, the switched capacitor circuit is in a feedback operation mode, and the operational amplifier outputs through the first capacitor C 1 And a second capacitor C 2 The feedback is connected to the negative input terminal of the operational amplifier, the second capacitor C 2 The first terminal is input +Vref, 0 or-Vref, and is specifically determined by the digital signal output by the sub-analog-to-digital converter.
3. The pipelined analog-to-digital converter based on a non-50% duty cycle sampling clock of claim 2, wherein: when the switched capacitor circuit is in a feedback mode of operation,
output signal V of operational amplifier output end out Can be expressed as:
the V is x Is +Vref, 0 or-Vref, V x Depending on the n-bits digital signal output by the sub-analog-to-digital converter, said A cl = (first capacitance C 1 +second capacitance C 2 ) First capacitor C 1 ＝1/β＝2^(n-1)，A cl The ideal closed loop gain of the operational amplifier is the voltage amplification factor when the amplifying circuit with negative feedback is formed, n is the quantized bit number of the sub-stage, beta is the loop feedback coefficient, V sub Is the residual error signal, namely the equivalent input signal of the switched capacitor circuit at the moment;
approximating the operational amplifier as a single-pole system, then V out The formula of change with sampling time t:
in the feedback operation mode, the switched capacitor circuit must output a result close enough to an ideal value in a period when the corresponding sampling clock is at a high level, where the ideal value is a value when the error epsilon of the output signal is equal to 0, and the error epsilon of the output signal needs to satisfy the following conditions:
the N is r For the number of bits not yet quantized after this sub-level,
feedback coefficient β=1/(2≡1)), where n is the number of quantization bits of the present sub-level.
4. A pipelined analog-to-digital converter based on a non-50% duty cycle sampling clock as claimed in claim 3 wherein: said S2 is according toOmega, omega u ＝f u *2 pi, f is u Is the gain bandwidth product omega u The corresponding frequency is obtained f u The conditions to be satisfied are:
in each sub-stage of the pipelined analog-to-digital converter, wherein the first m-1 sub-stages comprise operational amplifiers, the mth sub-stage only quantizes its input signal, the gain-bandwidth product f of the ith sub-stage of the first m-1 sub-stages u i conditions to be satisfied:
the N is r i is the number of bits which are not quantized in the ith sub-level in the previous m-1 sub-levels, βi is the loop feedback coefficient of the ith sub-level in the previous m-1 sub-levels, and ti is the feedback operation time corresponding to the ith sub-level in the previous m-1 sub-levels.
5. The non-50% duty cycle sampling clock based pipelined analog-to-digital converter of claim 4 wherein: g in the S3 m And power consumption current I D The relation of (2) is thatMu is carrier mobility, C ox For gate oxide capacitance, μ and C ox Are all technological parameters with fixed values, W and L are the gate width and the gate length of transconductance MOS in the operational amplifier, and the I is given that W and L are fixed and unchanged D Is regulated by changing the overdrive voltage Vdsat of the MOS; c (C) L Is of the same size as the first capacitance C 1 And the load of the next sub-stage circuit is related, when W and L of transconductance MOS in each sub-stage operational amplifier are fixed, C in each sub-stage operational amplifier L Also the same, and gain-bandwidth product can be obtainedCorresponding frequency f u And I D The relation of (2) is:
the k is a constant, and the power consumption current I D And f u Is proportional to the square of the gain bandwidth product in the ith sub-stage of the first m-1 sub-stages, comprehensively considering the corresponding frequency f u I is the condition to be satisfied and the frequency and I corresponding to the gain bandwidth product D The relation of the power consumption current I of the ith sub-stage in m-1 sub-stages before the pipelined analog-to-digital converter can be obtained D Expression of i
6. The non-50% duty cycle sampling clock based pipelined analog-to-digital converter of claim 1, wherein: in the pipelined analog-to-digital converter, the switched capacitor circuits in each sub-stage circuit are alternately in a sampling mode and a feedback operation mode,
Namely, when phi 1 is high level, the first sub-stage and the third sub-stage …, namely the 2j-1 sub-stage, the switched capacitor circuit is in a sampling mode;
when phi 2 is high level, the first sub-stage and the third sub-stage …, namely the 2j-1 sub-stage, are in a feedback operation mode;
when phi 1 is high level, the second and fourth sub-stages …, 2i sub-stage are in feedback operation mode; the second and fourth sub-stages …, 2i sub-stage are in the sampling mode when phi 2 is high;
the j and i are positive integers,
the sum of the high level time of phi 1 and phi 2 is T, T is a fixed value under a specific sampling frequency, and changing the duty ratio of phi 2 is to change the sampling time ti of each sub-stage, thereby changing the power consumption of each sub-stage.
7. The non-50% duty cycle sampling clock based pipelined analog-to-digital converter of claim 6, wherein: the normalization processing method comprises the following steps: taking the total power consumption value when the duty ratio of phi 2 is 0.5 as a reference, dividing the total power consumption when the duty ratio of phi 2 is equal to other values between 0 and 1 by the total power consumption value when the duty ratio of phi 2 is 0.5, and obtaining the normalized power consumption corresponding to the duty ratio of phi 2.
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