CN117277850A - Topological circuit of multi-level inverter and multi-level inverter - Google Patents
Topological circuit of multi-level inverter and multi-level inverter Download PDFInfo
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- CN117277850A CN117277850A CN202311281585.4A CN202311281585A CN117277850A CN 117277850 A CN117277850 A CN 117277850A CN 202311281585 A CN202311281585 A CN 202311281585A CN 117277850 A CN117277850 A CN 117277850A
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- 239000003990 capacitor Substances 0.000 claims abstract description 177
- 238000011084 recovery Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
Abstract
The invention discloses a topology circuit of a multi-level inverter and a multi-level inverter device, wherein the topology circuit comprises: the device comprises a direct-current voltage input module, a half-bridge module, an alternating-current voltage output module and a switched capacitor module; the switch capacitor module comprises n groups of switch capacitor units which are arranged in series; the switch capacitor unit comprises a first path and a second path, and the first path and the second path are conducted in a time-sharing way; the input end of the half-bridge module is electrically connected with the positive electrode of the direct-current voltage input module, the output end of the half-bridge module is respectively electrically connected with the negative electrode of the direct-current voltage input module and the first end of the alternating-current voltage output module, and the middle connecting end of the half-bridge module is electrically connected with the first end of the switch capacitor module; the second end of the alternating voltage output module is electrically connected with the second end of the switch capacitor module. By adopting the technical scheme, the multi-level output can be realized through n groups of switch capacitor units which are arranged in series, so that the harmonic interference of the output of the inverter can be reduced, and the circuit structure is simple.
Description
Technical Field
The present invention relates to the field of inverters, and in particular, to a topology circuit of a multilevel inverter and a multilevel inverter.
Background
Compared with the traditional two-level inverter, the multi-level inverter not only can realize the output of more voltage levels, thereby reducing the voltage stress of a switching device, generating output voltage which is more similar to sine waves, and reducing harmonic content and electromagnetic interference. Meanwhile, the multilevel inverter can also realize higher voltage and current regulation precision, and reduces the loss in the energy conversion process.
In the prior art, in order to realize more level output, diode clamping, capacitance clamping or cascaded H-bridge mode is often adopted, and an exemplary H-bridge type five-level inverter in the prior art uses 4H-bridge inverters, and each H-bridge is formed by 4 switching devices, so 16 switching devices are required in total, and the system cost is high.
Therefore, in order to meet the increasing voltage class requirements, it is important to research a novel multi-level inverter.
Disclosure of Invention
The invention provides a topological circuit of a multi-level inverter and a multi-level inverter device, which are used for reducing harmonic interference output by the inverter and have a simple circuit structure.
In a first aspect, an embodiment of the present invention provides a topology circuit of a multilevel inverter, including: the device comprises a direct-current voltage input module, a half-bridge module, an alternating-current voltage output module and a switched capacitor module;
The switch capacitor module comprises n groups of switch capacitor units which are arranged in series; the switch capacitor unit comprises a first path and a second path, and the first path and the second path are conducted in a time-sharing way; n is more than or equal to 3, and n is a positive integer;
the input end of the half-bridge module is electrically connected with the positive electrode of the direct-current voltage input module, the output end of the half-bridge module is respectively electrically connected with the negative electrode of the direct-current voltage input module and the first end of the alternating-current voltage output module, and the middle connecting end of the half-bridge module is electrically connected with the first end of the switched capacitor module;
the second end of the alternating voltage output module is electrically connected with the second end of the switch capacitor module.
Optionally, the half-bridge module includes a first switch and a second switch;
the switch capacitor unit comprises a third switch, a fourth switch and a capacitor;
the input end of the first switch is electrically connected with the positive electrode of the direct-current voltage input module, and the output end of the first switch is electrically connected with the input end of the second switch and the middle connection end of the half-bridge module, the input end of the third switch and the output end of the fourth switch respectively;
The output end of the second switch is electrically connected with the negative electrode of the direct-current voltage input module;
the output end of the third switch is electrically connected with the negative electrode of the capacitor, and the input end of the fourth switch is electrically connected with the positive electrode of the capacitor.
Optionally, the half-bridge module further includes a first diode and a second diode;
the switch capacitance unit also comprises a third diode and a fourth diode;
the positive electrode of the first diode is electrically connected with the output end of the first switch, and the negative electrode of the first diode is electrically connected with the negative electrode of the first switch;
the anode of the second diode is electrically connected with the output end of the second switch, and the cathode of the second diode is electrically connected with the cathode of the second switch;
the anode of the third diode is electrically connected with the output end of the third switch, and the cathode of the third diode is electrically connected with the cathode of the third switch;
the positive pole of the fourth diode is electrically connected with the output end of the fourth switch, and the negative pole of the fourth diode is electrically connected with the negative pole of the fourth switch.
Optionally, the first switch and the second switch are complementarily turned on;
the third switch is complementarily conducted with the fourth switch.
Optionally, the topology circuit further includes: a controller;
the controller is electrically connected with the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch respectively, and is used for controlling the on and off of the first switch, the second switch, the third switch and the fourth switch.
Optionally, the capacitance values of any two of the capacitors are the same.
Optionally, the switched capacitor module includes three groups of the switched capacitor units arranged in series;
the three groups of switch capacitor units are arranged in series and comprise a first group of switch capacitor units, a second group of switch capacitor units and a third group of switch capacitor units which are sequentially arranged between the connecting middle end of the half-bridge module and the second end of the alternating voltage output module;
the first group of switch capacitor units comprise a first group of first switches and a first group of second switches, the second group of switch capacitor units comprise a second group of first switches and a second group of second switches, and the third group of switch capacitor units comprise a third group of first switches and a third group of second switches;
the input voltage value of the direct-current voltage input module is V1, and the output voltage value of the alternating-current voltage output module is V2;
When the multilevel inverter is in a first working state, the first switch is turned on, the second switch is turned off, the first group of first switches are turned on, the first group of second switches are turned off, the second group of first switches are turned on, the second group of second switches are turned off, the third group of first switches are turned on, and the third group of second switches are turned off, so that v2=v1;
when the multi-level inverter is in a second working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned off, and the third group of second switches is turned on, so that v2= -V1;
when the multilevel inverter is in a third working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= (2/3) V1;
When the multilevel inverter device is in a fourth operating state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned on, and the third group of second switches is turned off, v2= (2/3) V1;
when the multilevel inverter device is in a fifth working state, the first switch is turned on, the second switch is turned off, the first group of first switches are turned on, the first group of second switches are turned off, the second group of first switches are turned on, the second group of second switches are turned off, the third group of first switches are turned off, and the third group of second switches are turned on, so that v2= (2/3) V1;
when the multilevel inverter device is in a sixth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= - (2/3) V1;
When the multi-level inverter is in a seventh working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned off, and the third group of second switches is turned on, so that v2= - (2/3) V1;
when the multi-level inverter is in an eighth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned off, and the third group of second switches is turned on, so that v2= - (2/3) V1;
when the multi-level inverter is in a ninth working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= (1/3) V1;
When the multilevel inverter device is in a tenth working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned off, and the third group of second switches is turned on, so v2= (1/3) V1;
when the multi-level inverter is in an eleventh working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned off, and the third group of second switches is turned on, then v2= (1/3) V1;
when the multilevel inverter device is in a twelfth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= - (1/3) V1;
When the multi-level inverter is in a thirteenth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned off, and the third group of second switches is turned on, then v2= - (1/3) V1;
when the multi-level inverter is in a fourteenth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= - (1/3) V1;
when the multi-level inverter is in a fifteenth working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned off, and the third group of second switches is turned on, so that v2=0;
When the multi-level inverter is in the sixteenth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned on, and the third group of second switches is turned off, so v2=0.
Optionally, the first switch, the second switch, the third switch and the fourth switch each comprise a metal oxide semiconductor, a junction field effect transistor or an insulated gate bipolar transistor.
Optionally, the first diode, the second diode, the third diode, and the fourth diode each include a silicon carbide diode, a fast recovery diode, or an ultrafast recovery diode.
In a second aspect, an embodiment of the present invention further provides a multi-level inverter, including the topology circuit according to any one of the first aspects.
According to the technical scheme provided by the embodiment of the invention, the direct-current voltage input module can output direct-current voltage, and then the direct-current voltage can be changed into alternating current through the half-bridge module and the switched capacitor module, so that the alternating current can be output through the alternating-current voltage output module. Further, the switched capacitor module comprises n groups of switched capacitor units which are arranged in series, the switched capacitor units comprise a first path and a second path, the first path and the second path are conducted in a time-sharing mode, that is, the first path and the second path can be controlled to be conducted in a time-sharing mode by controlling the on-off of a switch in the switched capacitor units, on one hand, the output of the inverter in a multi-level mode, namely, the output voltage which is closer to sine waves can be achieved through the n groups of switched capacitor units which are arranged in series, and further, the harmonic content and the electromagnetic interference can be reduced, on the other hand, the circuit is simple in structure, compact in device and low in cost.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is an electrical schematic diagram of a topology circuit of a multi-level inverter according to an embodiment of the present invention;
fig. 2 is an electrical schematic diagram of a topology circuit of another multi-level inverter according to an embodiment of the present invention;
fig. 3 is a schematic diagram of conduction of a topology circuit of a multi-level inverter in a first operating state according to an embodiment of the present invention;
fig. 4 is a schematic conduction diagram of a topology circuit of a multi-level inverter according to an embodiment of the present invention in a second operating state;
Fig. 5 is a schematic diagram of conduction of a topology circuit of a multi-level inverter in a third operating state according to an embodiment of the present invention;
fig. 6 is a schematic diagram of conduction of a topology circuit of a multi-level inverter in a sixth operating state according to an embodiment of the present invention;
fig. 7 is a schematic diagram of conduction of a topology circuit of a multi-level inverter in a ninth operating state according to an embodiment of the present invention;
fig. 8 is a schematic diagram illustrating a topology circuit of a multi-level inverter according to an embodiment of the present invention in a twelfth operating state;
fig. 9 is a schematic diagram of conduction of a topology circuit of a multi-level inverter in a fifteenth operating state according to an embodiment of the present invention;
fig. 10 is a schematic diagram of conduction of a topology circuit of a multi-level inverter in a sixteenth operating state according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
Fig. 1 is an electrical schematic diagram of a topology circuit of a multi-level inverter according to an embodiment of the present invention, where, as shown in fig. 1, the topology circuit of the multi-level inverter includes: a direct current voltage input module 10, a half-bridge module 20, an alternating current voltage output module 30, and a switched capacitor module 40; the switched capacitor module 40 includes n groups of switched capacitor units 401 arranged in series; the switched capacitor unit 401 includes a first path 41 and a second path 42, where the first path 41 and the second path 42 are in time-sharing conduction; n is more than or equal to 3, and n is a positive integer; the input end a of the half-bridge module 20 is electrically connected with the positive pole+ of the direct-current voltage input module 10, the output end B of the half-bridge module 20 is electrically connected with the negative pole-a 1 of the direct-current voltage input module 10 and the first end a1 of the alternating-current voltage output module 30 respectively, and the middle connecting end E of the half-bridge module 20 is electrically connected with the first end B1 of the switched capacitor module 40; the second terminal a2 of the ac voltage output module 30 is electrically connected to the second terminal b2 of the switched capacitor module 40.
Specifically, the dc voltage input module 10 can provide dc power, and the dc power can be converted into ac power after passing through the half-bridge module 20 and the switched capacitor module 40, thereby implementing the inverter function.
Further, the input terminal a of the half-bridge module 20 is electrically connected to the positive electrode+ of the dc voltage input module 10, so that the current of the dc voltage input module 10 is output from the positive electrode to the ac output module 30 along the first path 41 through the input terminal a of the half-bridge module 20, that is, the ac output module 30 can output positive ac current. The output terminal B of the half-bridge module 20 is electrically connected to the negative electrode-a 1 of the dc voltage input module 10 and the first terminal a1 of the ac voltage output module 30, and when the capacitor in the switched capacitor unit 401 discharges, since the middle connection terminal E of the half-bridge module 20 is electrically connected to the first terminal B1 of the switched capacitor module 40, the positive electrode+ current of the capacitor reaches the ac output module 30 through the middle connection terminal E of the half-bridge module 20 and the output terminal B of the half-bridge module 20, and thus the ac output module 30 can output negative ac. In other words, the ac voltage output module 30 may be controlled to output the positive and negative of the ac power by controlling the on and off of the switch between the input terminal a and the connection center terminal E and the switch between the connection center terminal E and the output terminal B of the half bridge module 20.
It will be appreciated that the first path 41 means that the current does not pass through the capacitance in the switched capacitor unit 401, but rather through a switch in parallel with the capacitance. The second path 42 refers to the current flowing from the capacitor in the switched capacitor unit 401 through the switch in series with the capacitor.
Further, the switched capacitor module 40 includes a switch and a capacitor, and can realize charging and discharging of the capacitor by controlling on/off of the switch, so as to realize time-sharing conduction of the first path 41 and the second path 42. Specifically, the switched capacitor module 40 includes n groups of switched capacitor units 401 arranged in series, each group of switched capacitor units 401 is formed by the same device, and by controlling the on and off states of the switches in the switched capacitor units 401, a plurality of arrangements and combinations can be formed, so that a plurality of ac power can be output. In addition, by arranging and combining the on/off of the switch in the half bridge module 20 and the switch in the switching capacitor unit 401, the ac output module 30 can be made to output an ac voltage close to a sine wave, and thus the harmonic content and electromagnetic interference can be reduced.
The topological circuit of the multilevel inverter provided by the embodiment of the invention has the advantages that the switch capacitor module comprises n groups of switch capacitor units which are arranged in series, the switch capacitor unit comprises a first path and a second path, the first path and the second path are conducted in a time-sharing way, namely, the first path and the second path can be controlled to be conducted in a time-sharing way by controlling the on-off of a switch in the switch capacitor unit, so that on one hand, the output multilevel of the inverter can be realized through the n groups of switch capacitor units which are arranged in series, namely, the output voltage is closer to the output voltage of sine waves, and further, the harmonic content and the electromagnetic interference can be reduced, and on the other hand, the circuit structure is simple, the device is compact, and the cost is low.
Optionally, with continued reference to fig. 1, the half-bridge module 20 includes a first switch S1 and a second switch S2; the switched capacitor unit 401 includes a third switch S3, a fourth switch S4, and a capacitor C; the input end of the first switch S1 is electrically connected with the positive electrode of the direct-current voltage input module 10, and the output end of the first switch S1 is electrically connected with the input end of the second switch S2 and the middle connection end E of the half-bridge module 20, the input end of the third switch S3 and the output end of the fourth switch S4 respectively; the output end of the second switch S2 is electrically connected with the negative electrode of the direct-current voltage input module 10; the output end of the third switch S3 is electrically connected with the negative electrode of the capacitor C, and the input end of the fourth switch S4 is electrically connected with the positive electrode of the capacitor C.
Specifically, the first switch S1 is disposed between the positive electrode of the dc voltage input module 10+ and the middle connection terminal E of the half-bridge module 20, and the second switch S2 is disposed between the negative electrode of the dc voltage input module 10-and the middle connection terminal E of the half-bridge module 20, that is, the on/off of the first switch S1 and the second switch S2 is controlled to control the ac voltage output module 30 to output the positive or negative of the ac voltage.
Further, with continued reference to fig. 1, the first switch S1 and the second switch S2 are complementarily turned on; the third switch S3 is complementarily turned on with the fourth switch S4.
Specifically, taking the first switch S1 and the second switch S2 as examples, the complementary conduction may be understood as that the first switch S1 and the second switch S2 are not turned on at the same time, that is, when the first switch S1 is turned on, the second switch S2 is turned off, or when the second switch S2 is turned on, the first switch S1 is turned off. As can be seen from fig. 1, the switched capacitor unit 401 includes two switches and a capacitor C, the third switch S3 is connected in parallel with the capacitor C, the fourth switch S4 is connected in series with the capacitor C, and the third switch S3 and the fourth switch S4 are complementarily turned on, so that the capacitor C can be prevented from being directly connected. Taking a switched capacitor unit 401 as an example, the switched capacitor unit 401 may include a third switch S3, a fourth switch S4 and a first capacitor C1, when the third switch S3 is turned on and the fourth switch S4 is turned off, i.e. the first path 41 is turned on, the branch of the third switch S3 is short-circuited, i.e. corresponds to a wire, and the first capacitor C1 is not connected to the circuit, and the voltage across the first capacitor C1 is 0; when the fourth switch S4 is turned on and the third switch S3 is turned off, i.e. the second path 42 is turned on, the positive electrode+ of the first capacitor C1 is connected to the middle connection terminal E of the half-bridge module 20 through the fourth switch S4, and at this time, the first capacitor C1 is discharged, which is equivalent to that the first capacitor C1 is connected to the ac voltage output module 30 through the second path.
Specifically, when the first switch S1 is turned on and the second switch S2 is turned off, the current is transmitted from the positive electrode+ of the dc voltage input module 10 to the second end a2 of the ac voltage output module 30 through the first switch S1 and the switching module 40 in sequence, and then forms a loop with the negative electrode of the dc voltage input module 10 and the first end a1 of the ac voltage output module 30, so that the ac voltage output module 30 can output positive ac current. When the second switch S2 is turned on and the first switch S1 is turned off, the capacitor C in the switched capacitor module 40 discharges, and the current flows out from the positive electrode of the capacitor C, is transmitted to the first end a1 of the ac voltage output module 30 through the middle connection end E of the half-bridge module 20 and the second switch S2, and forms a loop with the negative electrode of the capacitor C and the second end a2 of the ac voltage output module 30, so that the ac voltage output end can output negative ac current.
Further, by controlling the on/off of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, various ac voltages can be output, thereby realizing the function of the multilevel inverter.
Optionally, with continued reference to fig. 1, the half-bridge module 20 further includes a first diode D1 and a second diode D2; the switched capacitor unit 401 further includes a third diode D3 and a fourth diode D4; the positive electrode of the first diode D1 is electrically connected with the output end of the first switch S1, and the negative electrode of the first diode D1 is electrically connected with the negative electrode of the first switch S1; the positive electrode of the second diode D2 is electrically connected with the output end of the second switch S2, and the negative electrode of the second diode D2 is electrically connected with the negative electrode of the second switch S2; the positive electrode of the third diode D3 is electrically connected with the output end of the third switch S3, and the negative electrode of the third diode D3 is electrically connected with the negative electrode of the third switch S3; the positive electrode of the fourth diode D4 is electrically connected to the output terminal of the fourth switch S4, and the negative electrode of the fourth diode D4 is electrically connected to the negative electrode of the fourth switch S4.
Specifically, taking the first diode D1 as an example, the anode of the first diode D1 is electrically connected to the output end of the first switch S1, and the cathode of the first diode D1 is electrically connected to the cathode of the first switch S1, that is, the first diode D1 is reversely connected in parallel to two ends of the first switch S1, so that the first switch S1 can be protected from reverse voltage, that is, when the first switch S1 is turned off, charges flow back to the first diode D1, and the first diode D1 is turned on to form a path, thereby preventing the first switch S1 from being damaged due to excessively high reverse voltage. In addition, the efficiency of the inverter can be improved by arranging the anti-parallel diode, namely, uninterrupted current circulation is realized through the anti-parallel diode, the bottleneck of current is reduced, and the loss and the power consumption of the switching tube can be reduced.
It can be understood that each diode connected in anti-parallel with the switch has the functions of protecting the switch and improving the working efficiency of the inverter, which is not described herein.
Optionally, the topology circuit further comprises: a controller; the controller is electrically connected with the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch respectively and is used for controlling the on and off of the first switch, the second switch, the third switch and the fourth switch.
Specifically, the control end of each switch can be understood as a gate or a base, the on/off of the switch can be controlled by the control end, and the controller is electrically connected with the control end of each switch to further control the on/off of each switch, namely, the on/off of the switches can be arranged and combined to realize the output of various alternating voltages.
Further, with continued reference to fig. 1, the capacitance values of any two capacitors C are the same.
For example, when the switched capacitor module 40 includes 3 switched capacitor cells 401 arranged in series, the voltage across each capacitor C may be 1/3 of the dc input voltage module 10 when the capacitor C is connected into the circuit. When the switched capacitor module 40 comprises 4 switched capacitor units 401 arranged in series, the voltage across each capacitor C may be 1/4 of the dc input voltage module 10 when the capacitor C is connected to the circuit, i.e. when the switched capacitor module 40 comprises n switched capacitor units 401 arranged in series, the voltage across each capacitor C may be 1/n of the dc input voltage module 10 when the capacitor C is connected to the circuit.
Further, fig. 2 is an electrical schematic diagram of a topology circuit of another multi-level inverter according to an embodiment of the present invention, and as shown in fig. 2, the switched capacitor module 40 includes three groups of switched capacitor units 401 arranged in series; the three groups of switch capacitor units 401 arranged in series include a first group of switch capacitor units 4011, a second group of switch capacitor units 4012 and a third group of switch capacitor units 4013 which are sequentially arranged between the connection middle end E of the half-bridge module 20 and the second end a2 of the alternating voltage output module 30; the first group of switch capacitor units 4011 comprises a first group of first switches S11 and a first group of second switches S12, the second group of switch capacitor units 4012 comprises a second group of first switches S21 and a second group of second switches S22, and the third group of switch capacitor units 4013 comprises a third group of first switches S31 and a third group of second switches S32; the input voltage value of the direct-current voltage input module 10 is V1, and the output voltage value of the alternating-current voltage output module 30 is V2;
The first group of switch capacitor units 4011 further includes a first capacitor C1, the second group of switch capacitor units 4012 further includes a second capacitor C2, and the third group of switch capacitor units 4013 further includes a third capacitor C3.
As a possible implementation manner, fig. 3 is a schematic conducting diagram of the topology circuit of the multi-level inverter provided by the embodiment of the present invention in the first operating state, as shown in fig. 3, when the multi-level inverter is in the first operating state, the first switch S1 is turned on, the second switch S2 is turned off, the first switch S11 is turned on, the first switch S12 is turned off, the first switch S21 is turned on, the second switch S22 is turned off, the first switch S31 is turned on, and the second switch S32 is turned off, that is, the voltage across the dc voltage input module 10 is directly output to the ac voltage output module 30 through the first switch S1, the second capacitor C2, and the third capacitor C3 without passing through the first switch S1, the first switch S11, the second switch S21, and the third switch S31, so v2=v1.
As another possible implementation manner, fig. 4 is a schematic conduction diagram of the topology circuit of the multi-level inverter provided by the embodiment of the present invention in the second operating state, as shown in fig. 4, when the multi-level inverter is in the second operating state, the first switch S1 is turned off, the second switch S2 is turned on, the first set of first switches S11 is turned off, the first set of second switches S12 is turned on, the second set of first switches S21 is turned off, the second set of second switches S22 is turned on, the third set of first switches S31 is turned off, and the third set of second switches S32 is turned on, i.e. the first capacitor C1, the second capacitor C2, and the third capacitor C3 are discharged, and at this time, the current paths are opposite to those of the first operating state, so v2= -V1.
As still another possible implementation manner, fig. 5 is a schematic conducting diagram of the topology circuit of the multi-level inverter provided by the embodiment of the present invention in the third operating state, as shown in fig. 5, when the multi-level inverter is in the third operating state, the first switch S1 is turned on, the second switch S2 is turned off, the first set of first switches S11 is turned off, the first set of second switches S12 is turned on, the second set of first switches S21 is turned on, the second set of second switches S22 is turned off, the third set of first switches S31 is turned on, and the third set of second switches S32 is turned off, that is, only the first capacitor C1 is turned on, that is, the dc voltage input module 10 charges the first capacitor C1, and v2= (2/3) V1 because the capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2 is equal to the capacitance value of the third capacitor C3.
It can be understood that when the multilevel inverter device is in the fourth operating state, the first switch S1 is turned on, the second switch S2 is turned off, the first set of first switches S11 is turned on, the first set of second switches S12 is turned off, the second set of first switches S21 is turned off, the second set of second switches S22 is turned on, the third set of first switches S31 is turned on, and the third set of second switches S32 is turned off, only the second capacitor C2 is connected to the circuit, i.e. the dc voltage input module 10 charges the second capacitor C2, so v2= (2/3) V1.
It can be understood that when the multilevel inverter device is in the fifth operating state, the first switch S1 is turned on, the second switch S2 is turned off, the first set of first switches S11 is turned on, the first set of second switches S12 is turned off, the second set of first switches S21 is turned on, the second set of second switches S22 is turned off, the third set of first switches S31 is turned off, and the third set of second switches S32 is turned on, and only the third capacitor C3 is connected to the circuit, i.e. the dc voltage input module 10 charges the third capacitor C3, so v2= (2/3) V1.
As yet another possible implementation manner, fig. 6 is a schematic conduction diagram of a topology circuit of a multi-level inverter provided by the embodiment of the present invention in a sixth operating state, as shown in fig. 6, when the multi-level inverter is in the sixth operating state, the first switch S1 is turned off, the second switch S2 is turned on, the first set of first switches S11 is turned off, the first set of second switches S12 is turned on, the second set of first switches S21 is turned off, the second set of second switches S22 is turned on, the third set of first switches S31 is turned on, and the third set of second switches S32 is turned off, that is, when the first capacitor C1 and the second capacitor C2 are discharged, so v2= - (2/3) V1.
It can be appreciated that when the multilevel inverter device is in the seventh operating state, the first switch S1 is turned off, the second switch S2 is turned on, the first set of first switches S11 is turned on, the first set of second switches S12 is turned off, the second set of first switches S21 is turned off, the second set of second switches S22 is turned on, the third set of first switches S31 is turned off, and the third set of second switches S32 is turned on, that is, the second capacitor C2 and the third capacitor C3 are discharged at this time, so v2= - (2/3) V1.
It can be appreciated that when the multilevel inverter device is in the eighth operating state, the first switch S1 is turned off, the second switch S2 is turned on, the first set of first switches S11 is turned off, the first set of second switches S12 is turned on, the second set of first switches S21 is turned on, the second set of second switches S22 is turned off, the third set of first switches S31 is turned off, and the third set of second switches S32 is turned on, that is, the first capacitor C1 and the third capacitor C3 are discharged at this time, so v2= - (2/3) V1.
As still another possible implementation manner, fig. 7 is a schematic conduction diagram of a topology circuit of a multi-level inverter in a ninth operating state, as shown in fig. 7, when the multi-level inverter is in the ninth operating state, the first switch S1 is turned on, the second switch S2 is turned off, the first set of first switches S11 is turned off, the first set of second switches S12 is turned on, the second set of first switches S21 is turned off, the second set of second switches S22 is turned on, the third set of first switches S31 is turned on, and the third set of second switches S32 is turned off, and at this time, the first capacitor C1 and the second capacitor C2 are connected to the circuit, that is, the dc voltage input module 10 charges the first capacitor C1 and the second capacitor C2, so v2= (2/3) V1.
It can be understood that when the multilevel inverter device is in the tenth operating state, the first switch S1 is turned on, the second switch S2 is turned off, the first set of first switches S11 is turned off, the first set of second switches S12 is turned on, the second set of first switches S21 is turned on, the second set of second switches S22 is turned off, the third set of first switches S31 is turned off, and the third set of second switches S32 is turned on, and at this time, the first capacitor C1 and the third capacitor C3 are connected to the circuit, that is, the dc voltage input module 10 charges the first capacitor C1 and the third capacitor C3, so v2= (2/3) V1.
It can be understood that when the multi-level inverter is in the eleventh operating state, the first switch S1 is turned on, the second switch S2 is turned off, the first set of first switches S11 is turned on, the first set of second switches S12 is turned off, the second set of first switches S21 is turned off, the second set of second switches S22 is turned on, the third set of first switches S31 is turned off, and the third set of second switches S32 is turned on, and the first capacitor C1 and the third capacitor C3 are connected to the circuit, that is, the dc voltage input module 10 charges the second capacitor C2 and the third capacitor C3, so v2= (1/3) V1.
As still another possible implementation manner, fig. 8 is a schematic diagram of conduction when the topology circuit of the multi-level inverter provided by the embodiment of the present invention is in the twelfth operating state, as shown in fig. 8, and fig. 8 is a schematic diagram of conduction when the topology circuit of the multi-level inverter provided by the embodiment of the present invention is in the twelfth operating state, as shown in fig. 8, when the multi-level inverter is in the twelfth operating state, the first switch S1 is turned off, the second switch S2 is turned on, the first switch S11 is turned off, the first switch S12 is turned on, the first switch S21 is turned on, the second switch S22 is turned off, the first switch S31 is turned on, and the second switch S32 is turned off, that is, the first capacitor C1 is discharged, so v2= - (1/3) V1.
It will be appreciated that when the multilevel inverter device is in the thirteenth operating state, the first switch S1 is turned off, the second switch S2 is turned on, the first set of first switches S11 is turned on, the first set of second switches S12 is turned off, the second set of first switches S21 is turned on, the second set of second switches S22 is turned off, the third set of first switches S31 is turned off, and the third set of second switches S32 is turned on, that is, the third capacitor C1 is discharged, so v2= - (1/3) V1.
It will be appreciated that when the multilevel inverter device is in the fourteenth operating state, the first switch S1 is turned off, the second switch S2 is turned on, the first set of first switches S11 is turned on, the first set of second switches S12 is turned off, the second set of first switches S21 is turned off, the second set of second switches S22 is turned on, the third set of first switches S31 is turned on, and the third set of second switches S32 is turned off, that is, the second capacitor C2 is discharged, so v2= - (1/3) V1.
As still another possible implementation manner, fig. 9 is a schematic conduction diagram of a topology circuit of a multi-level inverter in a fifteenth operating state, as shown in fig. 9, when the multi-level inverter is in the fifteenth operating state, the first switch S1 is turned on, the second switch S2 is turned off, the first set of first switches S11 is turned off, the first set of second switches S12 is turned on, the second set of first switches S21 is turned off, the second set of second switches S22 is turned on, the third set of first switches S31 is turned off, and the third set of second switches S32 is turned on, and the dc voltage input module 10 charges the first capacitor C1, the second capacitor C2, and the third capacitor C3, so v2=0.
As still another possible implementation manner, fig. 10 is a schematic conduction diagram of a topology circuit of a multi-level inverter in a sixteenth operating state, as shown in fig. 10, when the multi-level inverter is in the sixteenth operating state, the first switch S1 is turned off, the second switch S2 is turned on, the first set of first switches S11 is turned on, the first set of second switches S12 is turned off, the second set of first switches S21 is turned on, the second set of second switches S22 is turned off, the third set of first switches S31 is turned on, and the third set of second switches S32 is turned off, and neither the dc voltage input module 10 nor the capacitor C is connected to the circuit, so v2=0.
Therefore, when the switched capacitor module 40 includes three groups of switched capacitor units 401 arranged in series, the ac power output module 30 can output 7 different ac voltages through the arrangement and combination of the on and off states of the switches, that is, seven-level output can be achieved, and thus, the function of the seven-level inverter can be achieved.
Optionally, with continued reference to fig. 1, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 each include a metal oxide semiconductor, a junction field effect transistor, or an insulated gate bipolar transistor.
Specifically, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 may be metal oxide semiconductor transistors, junction field effect transistors, or insulated gate bipolar transistors; taking the first switch S1 as an example, when the first switch S1 is a metal oxide semiconductor tube, the input end of the first switch S1 is a source electrode, the output end of the first switch S1 is a drain electrode, and the control end of the first switch S1 is a gate electrode; when the first switch S1 is an insulated gate bipolar transistor, the input end of the first switch S1 is a collector, the output end of the first switch S1 is an emitter, and the control end of the first switch S1 is a base. It will be appreciated that the above plurality of switching tubes may alternatively be other types of switching tubes.
Optionally, with continued reference to fig. 1, the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 each comprise a silicon carbide diode, a fast recovery diode, or an ultrafast recovery diode.
Specifically, the silicon carbide diode has a high voltage withstand capability, a low conduction loss, and the like, as compared with the conventional silicon diode, and thus can satisfy the operation performance of the inverter.
Specifically, the fast recovery diode is a semiconductor diode with good switching characteristics and short reverse recovery time, and because the base region is very thin and the reverse recovery charge is very small, the fast recovery diode has short reverse recovery time, low forward voltage drop and high reverse breakdown voltage (voltage resistance value).
Specifically, an ultrafast recovery diode is a semiconductor diode with good switching characteristics and ultra-short reverse recovery time, and is commonly used for freewheeling, absorption, clamping, isolation, output and input rectifiers for switching devices of a high-frequency inverter, so that the functions of the switching devices are fully exerted. When the diodes of the topological circuit of the multilevel inverter are silicon carbide diodes or fast recovery diodes or ultra-fast recovery diodes, the protection function can be achieved on the switches in the circuit. It is also understood that other types of diodes may be selected.
In summary, in the topology circuit of the multilevel inverter provided by the embodiment of the invention, the switched capacitor module comprises n groups of switched capacitor units which are arranged in series, the switched capacitor unit comprises a first path and a second path, and the first path and the second path are conducted in a time-sharing way, that is to say, the first path and the second path can be controlled to be conducted in a time-sharing way by controlling the on-off of a switch in the switched capacitor unit, so that on one hand, the output multilevel of the inverter can be realized through the n groups of switched capacitor units which are arranged in series, namely, the output voltage is closer to the output voltage of sine waves, and further, the harmonic content and the electromagnetic interference can be reduced, and on the other hand, the circuit has a simple structure, compact device and low cost.
Based on the same inventive concept, the embodiment of the present invention further provides a multi-level inverter, which includes the topology circuit of the multi-level inverter in the foregoing embodiment, so that the multi-level inverter provided in the embodiment of the present invention also has the foregoing technical features, which are not repeated herein.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A topology for a multilevel inverter, comprising: the device comprises a direct-current voltage input module, a half-bridge module, an alternating-current voltage output module and a switched capacitor module;
the switch capacitor module comprises n groups of switch capacitor units which are arranged in series; the switch capacitor unit comprises a first path and a second path, and the first path and the second path are conducted in a time-sharing way; n is more than or equal to 3, and n is a positive integer;
The input end of the half-bridge module is electrically connected with the positive electrode of the direct-current voltage input module, the output end of the half-bridge module is respectively electrically connected with the negative electrode of the direct-current voltage input module and the first end of the alternating-current voltage output module, and the middle connecting end of the half-bridge module is electrically connected with the first end of the switched capacitor module;
the second end of the alternating voltage output module is electrically connected with the second end of the switch capacitor module.
2. The topology of claim 1, wherein the half-bridge module comprises a first switch and a second switch;
the switch capacitor unit comprises a third switch, a fourth switch and a capacitor;
the input end of the first switch is electrically connected with the positive electrode of the direct-current voltage input module, and the output end of the first switch is electrically connected with the input end of the second switch and the middle connection end of the half-bridge module, the input end of the third switch and the output end of the fourth switch respectively;
the output end of the second switch is electrically connected with the negative electrode of the direct-current voltage input module;
the output end of the third switch is electrically connected with the negative electrode of the capacitor, and the input end of the fourth switch is electrically connected with the positive electrode of the capacitor.
3. The topology of claim 2, wherein said half-bridge module further comprises a first diode and a second diode;
the switch capacitance unit also comprises a third diode and a fourth diode;
the positive electrode of the first diode is electrically connected with the output end of the first switch, and the negative electrode of the first diode is electrically connected with the negative electrode of the first switch;
the anode of the second diode is electrically connected with the output end of the second switch, and the cathode of the second diode is electrically connected with the cathode of the second switch;
the anode of the third diode is electrically connected with the output end of the third switch, and the cathode of the third diode is electrically connected with the cathode of the third switch;
the positive pole of the fourth diode is electrically connected with the output end of the fourth switch, and the negative pole of the fourth diode is electrically connected with the negative pole of the fourth switch.
4. The topology of claim 2, wherein said first switch is complementarily conductive to said second switch;
the third switch is complementarily conducted with the fourth switch.
5. The topology of claim 2, wherein the topology further comprises: a controller;
The controller is electrically connected with the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch respectively, and is used for controlling the on and off of the first switch, the second switch, the third switch and the fourth switch.
6. The topology of claim 2, wherein the capacitance values of any two of said capacitors are the same.
7. The topology of claim 6, wherein said switched-capacitor module comprises three sets of said switched-capacitor cells arranged in series;
the three groups of switch capacitor units are arranged in series and comprise a first group of switch capacitor units, a second group of switch capacitor units and a third group of switch capacitor units which are sequentially arranged between the connecting middle end of the half-bridge module and the second end of the alternating voltage output module;
the first group of switch capacitor units comprise a first group of first switches and a first group of second switches, the second group of switch capacitor units comprise a second group of first switches and a second group of second switches, and the third group of switch capacitor units comprise a third group of first switches and a third group of second switches;
The input voltage value of the direct-current voltage input module is V1, and the output voltage value of the alternating-current voltage output module is V2;
when the multilevel inverter is in a first working state, the first switch is turned on, the second switch is turned off, the first group of first switches are turned on, the first group of second switches are turned off, the second group of first switches are turned on, the second group of second switches are turned off, the third group of first switches are turned on, and the third group of second switches are turned off, so that v2=v1;
when the multi-level inverter is in a second working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned off, and the third group of second switches is turned on, so that v2= -V1;
when the multilevel inverter is in a third working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= (2/3) V1;
When the multilevel inverter device is in a fourth operating state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned on, and the third group of second switches is turned off, v2= (2/3) V1;
when the multilevel inverter device is in a fifth working state, the first switch is turned on, the second switch is turned off, the first group of first switches are turned on, the first group of second switches are turned off, the second group of first switches are turned on, the second group of second switches are turned off, the third group of first switches are turned off, and the third group of second switches are turned on, so that v2= (2/3) V1;
when the multilevel inverter device is in a sixth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= - (2/3) V1;
When the multi-level inverter is in a seventh working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned off, and the third group of second switches is turned on, so that v2= - (2/3) V1;
when the multi-level inverter is in an eighth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned off, and the third group of second switches is turned on, so that v2= - (2/3) V1;
when the multi-level inverter is in a ninth working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= (1/3) V1;
When the multilevel inverter device is in a tenth working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned off, and the third group of second switches is turned on, so v2= (1/3) V1;
when the multi-level inverter is in an eleventh working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned off, and the third group of second switches is turned on, then v2= (1/3) V1;
when the multilevel inverter device is in a twelfth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= - (1/3) V1;
When the multi-level inverter is in a thirteenth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned off, and the third group of second switches is turned on, then v2= - (1/3) V1;
when the multi-level inverter is in a fourteenth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned on, and the third group of second switches is turned off, so that v2= - (1/3) V1;
when the multi-level inverter is in a fifteenth working state, the first switch is turned on, the second switch is turned off, the first group of first switches is turned off, the first group of second switches is turned on, the second group of first switches is turned off, the second group of second switches is turned on, the third group of first switches is turned off, and the third group of second switches is turned on, so that v2=0;
When the multi-level inverter is in the sixteenth working state, the first switch is turned off, the second switch is turned on, the first group of first switches is turned on, the first group of second switches is turned off, the second group of first switches is turned on, the second group of second switches is turned off, the third group of first switches is turned on, and the third group of second switches is turned off, so v2=0.
8. The topology of claim 2, wherein said first switch, said second switch, said third switch, and said fourth switch each comprise a metal oxide semiconductor transistor, a junction field effect transistor, or an insulated gate bipolar transistor.
9. The topology of claim 3, wherein said first diode, said second diode, said third diode, and said fourth diode each comprise a silicon carbide diode, a fast recovery diode, or an ultrafast recovery diode.
10. A multilevel inverter comprising the topology according to any one of claims 1-9.
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