CN117276081A - Preparation method of shielded gate trench MOSFET and shielded gate trench MOSFET - Google Patents

Preparation method of shielded gate trench MOSFET and shielded gate trench MOSFET Download PDF

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Publication number
CN117276081A
CN117276081A CN202311449820.4A CN202311449820A CN117276081A CN 117276081 A CN117276081 A CN 117276081A CN 202311449820 A CN202311449820 A CN 202311449820A CN 117276081 A CN117276081 A CN 117276081A
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Prior art keywords
dielectric layer
forming
layer
trench
gate
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万鹏
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Hangzhou Fuxin Semiconductor Co Ltd
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Hangzhou Fuxin Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The present disclosure provides a method for preparing a shielded gate trench MOSFET and a shielded gate trench MOSFET, the method for preparing the same comprising: forming a first epitaxial layer on a substrate; forming a first trench extending from an upper surface of the first epitaxial layer to an inside thereof; forming a source electrode dielectric layer and a source electrode conductor which are positioned in the first groove, wherein the source electrode dielectric layer comprises a first dielectric layer covering the inner wall of the first groove and a second dielectric layer at the opening of the first groove, and the source electrode conductor is positioned in a cavity formed by the source electrode dielectric layer around the first groove and is isolated from the first epitaxial layer through the source electrode dielectric layer; forming a second epitaxial layer on the first epitaxial layer, wherein the second epitaxial layer covers the second dielectric layer; forming a second trench extending from the upper surface of the second epitaxial layer to the second dielectric layer, the second trench exposing the second dielectric layer; and forming a gate dielectric layer and a gate conductor in the second trench, wherein the gate dielectric layer covers the inner surface of the second trench so as to isolate the gate conductor from the second epitaxial layer.

Description

Preparation method of shielded gate trench MOSFET and shielded gate trench MOSFET
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit manufacturing technology, and in particular, to a method for manufacturing a shielded gate trench MOSFET and a shielded gate trench MOSFET.
Background
In order to reduce the parasitic capacitance of the gate and drain of the MOSFET device, the electric field distribution is optimized, and the breakdown voltage of the device is improved. The industry is currently practiced with SGT devices having a shielded gate structure. However, the problem of large depth-to-width ratio of the groove and difficult filling of the polysilicon exists in the process flow of the device, and the formation of the shielding grid with high depth-to-width ratio is limited, so that the further improvement of the pressure resistance of the device is limited.
Disclosure of Invention
The present disclosure provides a method for manufacturing a shielded gate trench MOSFET and a shielded gate trench MOSFET, so as to at least solve the above technical problems existing in the prior art.
According to a first aspect of the present disclosure, there is provided a method for manufacturing a shielded gate trench MOSFET, the method comprising:
forming a first epitaxial layer on a substrate;
forming a first trench extending from an upper surface of the first epitaxial layer to an interior thereof;
forming a source dielectric layer and a source conductor in the first groove, wherein the source dielectric layer comprises a first dielectric layer covering the inner wall of the first groove and a second dielectric layer at the opening of the first groove, and the source conductor is positioned in a cavity formed by the source dielectric layer around the first groove and is isolated from the first epitaxial layer through the source dielectric layer;
forming a second epitaxial layer on the first epitaxial layer, wherein the second epitaxial layer covers the second dielectric layer;
forming a second trench extending from the upper surface of the second epitaxial layer to the second dielectric layer, the second trench exposing the second dielectric layer;
and forming a gate dielectric layer and a gate conductor in the second trench, wherein the gate dielectric layer covers the inner surface of the second trench so as to isolate the gate conductor from the second epitaxial layer.
In an embodiment, the forming the source dielectric layer and the source conductor in the first trench includes:
forming a first dielectric layer covering the inner wall of the first groove and the upper surface of the first epitaxial layer;
forming a source conductor which covers the surface of the first dielectric layer and is filled in the first groove;
the source conductor located above the first epitaxial layer is removed, and the source conductor located in the first trench is reserved.
In an embodiment, the forming the source dielectric layer and the source conductor in the first trench further includes:
oxidizing the upper part of the source electrode conductor by adopting an oxidation process to form the second dielectric layer positioned at the opening of the first groove;
and removing the first dielectric layer above the first epitaxial layer, reserving the first dielectric layer in the first groove, combining the first dielectric layer with the second dielectric layer to form the source dielectric layer, and wrapping the source conductor by the source dielectric layer.
In one embodiment, the upper surface of the second dielectric layer is higher than the upper surface of the first dielectric layer.
In an embodiment, the thickness of the second dielectric layer is greater than the thickness of the portion of the first dielectric layer on the upper surface of the first epitaxial layer.
In an embodiment, the forming the gate dielectric layer and the gate conductor in the second trench includes:
forming a gate dielectric layer covering the inner surface of the second trench and the upper surface of the second epitaxial layer;
forming a gate conductor covering the surface of the gate dielectric layer and filling the second trench;
and removing the gate dielectric layer and the gate conductor which are positioned above the second epitaxial layer, and reserving the gate dielectric layer and the gate conductor which are positioned in the second groove.
In one embodiment, the method further comprises:
after the gate conductor is formed, forming a well region of a first doping type in the second epitaxial layer at two sides of the gate conductor;
and forming a doped region of a second doping type in the well region of the first doping type.
In one embodiment, the method further comprises:
forming an interlayer dielectric layer covering the second epitaxial layer, the gate dielectric layer and the gate conductor;
forming a contact hole penetrating the interlayer dielectric layer, the doped region of the second doping type and extending into the well region of the first doping type;
and forming a doped region of a first doping type at the bottom of the contact hole, wherein the ion concentration of the doped region of the first doping type is larger than that of the well region of the first doping type.
In one embodiment, the method further comprises:
forming a contact plug filling the contact hole after forming the doped region of the first doping type;
and forming a metal layer on the interlayer dielectric layer, wherein the metal layer is connected with the contact plug.
According to a second aspect of the present disclosure, there is provided a shielded gate trench MOSFET including:
a substrate;
an epitaxial layer on the first surface of the substrate, the epitaxial layer having a trench therein;
the dielectric layer is positioned in the groove and comprises a peripheral dielectric layer and a second dielectric layer, the peripheral dielectric layer covers the inner wall of the groove, the second dielectric layer is transversely arranged in the groove so as to divide the groove into an upper cavity and a lower cavity from top to bottom, and the second dielectric layer is arranged to protrude towards one side of the upper cavity;
the source conductor and the gate conductor are positioned in the groove, wherein the source conductor is positioned in the lower cavity, the gate conductor is positioned in the upper cavity, and the gate conductor is exposed at the upper part of the groove.
According to the manufacturing method of the shielded gate trench MOSFET, the first trenches in the first epitaxial layer are all used for forming the source electrode conductor, then the second epitaxial layer is formed, and the second trenches in the second epitaxial layer are used for forming the gate electrode conductor, so that the depth-to-width ratio of a single-step process is reduced, the source electrode conductor (namely the shielded gate) with the ultra-high depth-to-width ratio is realized, the voltage resistance of a device is improved, and the process reliability is improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
Fig. 1 shows a cross-sectional view of a shielded gate trench MOSFET provided by an embodiment of the present disclosure;
fig. 2a to 2q are sectional views showing stages of a manufacturing method of a shielded gate trench MOSFET in an embodiment of the present disclosure; wherein,
figure 2a illustrates a schematic cross-sectional view after forming a first epitaxial layer and a mask layer in an embodiment of the present disclosure;
FIG. 2b illustrates a schematic cross-sectional view after etching a first trench location in an embodiment of the disclosure;
FIG. 2c illustrates a schematic cross-sectional view after etching a first trench in an embodiment of the disclosure;
figure 2d illustrates a schematic cross-sectional view after forming a first dielectric layer in an embodiment of the present disclosure;
fig. 2e shows a schematic cross-sectional view after forming a source conductor in an embodiment of the present disclosure;
figure 2f illustrates a schematic cross-sectional view after etching away the source conductor over the first epitaxial layer in an embodiment of the present disclosure;
FIG. 2g illustrates a schematic cross-sectional view after forming a second dielectric layer in an embodiment of the present disclosure;
figure 2h illustrates a schematic cross-sectional view of an embodiment of the present disclosure after etching away the first dielectric layer over the first epitaxial layer;
figure 2i illustrates a schematic cross-sectional view after forming a second epitaxial layer in an embodiment of the present disclosure;
FIG. 2j illustrates a schematic cross-sectional view after etching a second trench in an embodiment of the disclosure;
FIG. 2k illustrates a schematic cross-sectional view of forming a gate dielectric layer and a gate conductor in an embodiment of the disclosure;
fig. 2l illustrates a schematic cross-sectional view of removing the gate dielectric layer and gate conductor over the second epitaxial layer in an embodiment of the disclosure;
FIG. 2m illustrates a cross-sectional schematic view of forming a well region of a first doping type in an embodiment of the disclosure;
FIG. 2n illustrates a schematic cross-sectional view of forming a doped region of a second doping type in an embodiment of the disclosure;
FIG. 2o illustrates a schematic cross-sectional view of a contact hole etched in an embodiment of the present disclosure;
FIG. 2p illustrates a schematic cross-sectional view of forming a doped region of a first doping type in an embodiment of the disclosure;
FIG. 2q illustrates a schematic cross-sectional view of forming a contact plug and a metal layer in an embodiment of the present disclosure;
part number description:
10. a substrate;
20. an epitaxial layer;
201. a groove;
21. a first epitaxial layer;
211. a first trench;
211', first trench locations;
22. a second epitaxial layer;
221. a second trench;
30. a dielectric layer;
301. a peripheral dielectric layer;
31. a source electrode dielectric layer;
311. a first dielectric layer;
312. a second dielectric layer;
32. a source conductor;
41. a gate dielectric layer;
42. a gate conductor;
51. a well region of a first doping type;
52. a doped region of a second doping type;
53. a doped region of a first doping type;
60. an interlayer dielectric layer;
71. a contact hole;
72. a contact plug;
80. a metal layer;
91. a hard mask layer;
92. and a photoresist mask layer.
Detailed Description
It should be appreciated that various forms of the flows shown below may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
The embodiment of the disclosure provides a shielded gate trench MOSFET, and FIG. 1 shows a cross-sectional view of the shielded gate trench MOSFET provided by the embodiment of the disclosure.
As shown in fig. 1, the shielded gate trench MOSFET includes a substrate 10 and an epitaxial layer 20, the epitaxial layer 20 being located on a first surface (i.e., upper surface) of the substrate 10.
In an embodiment, the substrate 10 may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium substrate, etc.), or a silicon-on-insulator substrate (Silicon on Insulator, SOI), a germanium-on-insulator (Germanium on Insulator, GOI) substrate, etc.
In one embodiment, the substrate 10 is N-doped as the drain region of a shielded gate trench MOSFET, in one embodiment heavily N-doped, the epitaxial layer 20 is N-doped, and the epitaxial layer 20 is lightly doped with respect to the substrate 10.
The shielded gate trench MOSFET also includes a trench 201 within the epitaxial layer 20. The trench 201 extends from the upper surface of the epitaxial layer 20 to the inside of the epitaxial layer 20 and terminates in the epitaxial layer 20.
The shielded gate trench MOSFET further includes a dielectric layer 30 located in the trench 201, the dielectric layer 30 including a peripheral dielectric layer 301 and a second dielectric layer 312. The peripheral dielectric layer 301 includes a first dielectric layer 311 and a gate dielectric layer 41. The peripheral dielectric layer 301 covers the inner wall of the trench 201, the second dielectric layer 312 is transversely arranged in the trench 201 to divide the trench 201 into an upper cavity and a lower cavity, and the second dielectric layer 312 protrudes to one side of the upper cavity;
the second dielectric layer 312 protrudes toward the upper cavity side to form a bump structure that serves as a compression and withstand voltage when the shielded gate trench MOSFET is powered on.
In one embodiment, the upper surface of the second dielectric layer 312 is higher than the upper surface of the first dielectric layer 311. In this manner, the second dielectric layer 312 can better function to isolate the source conductor 32 from the gate conductor 42.
The shielded gate trench MOSFET also includes a source conductor 32 and a gate conductor 42 located in the trench 201. The source conductor 32 is located in the lower cavity, the gate conductor 42 is located in the upper cavity, and the gate conductor 42 is exposed at the upper portion of the trench 201.
A first dielectric layer 311 separates source conductor 32 from epitaxial layer 20 and a gate dielectric layer 41 separates gate conductor 42 from epitaxial layer 20.
The source conductor 32 constitutes the source of a shielded gate trench MOSFET.
The shielded gate trench MOSFET further includes a well region 51 of the first doping type in the epitaxial layer 20 on either side of the gate conductor 42; and a doped region 52 of the second doping type within the well region 51 of the first doping type.
In one embodiment, doped region 52 of the second doping type may serve as a source region for the device structure.
In one embodiment, the first doping type is P-type and the second doping type is N-type. In other embodiments, the first doping type may be N-type and the second doping type may be P-type.
The shielded gate trench MOSFET further includes an interlayer dielectric layer 60 on the epitaxial layer 20, the gate dielectric layer 41, and the gate conductor 42. The material of interlayer dielectric layer 60 includes, but is not limited to, silicon dioxide.
The shielded gate trench MOSFET further includes a contact hole 71 penetrating the interlayer dielectric layer 60, the doped region 52 of the second doping type and extending into the well region 51 of the first doping type, and a doped region 53 of the first doping type and a contact plug 72 located in the contact hole 71, wherein the doped region 53 of the first doping type is located at the bottom of the contact hole 71, and the contact plug 72 is located on the doped region 53 of the first doping type and fills the contact hole 71.
In one implementation, the ion concentration of doped region 53 of the first doping type is greater than the ion concentration of well region 51 of the first doping type. In this embodiment, by setting the ion concentration of the doped region 53 of the first doping type to be greater than that of the well region 51 of the first doping type, breakdown of the transistor under an inductive load can be prevented.
In one embodiment, the contact plug 72 may be a stacked structure, with the underlying material including but not limited to titanium nitride and the overlying material including but not limited to metallic titanium or metallic tungsten.
The shielded gate trench MOSFET also includes a metal layer 80 over the interlayer dielectric layer 60. The metal layer 80 is connected to the contact plug 72.
The embodiment of the disclosure also provides a preparation method of the shielded gate trench MOSFET, and the preparation method of the shielded gate trench MOSFET provided by the embodiment of the disclosure is further described in detail below with reference to specific embodiments. Fig. 2a to 2q are schematic diagrams of a shielded gate trench MOSFET according to an embodiment of the disclosure in a manufacturing process.
Figure 2a illustrates a schematic cross-sectional view after forming a first epitaxial layer and a mask layer in an embodiment of the present disclosure. Referring to fig. 2a, a first epitaxial layer 21 is formed on a substrate 10.
In an embodiment, the substrate 10 may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium substrate, etc.), or a silicon-on-insulator substrate (Silicon on Insulator, SOI), a germanium-on-insulator (Germanium on Insulator, GOI) substrate, etc. In an embodiment, the substrate 10 may have a first doping type, for example, the material of the substrate 10 may be a single crystal silicon substrate doped to an N-type.
The first epitaxial layer 21 may be a homoepitaxial layer or a heteroepitaxial layer, as the case may be. The first epitaxial layer 21 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Vapor Deposition, ALD), or other deposition methods.
The mask layer includes a hard mask layer 91 and photoresistThe mask layer 92 forms a hard mask layer 91 on the first epitaxial layer 21 after forming the first epitaxial layer 21. The hard mask layer 91 may be formed by an oxidation and chemical vapor deposition process. The oxidation process includes, but is not limited to: at least one of thermal oxidation, chemical vapor deposition, physical vapor deposition, and the like. Preferably a thermal oxidation process. The oxide may be silicon dioxide. The oxide may act as a hard mask layer 91 (HM). The hard mask layer 91 is an O-N-O stack, and in one embodiment, the O-N-O stack is SiO 2 -Si 3 N 4 -SiO 2 A laminated structure.
After forming the hard mask layer 91, a photoresist layer is formed on the hard mask layer 91. A spin-on process is used to form a photoresist mask layer 92. A first trench is etched in the first epitaxial layer 21 using the photoresist mask layer 92 and the hard mask layer 91 on the first epitaxial layer 21, see fig. 2b for a detailed description of the process.
Fig. 2b shows a schematic cross-sectional view after etching the first trench locations in an embodiment of the disclosure. Referring to fig. 2b, first, the photoresist mask layer 92 is patterned by photolithography to form first trench locations 211' on the photoresist mask layer 92. Etching the hard mask layer 91 transfers the first trench locations 211' onto the hard mask layer 91, removing the photoresist mask layer 92.
Fig. 2c is a schematic cross-sectional view of the embodiment of the disclosure after etching the first trench, please refer to fig. 2c, wherein the first epitaxial layer 21 is further etched by using the first trench position on the hard mask layer 91 to form a first trench 211 extending from the upper surface of the first epitaxial layer 21 to the inside thereof.
The etching process may be a wet etching process or a dry etching process. Preferably a dry etching process. The dry etching process includes, but is not limited to, at least one of ion milling etching, plasma etching, reactive ion etching, laser ablation.
After the first trench 211 is etched, the hard mask layer 91 is removed. In a specific embodiment, the hard mask layer 91 may be removed by a wet etching process.
Fig. 2d is a schematic cross-sectional view of the embodiment of the disclosure after forming the first dielectric layer, please refer to fig. 2d, in which a thin film growth process is used to grow Field Oxide (FOX) on the inner surface of the first trench 211 and the upper surface of the first epitaxial layer 21. Then, a normal pressure furnace tube process is adopted to deposit a certain thickness of ethyl silicate (TEOS) on the surface of the FOX. FOX and TEOS together serve as the first dielectric layer 311. The thickness of the first dielectric layer 311 is about 0.6 um. The film growth process comprises a thermal oxidation process, a chemical vapor deposition process and a physical vapor deposition process. In this step, a thermal oxidation process is preferable.
In the present disclosure, the first dielectric layer 311 covers the inner surface of the first trench 211 and the upper surface of the first epitaxial layer 21, and may play a role of isolation. The first dielectric layer 311 covering the upper surface of the first epitaxial layer 21 may be referred to as an oxide layer.
Fig. 2e shows a schematic cross-sectional view after forming a source conductor in an embodiment of the present disclosure. Referring to fig. 2e, in this step, a vapor deposition process is used to deposit a material into the first trench 211 along the notch of the first trench 211 until the deposited material covers the upper surface of the first dielectric layer 311.
Figure 2f illustrates a schematic cross-sectional view after etching away the source conductor over the first epitaxial layer in an embodiment of the present disclosure. Referring to fig. 2f, chemical Mechanical Polishing (CMP) is performed on the material deposited in the notch, and the polishing is stopped on the first dielectric layer 311 on the upper surface of the first epitaxial layer 21, so as to remove the material higher than the first dielectric layer 311, i.e. remove the redundant material. Among them, materials include, but are not limited to, polysilicon (POLY).
In this step, the polysilicon in the first trench 211 may be etched back, so that the height of the etched source conductor 32 is slightly lower than the upper surface of the first dielectric layer 311
The polysilicon deposited in the first trench 211 may serve as the source conductor 32 of a shielded gate trench MOSFET. The inner surface of the first trench 211 is covered with a first dielectric layer 311, and the first dielectric layer 311 forms a cavity around the first trench 211. The foregoing approach may be considered as an approach to depositing crystals within the cavity to form the source conductor 32. The first dielectric layer 311 may serve to isolate the source conductor 32 from the first epitaxial layer 21.
Fig. 2g illustrates a schematic cross-sectional view after forming a second dielectric layer in an embodiment of the present disclosure. Referring to fig. 2g, an oxidation process is used to oxidize the upper portion of the source conductor 32 in the first trench 211, so as to form a second dielectric layer 312 at the opening of the first trench 211. The second dielectric layer 312 is a bump structure, which plays a role in compression and voltage resistance when the shielded gate trench MOSFET is powered on. The oxidation process method used for oxidizing the upper portion of the source conductor 32 includes, but is not limited to: at least one of thermal oxidation, chemical vapor deposition, physical vapor deposition, and the like. Preferably a thermal oxidation process.
In one embodiment, the thickness of the second dielectric layer 312 is greater than the thickness of the portion of the first dielectric layer 311 on the upper surface of the first epitaxial layer 21.
As described above, the first dielectric layer 311 covers the inner wall of the first trench 211, the second dielectric layer 312 covers the opening of the first trench 211, and the source conductor 32 is wrapped, and the first dielectric layer 311 and the second dielectric layer 312 serve to isolate the source conductor 32 from the first epitaxial layer 21.
Figure 2h illustrates a schematic cross-sectional view of an embodiment of the present disclosure after etching away the first dielectric layer over the first epitaxial layer. Referring to fig. 2h, the first dielectric layer 311 over the first epi layer 21 is removed by chemical mechanical polishing, and a portion of the second dielectric layer 312 is removed.
In one embodiment, the upper surface of the second dielectric layer 312 is higher than the upper surface of the first dielectric layer 311. In this manner, the second dielectric layer 312 can better function to isolate the source conductor 32 from the subsequently formed gate conductor 42.
Figure 2i illustrates a schematic cross-sectional view after forming a second epitaxial layer in an embodiment of the present disclosure. Referring to fig. 2i, a second epitaxial layer 22 is formed on the first epitaxial layer 21, and the second epitaxial layer 22 covers the second dielectric layer 312.
The second epitaxial layer 22 may be a homoepitaxial layer or a heteroepitaxial layer, as the case may be. The second epitaxial layer 22 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Vapor Deposition, ALD), or other deposition methods.
In one implementation, the first epitaxial layer 21 and the second epitaxial layer 22 are formed as epitaxial layers 20.
Fig. 2j shows a schematic cross-sectional view after etching a second trench in an embodiment of the disclosure. Referring to fig. 2j, a second trench 221 is formed extending from the upper surface of the second epitaxial layer 22 to the second dielectric layer 312, and the second trench 221 exposes the second dielectric layer 312.
In this step, the process step of forming the second trench 221 is the same as the process step of forming the first trench 211, and the second trench 221 may be formed with reference to the process step of forming the first trench 211, which is not described herein.
In an embodiment, the first trench 211 and the second trench 221 are formed as the trench 201.
Fig. 2k illustrates a schematic cross-sectional view of forming a gate dielectric layer and a gate conductor in an embodiment of the disclosure. Referring to fig. 2k, in this step, a Field Oxide (FOX) is grown on the inner surface of the second trench 221 and the upper surface of the second epitaxial layer 22 by a thin film growth process. Then, a normal pressure furnace tube process is adopted to deposit a certain thickness of ethyl silicate (TEOS) on the surface of the FOX. FOX and TEOS together serve as gate dielectric layer 41. The film growth process comprises a thermal oxidation process, a chemical vapor deposition process and a physical vapor deposition process. In this step, a thermal oxidation process is preferable.
In the present disclosure, the gate dielectric layer 41 covers the inner surface of the second trench 221 and the upper surface of the second epitaxial layer 22, and may function as isolation. Wherein the second dielectric layer 41 covering the upper surface of the second epitaxial layer 22 may be regarded as an oxide layer.
With continued reference to fig. 2k, in this step, a vapor deposition process is used to deposit material into the second trench 221 along the notch of the second trench 221 until the deposited material covers the upper surface of the gate dielectric layer 41. Wherein the material includes, but is not limited to, polysilicon.
Figure 2l illustrates a schematic cross-sectional view of removing the gate dielectric layer and gate conductor over the second epitaxial layer in an embodiment of the present disclosure. Referring to fig. 2l, a chemical mechanical polishing process is used to remove the gate dielectric layer 41 and the gate conductor 42 above the second epitaxial layer 22, and the gate dielectric layer 41 and the gate conductor 42 in the second trench 221 are remained.
A gate dielectric layer 41 covers the inner surface of the second trench 221 to isolate the gate conductor 42 from the second epitaxial layer 22.
In one embodiment, first dielectric layer 311 and gate dielectric layer 41 are formed as peripheral dielectric layer 301, and peripheral dielectric layer 301 and second dielectric layer 312 are formed as dielectric layer 30.
Fig. 2m shows a schematic cross-sectional view of forming a well region of a first doping type in an embodiment of the disclosure. Referring to fig. 2m, in this step, a mask layer is formed on the second epitaxial layer 22, an opening pattern of the well region 51 of the first doping type is formed on the mask layer by a photolithography process, and then ions are implanted into the second epitaxial layer 22 under the opening pattern by an ion implantation process to form the well region 51 of the first doping type.
Fig. 2n shows a schematic cross-sectional view of forming a doped region of a second doping type in an embodiment of the disclosure. Referring to fig. 2n, in this step, a mask layer is formed on the second epitaxial layer 22, an opening pattern of a doped region 52 of a second doping type is formed on the mask layer by a photolithography process, and then ions are implanted into the well region 51 of the first doping type under the opening pattern by an ion implantation process to form the doped region 52 of the second doping type.
In one embodiment, doped region 52 of the second doping type may serve as a source region for the device structure.
In one embodiment, the first doping type is P-type and the second doping type is N-type. In other embodiments, the first doping type may be N-type and the second doping type may be P-type.
Fig. 2o shows a schematic cross-sectional view of a contact hole etched in an embodiment of the disclosure. Referring to fig. 2o, an interlayer dielectric layer 60 is formed to cover the second epitaxial layer 22, the gate dielectric layer 41 and the gate conductor 42.
Interlayer dielectric layer 60 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Vapor Deposition, ALD), or other deposition methods. The material of interlayer dielectric layer 60 includes, but is not limited to, silicon dioxide.
With continued reference to fig. 2o, a contact hole 71 is formed through the interlayer dielectric layer 60, the doped region 52 of the second doping type, and extending into the well region 51 of the first doping type.
In this step, a mask layer is formed on the interlayer dielectric layer 60, an opening pattern of the contact hole 71 is formed on the mask layer by a photolithography process, and then the interlayer dielectric layer 60, the doped region 52 of the second doping type and a part of the doped region 51 of the first doping type under the opening pattern are removed by etching to form the contact hole 71.
The etching process may be a wet etching process or a dry etching process. Preferably a dry etching process. The dry etching process includes, but is not limited to, at least one of ion milling etching, plasma etching, reactive ion etching, laser ablation.
Fig. 2p shows a schematic cross-sectional view of forming a doped region of a first doping type in an embodiment of the disclosure. Referring to fig. 2p, a doped region 53 of a first doping type is formed at the bottom of the contact hole 71, wherein the ion concentration of the doped region 53 of the first doping type is greater than that of the well region 51 of the first doping type.
In this embodiment, by setting the ion concentration of the doped region 53 of the first doping type to be greater than that of the well region 51 of the first doping type, breakdown of the transistor under an inductive load can be prevented.
Fig. 2q illustrates a schematic cross-sectional view of forming a contact plug and a metal layer in an embodiment of the present disclosure. Referring to fig. 2q, after forming the doped region 53 of the first doping type, a contact plug 72 filling the contact hole 71 is formed; a metal layer 80 is formed on the interlayer dielectric layer 60, and the metal layer 80 is connected to the contact plug 72.
The contact plugs 72 and the metal layer 80 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Vapor Deposition, ALD), or other deposition methods.
The contact plug 72 may be a stacked structure, with the underlying material including but not limited to titanium nitride and the overlying material including but not limited to metallic titanium or metallic tungsten.
In the embodiment of the disclosure, the first grooves in the first epitaxial layer are all used for forming the source electrode conductor, then a second epitaxial layer is formed, and the second grooves in the second epitaxial layer are used for forming the gate electrode conductor, so that the depth-to-width ratio of a single step process is reduced, SGT devices with high depth-to-width ratio shielding gate structures are prepared under the same machine capability, and the voltage resistance of the devices is greatly improved; in the traditional process, only one groove is etched, and a shielding gate and a gate conductor are sequentially formed in the groove, so that the depth of the gate conductor greatly influences the depth-to-width ratio of the shielding gate, and the voltage resistance of the device cannot be improved.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A method for manufacturing a shielded gate trench MOSFET, the method comprising:
forming a first epitaxial layer on a substrate;
forming a first trench extending from an upper surface of the first epitaxial layer to an interior thereof;
forming a source dielectric layer and a source conductor in the first groove, wherein the source dielectric layer comprises a first dielectric layer covering the inner wall of the first groove and a second dielectric layer at the opening of the first groove, and the source conductor is positioned in a cavity formed by the source dielectric layer around the first groove and is isolated from the first epitaxial layer through the source dielectric layer;
forming a second epitaxial layer on the first epitaxial layer, wherein the second epitaxial layer covers the second dielectric layer;
forming a second trench extending from the upper surface of the second epitaxial layer to the second dielectric layer, the second trench exposing the second dielectric layer;
and forming a gate dielectric layer and a gate conductor in the second trench, wherein the gate dielectric layer covers the inner surface of the second trench so as to isolate the gate conductor from the second epitaxial layer.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the forming a source dielectric layer and a source conductor in the first trench includes:
forming a first dielectric layer covering the inner wall of the first groove and the upper surface of the first epitaxial layer;
forming a source conductor which covers the surface of the first dielectric layer and is filled in the first groove;
the source conductor located above the first epitaxial layer is removed, and the source conductor located in the first trench is reserved.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the forming the source dielectric layer and the source conductor in the first trench further includes:
oxidizing the upper part of the source electrode conductor by adopting an oxidation process to form the second dielectric layer positioned at the opening of the first groove;
and removing the first dielectric layer above the first epitaxial layer, reserving the first dielectric layer in the first groove, combining the first dielectric layer with the second dielectric layer to form the source dielectric layer, and wrapping the source conductor by the source dielectric layer.
4. The method of claim 3, wherein the step of,
the upper surface of the second dielectric layer is higher than the upper surface of the first dielectric layer.
5. The method of claim 3, wherein the step of,
the thickness of the second dielectric layer is larger than that of the part of the first dielectric layer, which is positioned on the upper surface of the first epitaxial layer.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the forming a gate dielectric layer and a gate conductor in the second trench includes:
forming a gate dielectric layer covering the inner surface of the second trench and the upper surface of the second epitaxial layer;
forming a gate conductor covering the surface of the gate dielectric layer and filling the second trench;
and removing the gate dielectric layer and the gate conductor which are positioned above the second epitaxial layer, and reserving the gate dielectric layer and the gate conductor which are positioned in the second groove.
7. The method according to claim 1, wherein the method further comprises:
after the gate conductor is formed, forming a well region of a first doping type in the second epitaxial layer at two sides of the gate conductor;
and forming a doped region of a second doping type in the well region of the first doping type.
8. The method of claim 7, wherein the method further comprises:
forming an interlayer dielectric layer covering the second epitaxial layer, the gate dielectric layer and the gate conductor;
forming a contact hole penetrating the interlayer dielectric layer, the doped region of the second doping type and extending into the well region of the first doping type;
and forming a doped region of a first doping type at the bottom of the contact hole, wherein the ion concentration of the doped region of the first doping type is larger than that of the well region of the first doping type.
9. The method of claim 8, wherein the method further comprises:
forming a contact plug filling the contact hole after forming the doped region of the first doping type;
and forming a metal layer on the interlayer dielectric layer, wherein the metal layer is connected with the contact plug.
10. A shielded gate trench MOSFET comprising:
a substrate;
an epitaxial layer on the first surface of the substrate, the epitaxial layer having a trench therein;
the dielectric layer is positioned in the groove and comprises a peripheral dielectric layer and a second dielectric layer, the peripheral dielectric layer covers the inner wall of the groove, the second dielectric layer is transversely arranged in the groove so as to divide the groove into an upper cavity and a lower cavity from top to bottom, and the second dielectric layer is arranged to protrude towards one side of the upper cavity;
the source conductor and the gate conductor are positioned in the groove, wherein the source conductor is positioned in the lower cavity, the gate conductor is positioned in the upper cavity, and the gate conductor is exposed at the upper part of the groove.
CN202311449820.4A 2023-11-01 2023-11-01 Preparation method of shielded gate trench MOSFET and shielded gate trench MOSFET Pending CN117276081A (en)

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