CN117275395A

CN117275395A - Shift register unit, display driving circuit and display panel

Info

Publication number: CN117275395A
Application number: CN202311271880.1A
Authority: CN
Inventors: 袁志东; 李永谦
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2023-09-27
Filing date: 2023-09-27
Publication date: 2023-12-22

Abstract

A shift register unit, a display driving circuit, and a display panel are provided. The shift register unit comprises an input circuit, a pull-up circuit, a pull-down circuit, a cascade output circuit and a signal output circuit, wherein the signal output circuit is connected with K clock signal ends and K output signal ends of the shift register unit and is used for generating K driving signals required for driving the sub-pixels, the duty ratios of signals output by at least two of the K output signal ends are different, the K driving signals comprise grid driving signals and luminous control signals, K is an integer larger than 1, and at least one output unit is used for providing the signal of one of the connected clock signal ends and power signal ends to the connected output signal ends under the control of a pull-up node and a pull-down node; at least another output unit is for providing a signal of one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under control of the pull-up node and the pull-down node.

Description

Shift register unit, display driving circuit and display panel

Technical Field

The disclosure relates to the technical field of display, in particular to a shift register unit, a display driving circuit and a display panel.

Background

A plurality of sub-pixels and driving circuits for driving the sub-pixels are provided in the display panel, and a single sub-pixel generally requires a plurality of driving signals, each of which is provided by a separate driving circuit. But this design is disadvantageous for a narrow bezel and low cost.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a shift register unit including:

an input circuit connected to an input signal terminal of the shift register unit for inputting a signal of the input signal terminal to the pull-up node;

a pull-up circuit connected to the input signal terminal and a pull-down node of the shift register unit for pulling up a potential of the pull-down node based on a potential of the input signal terminal;

a pull-down circuit connected to the pull-up node and the pull-down node for pulling down the potential of the pull-down node based on the potential of the pull-up node;

a cascade output circuit connected to the power signal terminal, the reference signal terminal, and the cascade output terminal of the shift register unit, and configured to supply a signal of one of the power signal terminal and the reference signal terminal to the cascade output terminal under control of the pull-up node and the pull-down node; and

The signal output circuit is connected with K clock signal ends and K output signal ends of the shift register unit and is used for generating K driving signals required for driving the sub-pixels, the duty ratios of signals output by at least two of the K output signal ends are different, the K driving signals comprise a grid driving signal and a light emitting control signal, wherein K is an integer larger than 1,

the signal output circuit comprises K output units, wherein the kth output unit is connected to the pull-up node, the pull-down node, a kth clock signal end and a kth output signal end, and K is more than or equal to 1 and less than or equal to K;

the at least one output unit is also connected with a power signal end and is used for providing a signal of one of the connected clock signal end and the power signal end to the connected output signal end under the control of the pull-up node and the pull-down node;

wherein at least one further output unit is further connected to a reference signal terminal for providing a signal of one of the connected clock signal terminal and reference signal terminal to the connected output signal terminal under control of the pull-up node and the pull-down node.

For example, each output unit comprises a first output sub-circuit and a second output sub-circuit, each of the first and second output sub-circuits having a control terminal, an input terminal and an output terminal and being arranged to provide a signal of the input terminal to the output terminal under control of the control terminal;

Wherein:

the control end of the first output sub-circuit is connected with the first pull-up node, the input end of the first output sub-circuit is connected with the corresponding clock signal end, and the output end of the first output sub-circuit is connected with the corresponding output signal end;

the control end of the second output sub-circuit is connected with the pull-down node, the input end of the second output sub-circuit is connected with the power signal end and/or the reference signal end, and the output end of the second output sub-circuit is connected with the corresponding output signal end.

For example, the first output sub-circuit includes a first transistor and a first capacitor, the gate of the first transistor is used as the control end of the first output sub-circuit, the first pole of the first transistor is used as the input end of the first output sub-circuit, the second pole of the first transistor is used as the output end of the output sub-circuit, the first pole of the first capacitor is connected with the gate of the first transistor, and the second pole of the first capacitor is connected with the second pole of the first transistor;

the second output sub-circuit comprises a second transistor, wherein the grid electrode of the second transistor is used as the control end of the second output sub-circuit, the first electrode of the second transistor is used as the input end of the second output sub-circuit, and the second electrode of the second transistor is used as the output end of the second output sub-circuit.

For example, one of the K clock signal terminals is electrically connected to a power signal terminal.

For example, the cascade output circuit includes:

the first cascade sub-circuit is connected to the pull-up node, the power supply signal end and the cascade output end and is used for providing signals of the power supply signal end to the cascade output end under the control of the pull-up node;

and the second cascade subcircuit is connected to the pull-down node, the reference signal terminal and the cascade output terminal and is used for providing the signal of the reference signal terminal to the cascade output terminal under the control of the pull-down node.

For example, the first cascade sub-circuit includes a third transistor and a second capacitor, wherein a gate of the third transistor is connected to the pull-up node, a first pole of the third transistor is connected to the power signal terminal, a second pole of the third transistor is connected to the cascade output terminal, a first pole of the second capacitor is connected to the gate of the third transistor, and a second pole of the second capacitor is connected to the second pole of the third transistor;

the second cascade subcircuit comprises a fourth transistor and a third capacitor, wherein a grid electrode of the fourth transistor is connected with the pull-down node, a first electrode of the fourth transistor is connected with the reference signal end, a second electrode of the fourth transistor is connected with the cascade output end, a first electrode of the third capacitor is connected with the grid electrode of the fourth transistor, and a second electrode of the third capacitor is connected with the second electrode of the fourth transistor.

For example, the second cascode sub-circuit further includes a fifth transistor and a sixth transistor,

the second pole of the fourth transistor is connected to the cascade output terminal through the fifth transistor, wherein the first pole of the fifth transistor is connected to the second pole of the fourth transistor, the second pole of the fifth transistor is connected to the cascade output terminal, and the gate of the fifth transistor is connected to the pull-down node;

and a grid electrode of the sixth transistor is connected with the cascade output end, a first electrode of the sixth transistor is connected with the power supply signal end, and a second electrode of the sixth transistor is connected with the pull-up node.

For example, the power signal terminals include a first power signal terminal and a second power signal terminal, and the reference signal terminal includes a first reference signal terminal and a second reference signal terminal;

the cascade output circuit is connected with the first power supply signal end and the first reference signal end, and the signal output circuit is connected with the second power supply signal end and the second reference signal end.

For example, the pull-up circuit includes:

a first control sub-circuit connected to the input signal terminal, the power supply signal terminal, and a second control signal terminal and an intermediate node of the shift register unit, for controlling a potential of the intermediate node based on signals of the input signal terminal and the second control signal terminal;

And a second control sub-circuit connected to the intermediate node, the pull-down node, and a first control signal terminal of the shift register unit for pulling up a potential of the pull-down node based on signals of the intermediate node and the first control signal terminal.

For example, the first control sub-circuit includes a seventh transistor and an eighth transistor, wherein a gate of the seventh transistor is connected to the second control signal terminal, a first pole of the seventh transistor is connected to the power signal terminal, a second pole of the seventh transistor is connected to the intermediate node, a gate of the eighth transistor is connected to the input signal terminal, a first pole of the eighth transistor is connected to the second control signal terminal, and a second pole of the eighth transistor is connected to the intermediate node;

the second control sub-circuit comprises a ninth transistor, a tenth transistor and a fourth capacitor, wherein the grid electrode of the ninth transistor is connected with the intermediate node, the first pole of the ninth transistor is connected with the first control signal end, the second pole of the ninth transistor is connected with the first pole of the tenth transistor, the grid electrode of the tenth transistor is connected with the first control signal end, the second pole of the tenth transistor is connected with the pull-down node, the first pole of the fourth capacitor is connected with the grid electrode of the ninth transistor, and the second pole of the fourth capacitor is connected with the second pole of the ninth transistor.

For example, the first control sub-circuit further includes an eleventh transistor and a twelfth transistor,

a first pole of the eighth transistor is connected to the second control signal terminal through the eleventh transistor, a gate of the eleventh transistor is connected to the input signal terminal, a first pole of the eleventh transistor is connected to the second control signal terminal, and a second pole of the eleventh transistor is connected to the first pole of the eighth transistor;

the gate of the twelfth transistor is connected to the intermediate node, the first pole of the twelfth transistor is connected to the power signal terminal, and the second pole of the twelfth transistor is connected to the first pole of the eighth transistor.

For example, the pull-down circuit includes a thirteenth transistor having a gate connected to the pull-up node, a first pole connected to the reference signal terminal, and a second pole connected to the pull-down node.

For example, the input circuit includes a fourteenth transistor, a gate of the fourteenth transistor is connected to the first control signal terminal of the shift register unit, a first pole of the fourteenth transistor is connected to the input signal terminal, and a second pole of the fourteenth transistor is connected to the pull-up node.

For example, the input circuit further includes a fifteenth transistor, a second pole of the fourteenth transistor is connected to the pull-up node through the fifteenth transistor, wherein a gate of the fifteenth transistor is connected to the power supply signal terminal or the first control signal terminal, a first pole of the fifteenth transistor is connected to the second pole of the fourteenth transistor, and a second pole of the fifteenth transistor is connected to the pull-up node.

For example, the shift register unit further includes: and the reset circuit is connected with the pull-up node, the pull-down node, the power signal end, the reference signal end and the reset signal end of the shift register unit and is used for providing the signal of the reference signal end to the pull-up node and providing the signal of the power signal end to the pull-down node under the control of the reset signal end.

For example, the reset circuit includes:

a sixteenth transistor, a gate of the sixteenth transistor is connected to the reset signal terminal, a first pole of the sixteenth transistor is connected to the reference signal terminal, and a second pole of the sixteenth transistor is connected to the pull-up node;

A seventeenth transistor, a gate of the seventeenth transistor is connected to the reset signal terminal, a first pole of the seventeenth transistor is connected to the power signal terminal, and a second pole of the seventeenth transistor is connected to the pull-down node.

For example, the reset circuit further includes an eighteenth transistor, a first pole of the sixteenth transistor is connected to the reference signal terminal through the eighteenth transistor, a gate of the eighteenth transistor is connected to the reset signal terminal, a first pole of the eighteenth transistor is connected to the reference signal terminal, and a second pole of the eighteenth transistor is connected to the first pole of the sixteenth transistor.

For example, k=4, wherein one or two output units are configured to supply a signal of one of the connected clock signal terminal and the power signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node, and the other output units are configured to supply a signal of one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

For example, k=3, wherein one of the output units is configured to supply a signal of one of the connected clock signal terminal and power signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node; the other output unit is configured to supply a signal of one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

For example, the signal output circuit is used to generate some or all of K driving signals required to drive a single sub-pixel.

According to another aspect of the present disclosure, there is provided a display driving circuit, including N shift register units connected in cascade, the shift register units being shift register units as described above, wherein a cascade output terminal of an N-th shift register unit is connected to an input signal terminal of an n+i-th shift register unit, wherein N, N and i are both positive integers, and N < N.

For example, the display driving circuit receives M narrow clock signals and M wide clock signals sequentially shifted, the narrow clock signals and the wide clock signals having the same period, a duty ratio of the narrow clock signals being smaller than a duty ratio of the wide clock signals, where M is an integer multiple of K;

the N shift register units are divided into at least one group, each group comprises M shift register units which are connected in a cascade mode, M kth 1 clock signal ends of each group of shift register units are configured to respectively receive the M narrow clock signals, M kth 2 clock signal ends of each group of shift register units are configured to respectively receive the M wide clock signals, k1 and k2 are positive integers, k1 is less than or equal to N, k2 is less than or equal to 1 is less than or equal to N, and k1 is not equal to k2.

For example, k=4, i=1, m=4;

the first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second, third, fourth and first narrow clock signals, respectively;

the second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the first, second, third and fourth narrow clock signals, respectively;

the third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the first wide clock signal, the second wide clock signal, the third wide clock signal and the fourth wide clock signal, respectively;

the fourth clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the third narrow clock signal, the fourth narrow clock signal, the first narrow clock signal, and the second narrow clock signal, respectively.

For example, k=4, i=1, m=4;

the first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the fourth wide clock signal, a wide clock signal, the second wide clock signal and the third wide clock signal, respectively;

The second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second wide clock signal, the third wide clock signal, the fourth wide clock signal and the first wide clock signal, respectively;

For example, k= 3,i =1, m=4;

the first clock signal ends of the first to fourth stage shift register units in each group are configured to be connected with a third narrow clock signal, a fourth narrow clock signal, a first narrow clock signal and a second narrow clock signal respectively;

the third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second, third, fourth and first narrow clock signals, respectively.

For example, k=4, i=1, m=8;

the first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive 8 wide clock signals sequentially shifted from the second wide clock signal, respectively;

the second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive 8 narrow clock signals sequentially shifted from the seventh narrow clock signal, respectively;

the third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive 8 narrow clock signals sequentially shifted from the first narrow clock signal, respectively;

the fourth clock signal terminal of the first to fourth stage shift register units in each group is electrically connected to the power signal terminal and configured to receive a power signal.

For example, k=4, i=1, m=16;

the first clock signal terminals of the first to sixteenth stage shift register units in each group are configured to receive 16 wide clock signals sequentially shifted from the third wide clock signal, respectively;

the second clock signal terminals of the first to sixteenth stage shift register units in each group are configured to receive 16 narrow clock signals sequentially shifted from the fourteenth narrow clock signal, respectively;

The third clock signal terminals of the first to sixteenth stage shift register units in each group are configured to receive 16 wide clock signals sequentially shifted from the first wide clock signal, respectively;

the fourth clock signal terminals of the first to sixteenth stage shift register units in each group are configured to receive 16 narrow clock signals sequentially shifted from the first narrow clock signal, respectively.

Embodiments of the present disclosure also provide a display panel including a display driving circuit as described above and a plurality of subpixels arranged in an array, the display driving circuit being connected with the plurality of subpixels to provide display driving signals to the plurality of subpixels.

For example, K output signal terminals of the nth stage shift register unit are connected to the nth row of sub-pixels to supply K display driving signals including a gate driving signal and a light emission control signal required to drive the row of sub-pixels to the nth row of sub-pixels.

For example, the K1 output signal terminals of the n-th stage shift register unit and the K2 output signal terminals of the n+j-th stage shift register unit are connected to the n-th row of sub-pixels to supply K display driving signals to the n-th row of sub-pixels, wherein k1+k2=k, j is an integer greater than 1.

Drawings

Fig. 1A shows a circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 1B shows a timing diagram of the drive signals of the pixel circuit of FIG. 1A;

fig. 2A shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 2B shows a timing diagram of the drive signals of the pixel circuit of FIG. 2A;

fig. 3A shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

FIG. 3B shows a timing diagram of the drive signals of the pixel circuit of FIG. 3A;

FIG. 4 shows a schematic block diagram of a shift register cell according to an embodiment of the present disclosure;

FIG. 5 shows a schematic block diagram of a shift register cell according to another embodiment of the present disclosure;

fig. 6 shows a circuit diagram of a shift register cell according to an embodiment of the present disclosure;

fig. 7 shows a circuit diagram of a shift register cell according to another embodiment of the present disclosure.

Fig. 8 shows a circuit diagram of a shift register cell according to another embodiment of the present disclosure.

FIG. 9A shows a schematic diagram of a display drive circuit according to an embodiment of the present disclosure;

FIG. 9B shows a signal timing diagram of the display driver circuit of FIG. 9A;

FIG. 10A shows a schematic diagram of a display drive circuit according to another embodiment of the present disclosure;

FIG. 10B shows a signal timing diagram of the display driving circuit of FIG. 10A;

FIG. 11A shows a schematic diagram of a display drive circuit according to another embodiment of the present disclosure;

FIG. 11B shows a signal timing diagram of the display driver circuit of FIG. 11A;

FIG. 12A shows a schematic diagram of a display drive circuit according to another embodiment of the present disclosure;

FIG. 12B shows a signal timing diagram of the display driver circuit of FIG. 12A;

fig. 13A and 13B show schematic diagrams of a display driving circuit according to another embodiment of the present disclosure;

fig. 13C shows a signal timing diagram of the display driving circuit of fig. 13A and 13B;

FIG. 14 shows a schematic view of a display panel according to an embodiment of the disclosure;

fig. 15 shows a schematic view of a display panel according to another embodiment of the present disclosure.

Detailed Description

While the present disclosure will be fully described with reference to the accompanying drawings, which contain preferred embodiments of the present disclosure, it is to be understood before this description that one of ordinary skill in the art can modify the disclosure described herein while achieving the technical effects of the present disclosure. Accordingly, it is to be understood that the foregoing description is a broad disclosure by those having ordinary skill in the art, and is not intended to limit the exemplary embodiments described in the present disclosure.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in the drawings in order to simplify the drawings.

Fig. 1A shows a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

As shown in fig. 1A, the pixel circuit 10A of the sub-pixel may include a light emitting unit EL and a pixel driving circuit for driving the light emitting unit EL to emit light. According to an embodiment of the present disclosure, the pixel driving circuit may include an input sub-circuit, a driving sub-circuit, a compensation sub-circuit, and a light emission control sub-circuit. In fig. 1A, the driving sub-circuit includes a driving transistor DTFT and a capacitance Cst. The input subcircuit includes a transistor M1. The compensation subcircuit includes transistors M2 and M3. The light emission control sub-circuit includes a transistor M4. The light emitting unit EL may be a light emitting diode, for example, an organic light emitting diode OLED. The gate of the transistor M1 receives the first gate driving signal G1, the first pole receives the DATA signal DATA, and the second pole is connected to the gate G of the driving transistor DTFT. The gate of the transistor M2 receives the second gate driving signal G2, the first pole receives the initial voltage VIN2, and the second pole is connected to the gate of the driving transistor DTFT. The gate of the transistor M3 receives the third gate driving signal G3, the first pole receives the initial voltage VIN1, and the second pole is connected to the source of the driving transistor DTFT. The gate of the transistor M4 receives the emission control signal EM, the first pole receives the power supply voltage VDD, and the second pole is connected to the drain D of the driving transistor DTFT. The source S of the driving transistor DTFT is connected to a first pole of the light emitting unit EL, and a second pole of the light emitting unit EL receives the reference voltage VSS.

The driving signals of the pixel circuit of the above-described embodiment include the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, and the emission control signal EM. In other words, the pixel circuits emit light under the control of these driving signals. This will be described in detail below with reference to fig. 1B.

As shown in fig. 1B, in the period P1, the first gate driving signal G1 is at a low level, the second gate driving signal G2 and the third gate driving signal G3 are at a high level, and the crystals M2 and M3 are turned on, thereby providing the initial voltage VIN2 to the gate G of the driving transistor DTFT and providing the initial voltage VIN1 to the source S of the driving transistor DTFT.

In the period P2, the third gate driving signal G3 becomes a low level, the transistor M3 is turned off, and the source S of the driving transistor DTFT is charged until the potential difference between the gate G and the source S of the driving transistor DTFT is equal to the threshold voltage of the driving transistor DTFT, thereby realizing the compensation of the threshold voltage.

In the period P3, the second gate driving signal G2 becomes low level, the first gate driving signal G1 becomes high level, the light emission control signal EM becomes low level, the transistors M2 and M4 are turned off, and the transistor M1 is turned on, so that the DATA signal DATA is written to the gate G of the driving transistor DTFT.

In the period P4, the first to third gate driving signals G1, G2, G3 are all low level, the emission control signal EM is high level, the transistor M4 is turned on, and the driving transistor DTFT generates a driving current by the data signal at the gate G, thereby driving the light emitting unit EL to emit light. Thus, the display driving of the pixel circuit is completed.

In the example of fig. 1B, the emission control signal EM remains at a high level for the periods P1 to P2, and the transistor M4 is in an on state. However, the embodiments of the present disclosure are not limited thereto, and the light emission control signal EM may also be always low level in the periods P1 to P2, or switched between high level and low level, as long as the light emission driving is not affected.

Fig. 2A shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

The pixel circuit 10B of fig. 2A also includes a light emitting unit EL and a pixel driving circuit for driving the light emitting unit EL to emit light. The pixel driving circuit may include an input sub-circuit, a driving sub-circuit, a compensation sub-circuit, and a light emission control sub-circuit. In the example of fig. 2A, the input subcircuit includes a transistor M1. The driving sub-circuit comprises a driving transistor DTFT and a capacitor C2. The compensation subcircuit includes transistors M2 and M3 and a capacitor C1. The light emission control sub-circuit includes transistors M4 and M5.

The gate of the transistor M1 receives the first gate driving signal G1, the first pole receives the DATA signal DATA, and the second pole is connected to the source of the driving transistor DTFT. The gate of the transistor M2 receives the second gate driving signal G2, the first pole is connected to the drain of the driving transistor DTFT, and the second pole is connected to the gate of the driving transistor DTFT. The gate of the transistor M3 receives the second gate driving signal G2, and the first electrode receives the initial voltage VINI. A first pole of the capacitor C2 is connected to the gate of the driving transistor DTFT, and a second pole of the capacitor C2 is connected to the second pole of the transistor M3. The first pole of the capacitor C1 receives the first gate driving signal G1, and the second pole is connected to the first pole of the light emitting unit EL. The gate of the transistor M4 receives the first light emitting control signal EM1, the first pole receives the power voltage VDD, and the second pole is connected to the drain of the driving transistor DTFT. The gate of the transistor M5 receives the second emission control signal EM2, the first pole is connected to the source of the driving transistor DTFT, and the second pole is connected to the first pole of the light emitting unit EL. The second pole of the light emitting unit EL is connected to the reference voltage VSS.

The driving signals of the pixel circuit of the above-described embodiment include the first gate driving signal G1, the second gate driving signal G2, the first light emission control signal EM1, and the second light emission control signal EM2. In other words, the pixel circuits emit light under the control of these driving signals. This will be described in detail below with reference to fig. 2B.

As shown in fig. 2B, in the period P1, the first gate driving signal G1 and the second light emission control signal EM2 are at low level, the second gate driving signal G2 and the first light emission control signal EM1 are at high level, the transistors M2, M3 and M4 are turned on, the initial voltage VINI is written to the first electrode of the light emitting unit EL, and the power supply voltage VDD is written to the gate of the driving transistor DTFT.

In the period P2, the first gate driving signal G1 becomes high level, the first light emitting control signal EM1 becomes low level, and the transistor M1 is turned on, thereby writing the DATA signal DATA to the drain S of the driving transistor DTFT. Transistors M4 and M5 are in an off state, thereby completing the threshold voltage compensation of the driving transistor DTFT.

In the period P3, the first and second gate driving signals G1 and G2 become low level, the first and second light emission control signals EM1 and EM2 become high level, the transistors M1 to M3 are turned off, the transistors M4 and M5 are turned on, and the driving transistor DTFT generates a driving current by the gate voltage thereof, thereby driving the light emitting unit EL to emit light.

The pixel circuit 10C of fig. 3A also includes a light emitting unit EL and a pixel driving circuit for driving the light emitting unit EL to emit light. The pixel driving circuit may include an input sub-circuit, a driving sub-circuit, a compensation sub-circuit, and a light emission control sub-circuit. In the example of fig. 3A, the input subcircuit includes a transistor M1. The driving sub-circuit includes a driving transistor DTFT and a capacitor C1. The compensation subcircuit includes a transistor M2 and a capacitor C2. The light emission control sub-circuit includes a transistor M3. The gate of the transistor M1 receives the first gate driving signal G1. A first pole of the transistor M1 receives the DATA signal DATA. The second pole of the transistor M1 is connected to the gate G of the driving transistor DTFT. The gate of the transistor M2 receives the second gate driving signal G2, the first pole of the transistor M2 receives the initial voltage V1NI, and the second pole of the transistor M2 is connected to the source S of the driving transistor DTFT. The gate of the transistor M3 receives the emission control signal EM, the first pole of the transistor M3 receives the power supply voltage ELVDD, and the second pole of the transistor M3 is connected to the drain D of the driving transistor DTFT. The first pole of the capacitor C1 is connected to the gate of the driving transistor DTFT, and the second pole is connected to the drain S of the driving transistor DTFT. The first pole of the capacitor C2 is connected to the drain S of the driving transistor DTFT, and the second pole receives the power supply voltage ELVDD. The first pole of the light emitting unit EL is connected to the source of the driving transistor DTFT, and the second pole is connected to the reference voltage ELVSS.

The driving signals of the pixel circuit of the above-described embodiment include the first gate driving signal G1, the second gate driving signal G2, and the emission control signal EM. In other words, the pixel circuits emit light under the control of these driving signals. This will be described in detail below with reference to fig. 3B.

As shown in fig. 3B, in the period P1, the first gate driving signal G1 and the second gate driving signal G2 are at a high level, the DATA signal DATA is at a reference level, the light emission control signal EM is at a low level, the transistors M1 and M2 are turned on, the reference level Vref of the DATA signal DATA is written to the gate G of the driving transistor DTFT, and the initial voltage VINI is written to the source S of the driving transistor DTFT.

In the period P2, the second gate driving signal G2 becomes low level, the emission control signal EM becomes high level, the transistor M1 is kept on, the transistor M2 is turned off, the potential of the source S of the driving transistor DTFT starts to rise until the potential difference between the gate G and the source S of the driving transistor DTFT is equal to the threshold voltage Vth of the driving transistor DTFT, and the driving transistor DTFT is turned off.

In the period P3, the emission control signal EM becomes a low level, and the DATA signal DATA becomes a DATA voltage. The different data voltages cause the driving transistors DTFT to generate corresponding driving currents to drive the corresponding light emitting units EL to display in corresponding gray scale, and the light emitting units EL may be one of red, blue and green, so the data voltages are indicated by R, G, B in fig. 3B. The data voltage Vref changes the potential of the gate G of the driving transistor DTFT (gradually increases in fig. 3B), and the presence of the capacitor C1 changes the potential of the source S of the driving transistor DTFT accordingly (also increases in fig. 3B) so that the potential difference between the gate G and the source S is maintained at Vth.

In the period P4, the light emission control signal EM becomes high level, the first gate driving signal G1 becomes low level, the transistor M1 is turned off, the transistor M3 is turned on, and the driving transistor DTFT generates a driving current driven by the voltage of the gate G thereof, thereby driving the light emitting unit EL to emit light.

Embodiments of the present disclosure also provide a shift register unit that may provide gate drive signals and emission control signals required to drive a subpixel, for example, all or part of the drive signals required for the pixel circuits of any of the embodiments described above. Although the pixel circuits of the above embodiments are implemented based on N-type transistors, embodiments of the present disclosure are not limited thereto, and the shift pixel unit of the embodiments of the present disclosure is also applicable to generating a required driving signal to a sub-pixel having other pixel circuit structures. Embodiments of the shift register unit will be described below with reference to fig. 4 to 8.

Fig. 4 shows a schematic block diagram of a shift register cell according to an embodiment of the present disclosure.

As shown in fig. 4, the shift register unit includes an input circuit 110, a pull-up circuit 120, a pull-down circuit 130, a cascade output circuit 140, and a signal output circuit 150.

The input circuit 110 is connected to the input signal terminal IN of the shift register unit. The input circuit 110 may input a signal of the input signal terminal IN to the pull-up node Q.

The pull-up circuit 120 is connected to the input signal terminal IN and the pull-down node QB of the shift register unit. The pull-up circuit 120 may pull up the potential of the pull-down node QB based on the potential of the input signal terminal IN.

The pull-down circuit 130 is connected to the pull-up node Q and the pull-down node QB. The pull-down circuit 130 may pull down the potential of the pull-down node QB based on the potential of the pull-up node Q.

The cascade output circuit 140 is connected to the pull-up node Q, the pull-down node QB, and the power signal terminal GVDD, the reference signal terminal VGL, and the cascade output terminal CR of the shift register unit. The cascade output circuit 140 may supply a signal of one of the power signal terminal GVDD and the reference signal terminal VGL to the cascade output terminal CR under the control of the pull-up node Q and the pull-down node QB.

The signal output circuit 150 connects K clock signal terminals and K output signal terminals of the shift register unit. The signal output circuit 150 may generate K driving signals required to drive the sub-pixels, and at least two of the K output signal terminals have different duty ratios, where K is an integer greater than 1, and the K driving signals include a gate driving signal and a light emission control signal. For example, the signal output circuit 150 may include K output units respectively connected to K clock signal terminals.

In fig. 4, for convenience of description, k=3 is illustrated as an example. However, embodiments of the present disclosure are not limited thereto, and the number of output units may be selected as needed.

As shown in fig. 4, the signal output circuit 150 includes a first output unit 150_1, a second output unit 150_2, and a third output unit 150_3, which are connected to the first clock signal terminal CLK1, the second clock signal terminal CLK2, and the third clock signal terminal CLK3, respectively.

The kth output unit is connected to the pull-up node Q, the pull-down node QB, the kth clock signal terminal and the kth output signal terminal, wherein K is greater than or equal to 1 and less than or equal to K. For example, in fig. 4, the first output unit 150_1 is connected to the pull-up node Q, the pull-down node QB, the first clock signal terminal CLK1, and the first output signal terminal OUT1, the second output unit 150_2 is connected to the pull-up node Q, the pull-down node QB, the second clock signal terminal CLK2, and the second output signal terminal OUT2, and the third output unit 150_3 is connected to the pull-up node Q, the pull-down node QB, the third clock signal terminal CLK3, and the third output signal terminal OUT3.

At least one output unit (e.g., the first output unit 150_1) is also connected to the power signal terminal GVDD for providing a signal of one of the connected clock signal terminal and the power signal terminal GVDD to the connected output signal terminal under the control of the pull-up node Q and the pull-down node QB. As shown in fig. 4, the first output unit 150_1 is connected to the pull-up node Q, the pull-down node QB, the power signal terminal GVDD, the first clock signal terminal CLK1, and the first output signal terminal OUT1. The first output unit 150_1 may supply a signal of one of the first clock signal terminal CLK1 and the power signal terminal GVDD to the first output signal terminal OUT1 under the control of the pull-up node Q and the pull-down node QB.

At least another output unit (e.g., the second output unit 150_2 and the third output unit 150_3) is further connected to the reference signal terminal VGL for supplying a signal of one of the connected clock signal terminal and the reference signal terminal VGL to the connected output signal terminal under the control of the pull-up node Q and the pull-down node QB. For example, in fig. 4, the second output unit 150_2 is connected to the pull-up node Q, the pull-down node QB, the reference signal terminal VGL, the second clock signal terminal CLK2, and the second output signal terminal OUT2. The second output unit 150_2 may supply a signal of one of the second clock signal terminal CLK2 and the reference signal terminal VGL to the second output signal terminal OUT2 under the control of the pull-up node Q and the pull-down node QB. The third output unit 150_3 is connected to the pull-up node Q, the pull-down node QB, the reference signal terminal VGL, the third clock signal terminal CLK3, and the third output signal terminal OUT3. The third output unit 150_3 may supply a signal of one of the third clock signal terminal CLK3 and the reference signal terminal VGL to the third output signal terminal OUT3 under the control of the pull-up node Q and the pull-down node QB.

In the embodiment of the disclosure, a signal output circuit including K output units is provided in a shift register unit, one end of each output unit is connected to a corresponding clock signal end, and the other end is connected to a reference signal end or a power signal end. In this way, the shift register unit can generate a plurality of display driving signals (e.g., gate driving signals and light emission control signals) required to drive the sub-pixels without providing a separate shift register unit for each display driving signal, which is advantageous for a narrow bezel design of the display panel.

Fig. 5 shows a schematic block diagram of a shift register cell according to another embodiment of the present disclosure.

Similar to fig. 4, the shift register cell of fig. 5 also includes an input circuit 110, a pull-up circuit 120, a pull-down circuit 130, a cascade output circuit 140, and a signal output circuit 150, and the above description of these circuits applies equally to fig. 5.

Unlike fig. 4, the power signal terminals of fig. 5 may include a first power signal terminal GVDD1 and a second power signal terminal GVDD2, and the reference signal terminals may include a first reference signal terminal VGL1 and a second reference signal terminal VGL2. The cascade output circuit 140 may be connected to the first power signal terminal GVDD1 and the first reference signal terminal VGL1, and the signal output circuit including K output units 150_1, 150_2, 150_3 may be connected to the second power signal terminal GVDD2 and the second reference signal terminal VGL2. By connecting the signal output circuit to a set of separate power signal terminals and reference signal terminals, the impact of other circuits on the signal output circuit can be reduced.

As shown in fig. 5, the cascade output circuit 140 may include a first cascade subcircuit 1401 and a second cascade subcircuit 1402.

The first cascade sub-circuit 1401 is connected to the pull-up node Q, the power signal terminal (the first power signal terminal GVDD1 in fig. 5), and the cascade output terminal CR. The first cascode sub-circuit 1401 may supply a signal of the power signal terminal to the cascode output terminal CR under the control of the pull-up node Q.

The second cascode sub-circuit 1402 is connected to the pull-down node QB, the reference signal terminal (the first reference signal terminal VGL1 in fig. 5), and the cascode output terminal CR. The second cascode sub-circuit 1402 may supply the signal of the reference signal terminal to the cascode output terminal CR under the control of the pull-down node QB.

In some embodiments, each output unit may include a first output sub-circuit and a second output sub-circuit. For example, in fig. 5, the first output unit 150_1 includes a first output sub-circuit 1501_1 and a second output sub-circuit 1501_2, the second output unit 1502 includes a first output sub-circuit 1502_1 and a second output sub-circuit 1502_2, and the third output unit 1503 includes a first output sub-circuit 1503_1 and a second output sub-circuit 1503_2.

In some embodiments, each of the first and second output sub-circuits has a control terminal, an input terminal, and an output terminal and is configured to provide a signal of the input terminal to the output terminal under control of the control terminal.

For example, in the first output unit 150_1, the control terminal of the first output sub-circuit 1501_1 is connected to the first pull-up node Q, the input terminal of the first output sub-circuit 1501_1 is connected to the first clock signal terminal CLK1, and the output terminal of the first output sub-circuit 1501_1 is connected to the first output signal terminal OUT1. The control terminal of the second output sub-circuit 1501_2 is connected to the pull-down node QB, the input terminal of the second output sub-circuit 1501_2 is connected to the power signal terminal (the second power signal terminal GVDD2 is connected in fig. 5), and the output terminal of the second output sub-circuit 1501_2 is connected to the first output signal terminal OUT1.

In the second output unit 150_2, the control terminal of the first output sub-circuit 1502_1 is connected to the first pull-up node Q, the input terminal of the first output sub-circuit 1502_1 is connected to the second clock signal terminal CLK2, and the output terminal of the first output sub-circuit 1502_1 is connected to the second output signal terminal OUT; the control terminal of the second output sub-circuit 1502_2 is connected to the pull-down node QB, the input terminal of the second output sub-circuit 1502_2 is connected to the reference signal terminal (the second reference signal terminal VGL2 is connected in fig. 5), and the output terminal of the second output sub-circuit 1502_2 is connected to the second output signal terminal OUT2.

Similarly, in the third output unit 150_3, the control terminal of the first output sub-circuit 1503_1 is connected to the first pull-up node Q, the input terminal of the first output sub-circuit 1503_1 is connected to the third clock signal terminal CLK3, and the output terminal of the first output sub-circuit 1503_1 is connected to the third output signal terminal OUT3; the control terminal of the second output sub-circuit 1503_2 is connected to the pull-down node QB, the input terminal of the second output sub-circuit 1503_2 is connected to the reference signal terminal (in fig. 5, the second reference signal terminal VGL2 is connected), and the output terminal of the second output sub-circuit 1503_2 is connected to the third output signal terminal OUT3.

In some embodiments, one of the K clock signal terminals may be electrically connected to a power signal terminal, for example, when k=4, the fourth clock signal terminal CLK4 may be electrically connected to the second power signal terminal GVDD2 to receive the second power signal, as will be described in detail below.

Fig. 6 shows a circuit diagram of a shift register cell according to an embodiment of the present disclosure.

The shift register unit of fig. 6 also includes an input circuit 210, a pull-up circuit 220, a pull-down circuit 230, a cascade output circuit 240, and a signal output circuit, and the above description for the input circuit, the pull-up circuit, the pull-down circuit, the cascade output circuit, and the signal output circuit is equally applicable to the present embodiment.

In fig. 6, k=4, and the signal output circuit includes a first output unit 250_1, a second output unit 250_2, a third output unit 250_3, and a fourth output unit 250_4.

Each of the output cells of fig. 6 also includes a first output sub-circuit and a second output sub-circuit. For example, the first output sub-circuit of the first output unit 250_1 includes a first transistor t1_1 and a first capacitor c1_1, and the second output sub-circuit of the first output unit 250_1 includes a second transistor t2_1. Similarly, the first output sub-circuit of the second output unit 250_2 includes a first transistor t1_2 and a first capacitor c1_2, and the second output sub-circuit of the first output unit 250_1 includes a second transistor T2v2; the first output sub-circuit of the third output unit 250_3 includes a first transistor t1_3 and a first capacitor c1_3, and the second output sub-circuit of the first output unit 250_3 includes a second transistor t2_3.

In each output unit, a gate of the first transistor is used as a control end of the first output sub-circuit, a first pole of the first transistor is used as an input end of the first output sub-circuit, a second pole of the first transistor is used as an output end of the first output sub-circuit, a first pole of the first capacitor is connected with the gate of the first transistor, and a second pole of the first capacitor is connected with a second pole of the first transistor; the gate of the second transistor is used as the control end of the second output sub-circuit, the first pole of the second transistor is used as the input end of the second output sub-circuit, and the second pole of the second transistor is used as the output end of the second output sub-circuit. Taking the first output unit 250_1 as an example, the gate of the first transistor t1_1 is connected to the pull-up node Q as the control end of the first output sub-circuit, the first pole of the first transistor t1_1 is connected to the first clock signal terminal CLK1 as the input end of the first output sub-circuit, the second pole of the first transistor t1_1 is connected to the first output signal terminal OUT1 as the output end of the first output sub-circuit, the first pole of the first capacitor c1_1 is connected to the gate of the first transistor t1_1, and the second pole of the first capacitor c1_1 is connected to the second pole of the first transistor t1_1. Also taking the first output unit 250_1 as an example, the gate of the second transistor t2_1 is connected to the pull-down node QB as the control terminal of the second output sub-circuit, the first pole of the second transistor t2_1 is connected to the second reference signal terminal VGL2 as the input terminal of the second output sub-circuit, and the second pole of the second transistor t2_1 is connected to the first output signal terminal OUT1 as the output terminal of the second output sub-circuit. The first transistor, the second transistor, and the second capacitor in the second output unit 250_2, the third output unit 250_3, and the fourth output unit 250_4 are connected in a similar manner, and a detailed description thereof is omitted.

With continued reference to fig. 6, the cascode output circuit 240 likewise includes a first cascode sub-circuit including the third transistor T3 and the second capacitor C2 and a second cascode sub-circuit including the fourth transistor T4 and the third capacitor C3. As shown in fig. 6, the gate of the third transistor T3 is connected to the pull-up node Q, the first pole of the third transistor T3 is connected to the power signal terminal (the first power signal terminal GVDD1 in fig. 6), and the second pole of the third transistor T3 is connected to the cascade output terminal CR. The first pole of the second capacitor C2 is connected to the gate of the third transistor T3, and the second pole of the second capacitor C2 is connected to the second pole of the third transistor T3. The gate of the fourth transistor T4 is connected to the pull-down node QB, the first pole of the fourth transistor T4 is connected to the reference signal terminal (the first reference signal terminal VGL1 in fig. 6), and the second pole of the fourth transistor T4 is connected to the cascode output terminal CR. The first pole of the third capacitor C3 is connected to the gate of the fourth transistor T4, and the second pole of the third capacitor C3 is connected to the second pole of the fourth transistor T4.

In some embodiments, as shown in fig. 6, the pull-up circuit 220 may include a first control sub-circuit 2201 and a second control sub-circuit 2202.

The first control sub-circuit 2201 is connected to the input signal terminal IN, the power signal terminal (the third power signal terminal VGH IN fig. 6, which may be implemented by other power signal terminals, for example, the first power signal terminal GVDD 1), and the second control signal terminal CKB and the intermediate node P of the shift register unit. The first control sub-circuit 2201 may control the potential of the intermediate node P based on the signals of the input signal terminal IN and the second control signal terminal CKB. In fig. 6, the first control sub-circuit 2201 includes a seventh transistor T7 and an eighth transistor T8. The gate of the seventh transistor T7 is connected to the second control signal terminal CKB, the first pole of the seventh transistor T7 is connected to the power signal terminal VGH, and the second pole of the seventh transistor T7 is connected to the intermediate node P. The gate of the eighth transistor T8 is connected to the input signal terminal IN, the first pole of the eighth transistor T8 is connected to the second control signal terminal CKB, and the second pole of the eighth transistor T8 is connected to the intermediate node P.

The second control sub-circuit 2202 is connected to the intermediate node P, the pull-down node QB and the first control signal terminal CKA of the shift register unit. The second control sub-circuit 2202 may pull up the potential of the pull-down node OB based on the signals of the intermediate node P and the first control signal terminal CKB. In fig. 6, the second control sub-circuit 2202 includes a ninth transistor T9, a tenth transistor T10, and a fourth capacitor C4. The gate of the ninth transistor T9 is connected to the intermediate node P, the first pole of the ninth transistor T9 is connected to the first control signal terminal CKA, the second pole of the ninth transistor T9 is connected to the first pole of the tenth transistor T10, the gate of the tenth transistor T9 is connected to the first control signal terminal CKA, and the second pole of the tenth transistor T10 is connected to the pull-down node QB. The first pole of the fourth capacitor C4 is connected to the gate of the ninth transistor T9, and the second pole of the fourth capacitor C4 is connected to the second pole of the ninth transistor T9.

The pull-down circuit 230 may include a thirteenth transistor T13. The gate of the thirteenth transistor T13 is connected to the pull-up node Q, the first pole of the thirteenth transistor T13 is connected to the reference signal terminal (the first reference signal terminal VGL1 in fig. 6), and the second pole of the thirteenth transistor T13 is connected to the pull-down node QB.

The input circuit 210 may include a fourteenth transistor T14, a gate of the fourteenth transistor T14 is connected to the first control signal terminal CKA, a first pole of the fourteenth transistor T14 is connected to the input signal terminal IN, and a second pole of the fourteenth transistor T14 is connected to the pull-up node Q.

In some embodiments, as shown in fig. 6, the input circuit may further include a fifteenth transistor T15. In this case, the second pole of the fourteenth transistor T14 may be connected to the pull-up node Q through a fifteenth transistor T15, wherein the gate of the fifteenth transistor T15 is connected to the power signal terminal (the first power signal terminal GVDD1 in fig. 6), the first pole of the fifteenth transistor T15 is connected to the second pole of the fourteenth transistor T14, and the second pole of the fifteenth transistor T15 is connected to the pull-up node Q. The fifteenth transistor T15 may function as an isolation. For example, taking the fifteenth transistor T15 as an N-type transistor, when the potential of the pull-up node Q or the node QH is higher than the potential of the gate of the fifteenth transistor (i.e., the potential of the first control signal terminal CKA), the fifteenth transistor T15 is turned off, so as to isolate the pull-up node Q from the node QH, so as to avoid the influence of the excessive potential of the pull-up node Q on the output signal.

In some embodiments, the shift register cell may also include a reset circuit 260, as shown in FIG. 6. The reset circuit 260 is connected to the pull-up node Q, the pull-down node QB, the power signal terminal (the first power signal terminal GVDD1 in fig. 6), the reference signal terminal (the first reference signal terminal VGL1 in fig. 6), and the reset signal terminal TRS of the shift register unit. The reset circuit 260 may supply the signal of the reference signal terminal (the first reference signal terminal VGL 1) to the pull-up node Q and the signal of the power signal terminal (the first power signal terminal GVDD 1) to the pull-down node QB under the control of the reset signal terminal TRS. In the example of fig. 6, the reset circuit 260 includes a sixteenth transistor T16 and a seventeenth transistor T17. The gate of the sixteenth transistor T16 is connected to the reset signal terminal TRS, the first pole of the sixteenth transistor T16 is connected to the reference signal terminal (the first reference signal terminal VGL 1), and the second pole of the sixteenth transistor is connected to the pull-up node Q. A gate of the seventeenth transistor T17 is connected to the reset signal terminal TRS, a first pole of the seventeenth transistor T17 is connected to the power signal terminal (the first power signal terminal GVDD 1), and a second pole of the seventeenth transistor T17 is connected to the pull-down node QB.

When the shift register unit operates, the input signal terminal IN and the first control signal terminal CKA are both at high level, the fourteenth transistor T14 is turned on, and the gate of the fifteenth transistor T15 is turned on under the action of the first power signal terminal GVDD1, so that the high level of the input signal terminal IN is provided to the pull-up node Q. The high level of the pull-up node Q turns on the first transistors t1_1, t1_2, t1_3, t1_4 of the respective output units, thereby providing the signals of the respective connected clock signal terminals CLK1 to CLK4 to the corresponding output signal terminals OUT1 to OUT4, thereby generating four output signals. In this process, the high level of the node QB turns on the thirteenth transistor T13, thereby providing the low level of the first reference signal terminal VGL1 to the pull-down node QB, so that the pull-down node QB is maintained at the low level.

Next, the input signal terminal IN becomes low level, and the eighth transistor T8 is turned off. When the second control signal terminal CKB is at a high level, the seventh transistor T7 is turned on, and the high level of the third power signal terminal VGH is provided to the intermediate node P, and the high level of the intermediate node P turns on the ninth transistor T9 to wait for the arrival of the high level of the first control signal terminal CKA. Thereafter, when the high level of the first control signal terminal CKA comes, both the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, thereby providing the low level of the input signal terminal IN to the pull-up node Q, so that both the third transistor T3 and the first transistors t1_1 to t1_4 of the respective output units are turned off. The high level of the first control signal terminal CKA also turns on the tenth transistor T10, thereby pulling up the pull-down node QB to the high level. The high level of the pull-down node QB turns on the fourth transistor T4, so that the cascade output terminal CR outputs a low level signal. The high level of the pull-down node QB also turns on the second transistors t2_1, t2_2, t2_3, and t2_4 of the respective output units, so that the first output signal terminal OUT1 outputs a high level, and the second to fourth output signal terminals OUT2 to OUT4 each output a low level. In this way, the shift register unit generates four output signals, wherein the output signal of the first output signal terminal OUT1 can be used as an active low light emission control signal; and the output signals of the second to fourth output signal terminals OUT2 to OUT4 may be used as active high gate driving signals. When one frame display is finished, all shift register units may be reset. For example, a reset signal of, for example, a high level is applied to the reset signal terminal TRS of each shift register unit, so that the sixteenth transistor T16 and the seventeenth transistor T17 of each shift register unit are turned on. Turning on the sixteenth transistor T16 resets the pull-up node Q to a low level of the first reference signal terminal VGL 1; the turn-on of the seventeenth transistor T17 resets the pull-down node QB to the high level of the first power signal terminal GVDD1, so that no output is generated from each output unit, thereby realizing the reset of the shift register unit.

The shift register unit of fig. 7 is similar to that of fig. 6, except that two output units are connected to the power signal terminal and the other two output units are connected to the reference signal terminal in fig. 7. As shown in fig. 7, the circuit configuration other than the fourth output unit 2504 is the same as that of fig. 6, and a detailed description thereof will be omitted. The fourth output unit 2504 is connected to the fourth clock signal terminal CLK4 and the second power signal terminal GVDD2. When the pull-up node Q is at a high level and the pull-down node QB is at a low level, the transistor t1_4 is turned on and the transistor t2_4 is turned off, thereby providing the signal of the fourth clock signal terminal CLK4 to the output signal terminal OUT4. When the pull-up node Q is at a low level and the pull-down stage QB is at a high level, the transistor t1_4 is turned off and the transistor t2_4 is turned on, thereby providing the signal of the second power signal terminal GVDD2 to the output signal terminal OUT4.

The shift register described above with reference to fig. 6 and 7 has four output signal terminals, and can generate four display driving signals required to drive a single sub-pixel, for example, the driving signals required for the above-described pixel circuit 10A.

Similar to fig. 6, the shift register unit of fig. 8 also includes an input circuit 310, a pull-up circuit 320, a pull-down circuit 330, a cascade output circuit, a signal output circuit, and a reset circuit 360, which are different at least in that k=3 (that is, the signal output circuit includes three output units), and at least one of the pull-up circuit 320, the cascade output circuit, and the reset circuit 360 may be further provided with an anti-leakage structure. For convenience of description, the distinguishing part will be mainly described in detail hereinafter.

The input circuit 310 includes a fourteenth transistor T14 and a fifteenth transistor T15. Unlike fig. 6, a gate of the fifteenth transistor T15 in the input circuit 310 of fig. 8 is connected to the first control signal terminal CKA. This connection of the fifteenth transistor T15 can also function as isolation. For example, when the first control signal terminal CKA is at a high level, the fifteenth transistor T15 is turned on, thereby allowing a high level of the input signal terminal IN to be input to the pull-up node Q through the fourteenth transistor T14 and the fifteenth transistor T15. When the first control signal terminal CKA is at a low level, the fifteenth transistor T15 is turned on, thereby isolating the node QH from the pull-up node Q. At this time, even if the fourteenth transistor T14 leaks or the potential of the node QH rises due to other reasons, the presence of the fifteenth transistor T15 can prevent the node QH from affecting the potential of the pull-up node Q.

The pull-up circuit 320 includes a first control sub-circuit 3201 and a second control sub-circuit 3202. The second control sub-circuit 3202 has the same structure as the second control sub-circuit 2202 described above, and will not be described again here. Unlike fig. 6, the first control sub-circuit 3201 includes an eleventh transistor T11 and a twelfth transistor T12 in addition to the seventh transistor T7 and the eighth transistor T8. The first pole of the eighth transistor T8 is connected to the second control signal terminal CKB through the eleventh transistor T11. As shown IN fig. 8, the gate of the eleventh transistor T11 is connected to the input signal terminal IN, the first pole of the eleventh transistor T11 is connected to the second control signal terminal CKB, and the second pole of the eleventh transistor T11 is connected to the first pole of the eighth transistor T8. The gate of the twelfth transistor T12 is connected to the intermediate node P, the first pole of the twelfth transistor T12 is connected to the power signal terminal, and the second pole of the twelfth transistor T12 is connected to the first pole of the eighth transistor. The presence of the eleventh transistor T11 and the twelfth transistor T12 may play a role in preventing leakage. For example, when the input signal terminal IN is low, the intermediate node P is high, and the second control signal terminal CKB is low, if there are no eleventh and twelfth transistors T11 and T12, then such a case will occur: the eighth transistor T8 is in an off state, but there is a large voltage difference between the first pole and the second pole of the eighth transistor T8, which makes the eighth transistor T8 susceptible to leakage. By providing the eleventh transistor T11 and the twelfth transistor T12, the high level of the intermediate node T12 in this case will turn on the twelfth transistor T12, thereby making both the first pole and the second pole of the eighth transistor T8 at the high level, reducing the voltage difference between the first pole and the second pole of the eighth transistor T8, and thus playing a role in preventing leakage. Meanwhile, the low level of the input signal terminal IN also turns off the eleventh transistor T11, thereby preventing the potential of the first pole of the eighth transistor T8 from being affected by the second control signal terminal CKB.

The pull-down circuit 330 may have the same structure as the pull-down circuit 230 in the above embodiment, and will not be described again.

The cascade output circuit includes a first cascade sub-circuit 3401 and a second cascade sub-circuit 3402. The description of the first cascade sub-circuit 3401 and the third transistor T3 and the second capacitor C2 described above with reference to fig. 6 is equally applicable to the present embodiment. Unlike fig. 6, the second cascade sub-circuit 3402 includes a fifth transistor T5 and a sixth transistor T6 in addition to the fourth transistor T4 and the third capacitor C2. The second pole of the fourth transistor T4 is connected to the cascade output CR through a fifth transistor T5. As shown in fig. 8, the first pole of the fifth transistor T5 is connected to the second pole of the fourth transistor T4, the second pole of the fifth transistor T5 is connected to the cascade output terminal CR, and the gate T5 of the fifth transistor is connected to the pull-down node QB. The gate of the sixth transistor T6 is connected to the cascode output terminal CR, the first pole of the sixth transistor T6 is connected to the power signal terminal (the first power signal terminal GVDD 1), and the second pole of the sixth transistor T6 is connected to the pull-up node Q. The fifth transistor T5 and the sixth transistor T6 may also function as an anti-leakage. When the cascade output terminal CR is at a high level and the pull-down node QB is at a low level, if there are no fifth transistor T5 and no sixth transistor T6, the following will occur: the fourth transistor T4 is in an off state, but the first pole of the fourth transistor T4 is extremely low and the second pole is high, and a large potential difference exists between the first pole and the second pole of the fourth transistor T4, so that the fourth transistor T4 is prone to leak. By setting the fifth transistor T5 and the sixth transistor T6, the low level of the pull-down node QB puts the fifth transistor T5 in an off state, the first pole of the fifth transistor T5 receives the high level of the cascade output CR, and the high level of the cascade output CR will put the sixth transistor T6 on, thereby providing the high level of the first power signal terminal GVDD1 to the first pole of the fifth transistor T5. In this way, the fifth transistor T5 is in an off state, and both the first and second poles of the fifth transistor T5 are at a high level, thereby preventing leakage of the fifth transistor T5. At this time, even if the fourth transistor T4 leaks, the presence of the fifth transistor T5 can prevent the leakage of the fourth transistor T4 from affecting the output signal of the cascade output terminal CR.

In the present embodiment, k=3, the signal output circuit includes a first output unit 350_1, a second output unit 350_2, and a third output unit 350_3. The descriptions of the first output unit 250_1, the second output unit 250_2, and the third output unit 250_3 in the above embodiment are also applicable to the present embodiment, and are not repeated here.

The reset circuit 360 is similar to the reset circuit 260 described above, except that the reset circuit 360 includes an eighteenth transistor T18 in addition to the sixteenth transistor T16 and the seventeenth transistor T17. A first pole of the sixteenth transistor T16 is connected to the reference signal terminal (the first reference signal terminal VGL 1) through the eighteenth transistor T18. As shown in fig. 8, the gate of the eighteenth transistor T18 is connected to the reset signal terminal TRS, the first pole of the eighteenth transistor T18 is connected to the reference signal terminal (the first reference signal terminal VGL 1), and the second pole of the eighteenth transistor T18 is connected to the first pole of the sixteenth transistor. The eighteenth transistor T18 may also function as an anti-leakage. For example, when the reset signal terminal TRS is low and the pull-up node Q is high, if the eighteenth transistor T18 is not present, the first and second poles of the sixteenth transistor T16 will be at a level and a high level, respectively, so that leakage easily occurs. By setting the eighteenth transistor T18, the low level of the reset signal terminal TRS will cause the eighteenth transistor T18 to be turned off, and the first and second poles of the sixteenth transistor T16 are both at a high level, thereby preventing the sixteenth transistor T16 from leaking.

The shift register described above with reference to fig. 8 has three output signal terminals adapted to generate three driving signals, such as the driving signals required for the pixel circuit 10C described above, which will be described in detail below.

In some embodiments, the signal output circuit of the shift register unit may generate some or all of K driving signals required to drive a single subpixel. For example, assuming that the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, and the emission control signal EM are required to drive a single sub-pixel, a single shift register unit may be set to generate all driving signals required for the single sub-pixel, i.e., the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, and the emission control signal EM (to be described in detail with reference to fig. 9A to 12B below). It is also possible to arrange one shift register unit to generate the first gate driving signal G1, the third gate driving signal G3 and the emission control signal EM required for the sub-pixel and the other shift register unit to generate the second gate driving signal G2 required for the sub-pixel such that the two shift register units cooperatively provide all of the required driving signals for the sub-pixel (to be described in detail below with reference to fig. 13A to 13C).

Embodiments of the present disclosure also provide a display driving circuit including the shift register unit of any of the above embodiments, which will be described in detail below with reference to fig. 9A to 13C.

Fig. 9A shows a schematic diagram of a display driving circuit according to an embodiment of the present disclosure.

As shown in fig. 9A, the display driving circuit includes N shift register units GOA <1>, GOA <2>, GOA < N > connected in cascade. The shift register cell in fig. 9A may be implemented as the shift register cell of any of the embodiments described above, such as the shift register cell described above with reference to fig. 6.

The cascade output CR of the N-th shift register unit may be connected to the input signal IN of the n+i-th shift register unit, where N, N and i are both positive integers, N < N. For example, IN fig. 9A, i=1, the cascade output CR of the 1 st stage shift register unit GOA <1> is connected to the input signal IN of the 2 nd stage shift register unit GOA <2>, the cascade output CR of the 2 nd stage shift register unit GOA <2> is connected to the input signal IN of the 3 rd stage shift register unit GOA <3>, and so on. The input signal terminal IN of the first stage shift register unit GOA <1> can receive the start signal STU. Although illustrated in fig. 9A by taking i=1 as an example, embodiments of the present disclosure are not limited thereto, and i may be set to other values as needed.

The display driving circuit may receive a plurality of clock signals, for example, M narrow clock signals and M wide clock signals sequentially shifted, M being an integer multiple of K. In fig. 9A, m=4, M narrow clock signals shifted in sequence are clock signals Clks1, clks2, clks3, and Clks4, and M wide clock signals shifted in sequence are Clkp1, clkp2, clkp3, and Clkp4.

The K clock signal terminals of each shift register unit may receive K clock signals of the plurality of clock signals, respectively. For example, the N shift register units may be divided into at least one group, each group including M shift register units connected in cascade, M1 st clock signal terminals of each group of shift register units being configured to receive M narrow clock signals, respectively, M2 nd clock signal terminals of each group of shift register units being configured to receive M wide clock signals, respectively, wherein k1 and k2 are positive integers, 1.ltoreq.k1.ltoreq.n, 1.ltoreq.k2.ltoreq.n, and k1.noteq.k2. In fig. 9A, k=4, m=4, n shift register units are divided into groups, each group including four shift register units, for example, a first group including first to fourth stages of shift register units GOA <1> to GOA <4>, a second group including fifth to eighth stages of shift register units GOA <5> to GOA <8>, and so on. The clock signal terminals CLK1, CLK2 and CLK4 of the shift register cells in each group receive a narrow clock signal, and the clock signal terminal CLK3 receives a wide clock signal.

In fig. 9A, taking the first group as an example, the first clock signal terminal CLK1 of the shift register unit GOA <1> at the first stage receives the second narrow clock signal CLK2, the first clock signal terminal CLK1 of the shift register unit GOA <2> at the second stage receives the third narrow clock signal CLK3, the first clock signal terminal CLK1 of the shift register unit GOA <3> at the third stage receives the fourth narrow clock signal CLK4, and the first clock signal terminal CLK1 of the shift register unit GOA <4> at the fourth stage receives the first narrow clock signal CLK 1. In a similar manner, the second clock signal terminals CLK2 of the shift register units GOA <1> to GOA <4> receive the first, second, third and fourth narrow clock signals CLK1, CLK2, CLK3 and CLK4, respectively. The third clock signal terminals CLK3 of the shift register units GOA <1> to GOA <4> respectively receive the first wide clock signal Clkp1, the second wide clock signal Clkp2, the third wide clock signal Clkp3 and the fourth wide clock signal Clkp1. The fourth clock signal terminals CLK4 of the shift register units GOA <1> to GOA <4> respectively receive the third narrow clock signal CLK3, the fourth narrow clock signal CLK4, the first narrow clock signal CLK1 and the second narrow clock signal CLK 2.

The clock signal terminals of the first to fourth stage shift register units GOA <5> to GOA <8> (i.e., the fifth to eighth stage shift register units in the entire display driving circuit) in the second group are connected in the same manner. Specifically, the first clock signal terminals CLK1 of the shift register units GOA <5> to GOA <8> respectively receive the clock signals CLK2, CLK3, CLK4 and CLK1, the second clock signal terminals CLK2 respectively receive the clock signals CLK1, CLK2, CLK3, CLK4, the third clock signal terminals CLK3 respectively receive the clock signals Cklp1, ckp 2, ckp 3, ckp 4, and the fourth clock signal terminals CLK4 respectively receive the clock signals CLK3, CLK4, CLK1, CLK 2. The clock terminals of the third group of shift register units GOA <9> to GOA <12> are also connected in the same manner, and so on.

The first control signal terminal CKA and the second control signal terminal CKB of each shift register unit receive the first control signal CKA and the second control signal CKB. In fig. 9A, the shift register units GOA <1>, GOA <3>, GOA <5> … at odd stages have a first control signal CKA receiving a first control signal CKA and a second control signal CKB receiving a second control signal CKB; the shift register units GOA <2>, GOA <4>, GOA <6> … at even stages have a first control signal terminal CKA receiving the second control signal cbb and a second control signal terminal Ckb receiving the second control signal CKA. However, embodiments of the present disclosure are not limited thereto, and the connection manner of the odd and even stages may be interchanged.

The reset signal terminals TRS of each shift register unit GOA <1>, GOA <2>, GOA < N > receive a reset signal TRS. Referring to fig. 6, the power signal terminal and the reference signal terminal of each shift register may receive corresponding power signals and reference signals, for example, the first power signal terminal GVDD1 may receive a first power signal, the first reference signal terminal VGL1 may receive a first reference signal, the second power signal terminal GVDD2 may receive a second power signal, and the second reference signal terminal VGL2 may receive a second reference signal, which will not be described herein.

The display driving circuit may be used to drive the plurality of rows of sub-pixels, wherein the K output signal terminals of each shift register unit provide display driving signals to a corresponding one of the plurality of rows of sub-pixels. According to an embodiment of the present disclosure, the display driving signals include gate driving signals and light emission control signals required to drive the row of subpixels. For example, as shown in fig. 9A, the output signal terminals OUT1, OUT2, OUT3, OUT4 of each shift register unit may be the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, and the light emission control signal EM required for the pixel circuit described above with reference to fig. 1 and 2. This will be described in detail below with reference to the signal timing of fig. 9B.

Fig. 9B shows a signal timing diagram of the display driving circuit of fig. 9A.

As shown in fig. 9B, the display driving circuit receives 4 narrow clock signals Clks1 to Clks4 and 4 wide clock signals Clkp1 to Clkp4, which are sequentially shifted. Clock signals clk 1, clk 2, clk 3, clk 4, clk p1, clk p2, clk p3, and clk p4 are sequentially shifted by H in this order. Here, H denotes a unit scan time, which is a time required to scan one line of sub-pixels, i.e., a time interval from generation of a gate driving signal for one line of sub-pixels to generation of a gate driving signal for the next line of sub-pixels. The duty cycle of the narrow clock signal is less than the duty cycle of the wide clock signal. For example, the duty cycle of the wide clock signal may be twice the duty cycle of the narrow clock signal. In fig. 9B, the clock periods of the narrow clock signals Clks1 to Clks14 and the wide clock signals Clkp1 to Clkp14 are each 4H, the active level duration of the narrow clock signals Clks1 to Clks4 is H, and the active level duration of the wide clock signals C1kp1 to Clkp4 is 2H.

The first control signal clk a and the second control signal clk b may have the same period and be relatively shifted such that one of the first control signal clk a and the second control signal clk b is in a high level period and the other is in a low level period. For example, in fig. 9B, the active level durations of the first control signal clk a and the second control signal Clkb may be one half H, and the shift therebetween may be H, so that the first control signal clk a and the second control signal Clkb are not at high level.

In fig. 9B, a signal timing of the shift register unit GOA < n > located at the n-th stage of fig. 9A, which has the circuit configuration described above with reference to fig. 6, is illustrated as an example. In connection with fig. 6 and 9A, it is assumed that n=2, and clock signals CLK1 to CLK4 of shift register unit GOA <2> receive clock signals CLKs3, CLKs2, clkp2, and CLKs4, respectively. The input signal terminal IN of the shift register unit GOA <2> receives as input signal the signal CR <1> of the cascade output terminal of the previous stage shift register unit GOA <1 >. The first control signal terminal CKA of the shift register unit GOA <2> receives the second control signal cbb, and the second control signal terminal Ckb receives the first control signal CKA.

IN the period t1, the signal CR < n-1> (i.e., CR <1 >) output from the cascade output terminal of the previous stage shift register unit is at a high level, that is, the input signal terminal IN of the shift register unit GOA <2> of fig. 9A is at a high level. Referring to fig. 6, the high level of the input signal terminal IN turns on the transistor T8, thereby providing the signal of the second control signal terminal CKB to the intermediate node P. As can be seen from fig. 9A, the intermediate node P follows the potential of the first control signal Cka received at the second control signal terminal CKB. In this period, since the second clock signal Ckb is low, the first control signal terminal CKA of the shift register unit GOA <2> of FIG. 9A is low, the transistor T14 is in an off state, the pull-up node Q is kept low, the transistor T3 and the transistors T1_1, T1_2, T1_3 and T1_4 are all in an off state, and the cascade output terminal CR and the output signal terminals OUT1 to OUT4 are all kept at the original potential, referring to FIG. 6.

In the period t2, the second control signal Ckb is high, that is, the first control signal terminal CKA of the shift register unit GOA <2> in FIG. 9A is high. Referring to fig. 6, the high level of the first control signal terminal CKA turns on the transistors T14 and T15, and the high level of the input signal terminal IN is supplied to the pull-up node Q and the node QH. The high level of the node QH turns on the transistor T13, and the pull-down node QB is pulled down to the low level of the first reference signal terminal VGL 1. The high level of the pull-up node Q turns on the transistor T3, thereby providing the high level of the first power signal terminal GVDD1 to the cascade output terminal CR (as shown by CR < n > in fig. 9A). The high level of the pull-up node Q also turns on the transistors t1_1, t1_2, t1_3, and t1_4, but at this time, since the clock signals CLKs3, CLKs2, clkp2, and CLKs4 received by the clock signal terminals CLK1 to CLK4 of the shift register unit GOA <2> are all at low level, the output signal terminals OUT1 to OUT4 are all at low level.

In the period T3, the clock signals CLK2 and Clkp2 received by the clock signal terminals CLK2 and CLK3 of the shift register unit GOA <2> are at a high level, the clock signals CLKs3 and CLKs4 received by the clock signal terminals CLK1 and CLK4 are at a low level, referring to fig. 6, the transistors t1_2 and t1_3 in the on state supply the clock signals CLKs2 and Clkp2 at a high level to the output signal terminals OUT2 and OUT3, and the transistors t1_1 and t1_4 in the on state supply the clock signals CLKs3 and CLKs4 at a low level to the output signal terminals OUT1 and OUT4. Since the output signal terminals OUT2 and OUT3 are at high level, the bootstrap action of the capacitors c1_2 and c1_3 further increases the potential of the pull-up node Q.

In the period T4, the clock signals Clks3 and Clkp2 are at a high level, the clock signals Clks2 and Clks4 are at a low level, the transistors t1_3 and t1_1 in the on state supply the clock signals Clks3 and Clkp2 at a high level to the output signal terminals OUT3 and OUT1, and the transistors t1_2 and t1_4 in the on state supply the clock signals Clks2 and Clks4 at a low level to the output signal terminals OUT1 and OUT4.

In the period T5, the clock signal clk 4 is at a high level, the clock signals clk 2, clk 3 and Clkp2 are all at a low level, the transistor t1_4 in the on state supplies the clock signal clk 4 at a high level to the output signal terminal OUT4, and the transistors t1_2, t1_3 and t1_4 in the on state supply the clock signals clk 2, clk 3 and Clkp2 at a low level to the output signal terminals OUT1, OUT3 and OUT4.

In period t6, the clock signals Clks3, clks2, clkp2, and Clks4 are all at low level, so that the output signal terminals OUT1 to OUT4 are all at low level. The bootstrap action of the capacitors c1_1 to c1_4 causes the voltage of the pull-up node Q to drop. IN this process, the signal CR < n-1> (i.e., CR <1 >) output from the cascade output terminal of the previous stage shift register unit is low, that is, the input signal terminal IN of the shift register unit GOA <2> of FIG. 9A is low. The first control signal Cka and the second control signal Ckb of the shift register unit GOA <2> are both low, that is, the first control signal terminal Cka and the second control signal terminal Ckb of the shift register unit GOA <2> are both low. Referring to fig. 6, the low level of the input signal terminal IN and the second control signal terminal CKB turns off the transistors T7 and T8, and the intermediate node P remains at the original high level.

IN the period T7, the second control signal Ckb becomes high, the first control signal terminal CKA of the shift register unit GOA <2> becomes high, and referring to FIG. 6, the transistors T14 and T15 are turned on, and the low level of the input signal terminal IN is supplied to the pull-up node Q and the node QH. The high level of the first control signal terminal CKA also turns on the transistor T10. The turned-on transistors T9 and T10 supply the high level of the first control signal terminal CKA to the pull-down node QB. The high level of the pull-down node QB turns on the transistor T4 and the transistors t2_1, t2_2, t2_3, and t2_4, thereby outputting a low level at the cascade output terminal CR, the output signal terminals OUT2, OUT3, and OUT4, and outputting a high level at the output signal terminal OUT 1.

Thus far, the shift register GOA <2> completes the output of the display driving signal. As shown in fig. 9B, signals output from the output signal terminals OUT1 to OUT4 of the shift register GOA <2> may be used as the light emission control signal EM, the third gate driving signal G3, the second gate driving signal G2, and the first gate driving signal G1 of the pixel driving circuit described above with reference to fig. 1 and 2, respectively. As can be seen from fig. 9B, the duty ratio of the signals output from at least two of the K output signal terminals is different, for example, the duty ratio of the signal output from the output signal terminal OUT3 is greater than the duty ratio of the signals output from the output signal terminals OUT2 and OUT 4. The duty cycle is referred to herein as the ratio of the duration of the active level to the period length within one period (e.g., within one frame).

Other stages of shift registers operate in a similar manner. The sub-pixels are arranged in an array, and the sub-pixels located in the same row are driven by the same set of display driving signals. Since each stage of shift registers may generate a plurality of display drive signals required to drive a single sub-pixel, each stage of shift registers may provide a corresponding row of pixels with its required plurality of display drive signals. For example, in connection with fig. 9A, the first stage shift register GOA <1> generates a light emission control signal EM <1>, a first gate driving signal G1<1>, a second gate driving signal G2<1>, and a third gate driving signal G3<1> for driving the first row of subpixels; the second stage shift register GOA <2> generates a light emission control signal EM <2>, a first gate driving signal G1<2>, a second gate driving signal G2<2> and a third gate driving signal G3<2> for driving the second row of sub-pixels, and so on.

Fig. 10A shows a schematic diagram of a display driving circuit according to another embodiment of the present disclosure. The shift register unit in the display driving circuit may be implemented as the shift register unit of any of the above-described embodiments, for example, the shift register unit described above with reference to fig. 6. The display driving circuit of fig. 10A is similar to the display driving circuit of fig. 9A, and differs at least in the manner of connection of the clock signal terminals, and the details of the differences will be mainly described below.

In the example of fig. 10A, k=4, i=1, m=4, N shift register units are also grouped in groups of four, each shift register unit GOA1<1>, GOA1<2>, GOA1< N > having four output units that receive the corresponding four clock signals at the four clock signal terminals CLK1 to CLK4, respectively, and generate the four output signals at the four output signal terminals OUT1 to OUT4, respectively. As shown in fig. 10A, taking the first group as an example, the first clock signal terminal CLK1 of the first stage shift register unit GOA1<1> in the first group receives the fourth wide clock signal Clkp4, the first clock signal terminal CLK1 of the second stage shift register unit GOA1<2> receives the first wide clock signal Clkp1, the first clock signal terminal CLK1 of the third stage shift register unit GOA1<3> receives the second wide clock signal Clkp2, and the first clock signal terminal CLK1 of the fourth stage shift register unit GOA1<4> receives the third wide clock signal Clkp3. In a similar manner, the second clock signal terminals CLK2 of the shift register units GOA1<1> to GOA1<4> respectively receive the second wide clock signal Clkp2, the third wide clock signal Clkp3, the fourth wide clock signal Clkp4 and the first wide clock signal Clkp1. The third clock signal terminals CLK3 of the shift register units GOA1<1> to GOA1<4> respectively receive the first wide clock signal Clkp1, the second wide clock signal Clkp2, the third wide clock signal Clkp3 and the fourth wide clock signal Clkp4. The fourth clock signal terminals CLK4 of the shift register units GOA1<1> to GOA1<4> receive the third narrow clock signal CLK3, the fourth narrow clock signal CLK4, the first narrow clock signal CLK1 and the second narrow clock signal CLK2, respectively.

The clock signal terminals of the other sets of shift register units are connected in the same manner, and are not described here again. The connection manner of the first control signal terminal CKA and the second control signal terminal CKB of each shift register unit is the same as that described above with reference to fig. 9A, and will not be repeated here.

The output signals of the output signal terminals OUT1, OUT2, OUT3, OUT4 of each shift register unit may be used as the first gate driving signal G1, the second gate driving signal G2, the first light emission control signal EM1, and the second light emission control signal EM2 required for the above-described pixel circuit 1B. This will be described in detail below with reference to the signal timing of fig. 10B.

Fig. 10B shows a signal timing diagram of the display driving circuit of fig. 10A. As shown in fig. 10B, each shift register unit in the display driving circuit operates in a similar manner to that described above with reference to fig. 9B, except that different clock signals are controlled to generate different display driving signals, and the detailed description of the difference will be mainly provided below.

Referring to fig. 6, 10A and 10B, taking n=1 as an example, the clock signal terminals CLK1 to CLK4 of the shift register unit GOA <1> receive the clock signals Clkp4, clkp2, clkp1 and CLKs3, respectively.

IN the period T1, the input signal terminal IN of the shift register unit GOA <1> is at a high level, and the transistor T8 of the shift register unit is turned on, thereby providing the signal of the second control signal terminal CKB to the intermediate node P. As can be seen from fig. 9A, the intermediate node P follows the potential of the first control signal cbb received at the second control signal terminal CKB. In this period, since the first clock signal Cka is low, the first control signal terminal Cka of the shift register unit GOA <1> of fig. 10A is low, the transistor T14 is in an off state, the pull-up node Q is maintained at a low level, the transistor T3 and the transistors t1_1, t1_2, t1_3 and t1_4 are all in an off state, and the cascade output terminal CR and the output signal terminals OUT1 to OUT4 are all maintained at the original potential, referring to fig. 6.

In the period t2, the first control signal Cka is at a high level, that is, the first control signal terminal Cka of the shift register unit GOA <1> in fig. 10A is at a high level. Referring to fig. 6, the high level of the first control signal terminal CKA turns on the transistors T14 and T15, and the high level of the input signal terminal IN is supplied to the pull-up node Q and the node QH. The high level of the node QH turns on the transistor T13, and the pull-down node QB is pulled down to the low level of the first reference signal terminal VGL 1. The high level of the pull-up node Q turns on the transistor T3, thereby providing the high level of the first power signal terminal GVDD1 to the cascade output terminal CR (as shown by CR < n > in fig. 10B). The high level of the pull-up node Q also turns on transistors t1_1, t1_2, t1_3, and t1_4. Since the clock signals Clkp4 and Clkp1 received by the clock signal terminals CLK1 and CLK3 of the shift register unit GOA <1> are at a high level, the clock signals Clkp2 and CLKs3 received by the clock signal terminals CLK2 and CLK4 are at a low level, the output signal terminals OUT1 and OUT3 are at a high level, and the output signal terminals OUT2 and OUT4 are at a low level.

In the period t3 to t5, the shift register unit GOA <1> operates in a similar manner to that of the period t3 to t5 of fig. 9B, such that the first output unit 250_1 generates an output signal at the first output signal terminal OUT1 based on the clock signal Clkp4, the second output unit 250_2 generates an output signal at the output signal terminal OUT2 based on the clock signal Clkp2, the third output unit 250_3 generates an output signal at the output signal terminal OUT3 based on the clock signal Clkp1, and the fourth output unit 250_4 generates an output signal at the output signal terminal OUT4 based on the clock signal Clks3, as shown in fig. 10B, which will not be repeated here.

In period t6, the clock signals C1kp4 and Clkp1 are at a high level, the clock signals Clkp2 and Clks3 are at a low level, so that the output signal terminals OUT1 and OUT3 are at a high level, and the output signal terminals OUT2 and OUT4 are at a low level. The start signal received by the input signal terminal IN of GOA <1>, the first control signal clk received by the first control signal terminal CKA of the shift register unit GOA <2>, and the second control signal Clkb received by the second control signal terminal CKB are all low levels. Referring to fig. 6, the low level of the input signal terminal IN and the second control signal terminal CKB turns off the transistors T7 and T8, and the intermediate node P remains at the original high level.

IN the period T7, the first control signal clk received at the first control signal terminal CKA of the shift register unit GOA <1> becomes a high level, and referring to fig. 6, the transistors T14 and T15 are turned on, and the low level of the input signal terminal IN is supplied to the pull-up node Q and the node QH. The high level of the first control signal terminal CKA also turns on the transistor T10. The turned-on transistors T9 and T10 supply the high level of the first control signal terminal CKA to the pull-down node QB. The high level of the pull-down node QB turns on the transistor T4 and the transistors t2_1, t2_2, t2_3, and t2_4, thereby outputting a low level at the cascade output terminal CR, the output signal terminals OUT2 and OUT4, and outputting a high level at the output signal terminals OUT1 and OUT 3.

Thus far, the shift register GOA <1> completes the output of the display driving signal. As shown in fig. 10B, signals output from the output signal terminals OUT1 to OUT4 of the shift register GOA <1> may be used as the second light emission control signal EM2, the second gate driving signal G2, the first light emission control signal EM1, and the first gate driving signal G1 of the above-described pixel driving circuit 10B, respectively.

The other stages of shift registers operate in a similar manner so that each stage of shift register can provide its required plurality of display drive signals to a corresponding row of pixels. Referring to fig. 10A, the first stage shift register GOA <1> generates a first light emission control signal EM1<1>, a second light emission control signal EM2<1>, a first gate driving signal G1<1>, and a second gate driving signal G2<1> for driving the first row of subpixels; the second stage shift register GOA <2> generates a first light emission control signal EM1<2>, a second light emission control signal EM2<2>, a first gate driving signal G1<2> and a second gate driving signal G2<2> for driving the second row of sub-pixels, and so on.

Fig. 11A shows a schematic diagram of a display driving circuit according to another embodiment of the present disclosure. The shift register unit in the display driving circuit may be implemented as the shift register unit of any of the above-described embodiments, for example, the shift register unit described above with reference to fig. 8. The display driving circuit of fig. 11A is similar to the display driving circuit of fig. 9A, and differs at least in the manner of connection of the clock signal terminals, and the details of the differences will be mainly described below.

In the example of fig. 11A, k= 3,i =1, m=4. The N shift register units are also grouped in groups of four, each shift register unit GOA1<1>, GOA1<2>, GOA1< N > having three output units receiving the corresponding three clock signals at the three clock signal terminals CLK1 to CLK3, respectively, and generating three output signals at the three output signal terminals OUT1 to OUT3, respectively. As shown in fig. 11A, taking the first group as an example, the first clock signal terminal CLK1 of the first stage shift register unit GOA1<1> in the first group receives the third narrow clock signal CLK3, the first clock signal terminal CLK1 of the second stage shift register unit GOA1<2> receives the fourth narrow clock signal CLK 4, the first clock signal terminal CLK1 of the third stage shift register unit GOA1<3> receives the first narrow clock signal CLK1, and the first clock signal terminal CLK1 of the fourth stage shift register unit GOA1<4> receives the second narrow clock signal CLK 2. In a similar manner, the second clock signal terminals CLK2 of the shift register units GOA1<1> to GOA1<4> respectively receive the second wide clock signal Clkp2, the third wide clock signal Clkp3, the fourth wide clock signal Clkp4 and the first wide clock signal Clkp1. The third clock signal terminals CLK3 of the shift register units GOA1<1> to GOA1<4> respectively receive the second narrow clock signal CLK2, the third narrow clock signal CLK3, the fourth narrow clock signal CLK 4 and the first narrow clock signal CLK 1.

The clock signal terminals of the other sets of shift register units are connected in the same manner, and are not described here again. Other signal terminals of each shift register unit, such as a control signal terminal, a power signal terminal, and a reference signal terminal, may be connected in the manner described above with reference to fig. 9A, and will not be described again.

The output signals of the output signal terminals OUT1, OUT2, OUT3 of the shift register unit may be used as the light emission control signal EM, the first gate driving signal G1, and the second gate driving signal G2, respectively, required for the above-described pixel circuit 10C. This will be described in detail below with reference to the signal timing of fig. 11B.

Fig. 11B shows a signal timing diagram of the display driving circuit of fig. 11A. As shown in fig. 11B, each shift register unit in the display driving circuit operates in a similar manner to that described above with reference to fig. 9B, except that different clock signals are controlled to generate different display driving signals, and the detailed description of the difference will be mainly provided below.

Referring to fig. 8, 11A and 11B, taking n=1 as an example, the clock signal terminals CLK1 to CLK3 of the shift register unit GOA <1> receive the clock signals CLKs3, clkp2 and CLKs2, respectively.

iN the period T1, the input signal terminal iN of the shift register unit GOA <1> is at a high level, and the transistor T8 of the shift register unit is turned on, thereby providing the signal of the second control signal terminal CKB to the intermediate node P. As can be seen from fig. 9A, the intermediate node P follows the potential of the first control signal cbb received at the second control signal terminal CKB. In this period, since the first clock signal Cka is low, the first control signal terminal Cka of the shift register unit GOA <1> is low, the transistor T14 is in an off state, the pull-up node Q is maintained at a low level, the transistor T3 and the transistors t1_1, t1_2, t1_3 and t1_4 are all in an off state, and the cascade output terminal CR and the output signal terminals OUT1 to OUT4 are all maintained at the original potential, referring to fig. 8.

In the period t2, the first control signal CKA received by the first control signal terminal CKA of the shift register unit GOA <1> is at a high level. Referring to fig. 8, the high level of the first control signal terminal CKA turns on the transistors T14 and T15, and the high level of the input signal terminal IN is supplied to the pull-up node Q and the node QH. The high level of the node QH turns on the transistor T13, and the pull-down node QB is pulled down to the low level of the first reference signal terminal VGL 1. The high level of the pull-up node Q turns on the transistor T3, thereby providing the high level of the first power signal terminal GVDD1 to the cascade output terminal CR (as shown by CR < n > in fig. 10B). The high level of the pull-up node Q also turns on transistors t1_1, t1_2, t1_3, and t1_4. Since the clock signals CLKs3, clkp2, and CLKs2 received by the clock signal terminals CLK1 to CLK3 of the shift register unit GOA <1> are all at low level, the output signal terminals OUT1 to OUT3 are all at low level.

In the period t3 to t5, the shift register unit GOA <1> operates in a similar manner to the period t3 to t5 in fig. 9B, such that the first output unit 350_1 generates an output signal at the first output signal terminal OUT1 based on the clock signal Clks3, the second output unit 350_2 generates an output signal at the output signal terminal OUT2 based on the clock signal Clkp2, and the third output unit 350_3 generates an output signal at the output signal terminal OUT3 based on the clock signal Clks2, as shown in fig. 11B, which will not be repeated here.

In period t6, the clock signals Clks3, clkp2, and Clks2 are all at low level, so that the output signal terminals OUT1 to OUT3 are all at low level. The start signal received by the input signal terminal IN of GOA <1>, the first control signal clk received by the first control signal terminal CKA of the shift register unit GOA <2>, and the second control signal Clkb received by the second control signal terminal CKB are all low levels. Referring to fig. 8, the low level of the input signal terminal IN and the second control signal terminal CKB turns off the transistors T7 and T8, and the intermediate node P remains at the original high level.

IN the period T7, the first control signal clk received at the first control signal terminal CKA of the shift register unit GOA <1> becomes a high level, and referring to fig. 8, the transistors T14 and T15 are turned on, and the low level of the input signal terminal IN is supplied to the pull-up node Q and the node QH. The high level of the first control signal terminal CKA also turns on the transistor T10. The turned-on transistors T9 and T10 supply the high level of the first control signal terminal CKA to the pull-down node QB. The high level of the pull-down node QB turns on the transistor T4 and the transistors t2_1, t2_2, t2_3 and t2_4, thereby outputting a low level at the cascade output terminal CR, the output signal terminals OUT2 and OUT3, and outputting a high level at the output signal terminal OUT 1.

Thus far, the shift register GOA <1> completes the output of the display driving signal. As shown in fig. 11B, signals output from the output signal terminals OUT1 to OUT3 of the shift register GOA <1> may be used as the light emission control signal EM, a gate driving signal G1, and a first gate driving signal G2 of the above-described pixel circuit 10C, respectively.

The other stages of shift registers operate in a similar manner so that each stage of shift register can provide its required plurality of display drive signals to a corresponding row of pixels. Referring to fig. 11A, the first stage shift register GOA <1> generates a light emission control signal EM <1>, a first gate driving signal G1<1>, and a second gate driving signal G2<1> for driving the first row of subpixels; the second stage shift register GOA <2> generates a light emission control signal EM <2>, a first gate driving signal G1<2> and a second gate driving signal G2<2>, and so on, for driving the second row of sub-pixels.

Fig. 12A shows a schematic diagram of a display driving circuit according to another embodiment of the present disclosure. The shift register unit in the display driving circuit may be implemented as the shift register unit of any of the above-described embodiments, for example, the shift register unit described above with reference to fig. 6. The display driving circuit of fig. 12A is similar to the display driving circuit of fig. 9A, and differs at least in the connection manner of the clock signal terminals and the number and duty ratio of the clock signals, and the distinguishing portions will be mainly described in detail below.

In the example of fig. 12A, k=4, i=1, m=16, and the display driving circuit receives 16 narrow clock signals Clks1 to Clks16 and 16 wide clock signals Clkp1 to Clkp16 that are sequentially shifted. The N shift register units are grouped into 16 groups, for example, a first group includes shift register units GOA1<1> to GOA1<16>, a second group includes shift register units GOA1<17> to GOA1<32>, and so on. Each shift register unit GOA1<1>, GOA1<2>, …, GOA1< N > has four output units that receive the corresponding four clock signals at the four clock signal terminals CLK1 to CLK4 and generate the four output signals at the four output signal terminals OUT1 to OUT4, respectively.

As shown in fig. 12A, in the first group, the first clock signal terminals CLK1 of the first to sixteenth stage shift register units GOA1<1> to GOA1<16> are sequentially shifted from the third wide clock signal Clkp3 by 16 wide clock signals, that is, clkp3, clkp4, clkp5, clkp6, clkp7, clkp8, clkp9, clkp10, clkp11, clkp12, clkp13, clkp14, clkp15, clkp16, clkp1, clkp2, respectively. That is, the first clock signal terminal CLK1 at the first stage shift register unit GOA1<1> receives the third wide clock signal Clkp3; the first clock signal terminal CLK1 at the second stage shift register unit GOA1<2> receives the next clock signal shifted with respect to the third wide clock signal Clkp3, i.e., the fourth wide clock signal Clkp4, and so on, until the first clock signal terminal CLK1 at the 16 th stage shift register unit GOA1<16> receives the next clock signal shifted with respect to the first wide clock signal Clkp1, i.e., the second wide clock signal Clkp2.

In a similar manner, the second clock signal terminals CLK2 of the shift register units GOA1<1> to GOA1<16> receive 16 narrow clock signals, i.e., CLK 14, CLK 15, CLK 16, CLK 1, CLK2, CLK3, CLK4, CLK 5, CLK 6, CLK 7, CLK 8, CLK 9, CLK 10, CLK 11, CLK 12, and CLK 13, respectively, shifted sequentially from the fourteenth narrow clock signal CLK 14. The third clock signal terminals CLK3 of the shift register units GOA1<1> to GOA1<16> respectively receive 16 wide clock signals, namely Clkp1 to Clkp16, sequentially shifted from the first wide clock signal Clkp 1. The fourth clock signal terminals CLK4 of the shift register units GOA1<1> to GOA1<16> respectively receive 16 narrow clock signals, i.e., CLKs1 to CLKs16, sequentially shifted from the first narrow clock signal CLKs 1.

The clock signal terminals of the other sets of shift register cells are connected in the same way. For example, for the second group of shift register units GOA1<17> to GOA1<32>, the clock signal terminals of GOA1<17> are connected in the same manner as GOA1<1>, the clock signal terminals of GOA1<18> are connected in the same manner as GOA1<2>, and so on. Other signal terminals of each shift register unit, such as a control signal terminal, a power signal terminal, and a reference signal terminal, may be connected in the manner described above with reference to fig. 9A, and will not be described again.

Each shift register unit may supply the light emission control signal EM, the first gate driving signal G1, the second gate driving signal G2, and the third gate driving signal G3 required for the pixel circuit described above with reference to fig. 1 and 2 at the output signal terminals OUT1, OUT2, OUT3, OUT 4. Unlike fig. 9A and 9B, the compensation period is longer, which will be described in detail below with reference to the signal timing of fig. 12B.

Fig. 12B shows a signal timing diagram of the display driving circuit of fig. 12A. As shown in fig. 12B, each shift register unit in the display driving circuit operates in a similar manner to that described above with reference to fig. 9B, except that different clock signals are controlled to generate different display driving signals, and the detailed description of the difference will be mainly provided below.

As shown in fig. 12B, the display driving circuit receives 16 narrow clock signals Clks1 to Clks16 and 16 wide clock signals Clkp1 to Clkp16 that are sequentially shifted. The narrow clock signals Clks1 to Clks16 have the same period as the wide clock signals Clkp1 to Clkp16, and the duty cycle of the narrow clock signals Clks1 to Clks16 is smaller than that of the wide clock signals Clkp1 to Clkp16. In fig. 12B, the clock periods of the narrow clock signals Clks1 to Clks16 and the wide clock signals Clkp1 to Clkp16 are 16H, the effective level duration of the narrow clock signals Clks1 to Clks16 is 2H, and the effective level duration of the wide clock signals Clkp1 to Clkp16 is 11H.

Referring to fig. 6, 12A and 12B, taking n=1 as an example, the clock signal terminals CLK1 to CLK4 of the shift register unit GOA <1> receive the clock signals Clkp3, CLKs14, clkp1 and CLKs1, respectively.

As shown in fig. 12B, the shift register unit GOA <1> performs substantially the same operation as the periods t7 to t7 described above with reference to fig. 9B during the periods t1 to t7, such that the first output unit 250_1 generates an output signal at the first output signal terminal OUT1 based on the clock signal Clkp3, the second output unit 250_2 generates an output signal at the output signal terminal OUT2 based on the clock signal Clks14, the third output unit 250_3 generates an output signal at the output signal terminal OUT3 based on the clock signal Clkp1, and the fourth output unit 250_4 generates an output signal at the output signal terminal OUT4 based on the clock signal Clks1.

The other stages of shift registers operate in a similar manner so that each stage of shift register can provide its required plurality of display drive signals to a corresponding row of pixels. Referring to fig. 12A, the first stage shift register GOA <1> generates a light emission control signal EM <1>, a first gate driving signal G1<1>, and a second gate driving signal G2<1> for driving the first row of subpixels; the second stage shift register GOA <2> generates a light emission control signal EM <2>, a first gate driving signal G1<2> and a second gate driving signal G2<2>, and so on, for driving the second row of sub-pixels.

The duty ratio difference of the wide clock signal and the narrow clock signal is larger than that of fig. 9B, which makes the period t4 for performing threshold voltage compensation longer, for example, up to 9H in driving the sub-pixel for display using the display driving signal output from the shift register unit, longer than that of fig. 9B. This is advantageous for further reducing the influence of the threshold voltage on the output signal.

Fig. 13A and 13B illustrate circuit diagrams of a display driving circuit according to another embodiment of the present disclosure. The shift register unit in the display driving circuit may be implemented as the shift register unit of any of the above-described embodiments, for example, the shift register unit described above with reference to fig. 6. The display driving circuit of fig. 13A and 13B is similar to the display driving circuit of fig. 9A, except that at least the fourth clock signal terminal CLK4 of each shift register unit is electrically connected to the power signal terminal (the second power signal terminal GVDD 2). In addition, the connection manner of the clock signal terminals in fig. 13A and 13B is also different from fig. 9A in the number and waveform of clock signals. The distinguishing portions will be mainly described in detail hereinafter.

In the examples of fig. 13A and 13B, k=4, i=1, m=8. The display driving circuit receives 8 narrow clock signals Clks1 to Clks8 and 8 wide clock signals Clkp1 to Clkp8, which are sequentially shifted. The N shift register units are grouped into 8 groups, for example, a first group includes shift register units GOA1<1> to GOA1<8>, a second group includes shift register units GOA1<9> to GOA1<16>, and so on. Each shift register unit has four clock signal terminals CLK1 to CLK4 and four output signal terminals OUT1 to OUT4, and generates four output signals at the output signal terminals OUT1 to OUT4 based on signals of the clock signal terminals CLK1 to CLK4, respectively.

As shown in fig. 13A, in the first group, the first clock signal terminals CLK1 of the first to eighth stage shift register units GOA1<1> to GOA1<8> are sequentially shifted from the second wide clock signal Clkp2 by 8 wide clock signals, that is, clkp2, clkp3, clkp4, clkp5, clkp6, clkp7, clkp8, clkp1, respectively. In a similar manner, the second clock signal terminals CLK2 of the shift register units GOA1<1> to GOA1<8> respectively receive 8 narrow clock signals, i.e., CLK 7, CLK 8, CLK1, CLK2, CLK3, CLK4, CLK 5, CLK 6, which are sequentially shifted from the seventh narrow clock signal CLK 7. The third clock signal terminals CLK3 of the shift register units GOA1<1> to GOA1<8> respectively receive 8 narrow clock signals, i.e., CLKs1 to CLKs8, which are sequentially shifted from the first narrow clock signal CLKs 1. The fourth clock signal terminal CLK4 of each of the shift register units GOA1<1> to GOA1<8> is electrically connected to the second power signal terminal GVDD2 of the shift register unit, which allows the fourth clock signal terminal CLK4 to receive the same signal as the second power signal terminal GVDD2, i.e., the second power signal GVDD2.

The clock signal terminals of the other sets of shift register cells are connected in the same way. For example, as shown in fig. 13B, for the second group of shift register units GOA1<9> to GOA1<16>, the clock signal terminals of GOA1<9> are connected in the same manner as GOA1<1>, the clock signal terminals of GOA1<10> are connected in the same manner as GOA1<2>, and so on. Other signal terminals of each shift register unit, such as a control signal terminal, a power signal terminal, and a reference signal terminal, may receive corresponding signals in a manner as described above with reference to fig. 9A, and will not be described again.

The output signals of the four output terminals OUT1 to OUT4 of each stage of the shift register may be used as the light emission control signal EM, the first gate driving signal G1, the second gate driving signal G2, and the third gate driving signal G3 required for the above-described pixel circuit 10B. Unlike fig. 9A, a part of the output signals of one shift register unit and a part of the output signals of the other shift register unit constitute all display driving signals required for a single sub-pixel, which will be described in detail with reference to fig. 13C.

Fig. 13C shows a signal timing chart of the display driving circuit of fig. 13A and 13B.

As shown in fig. 13C, each shift register unit in the display driving circuit operates in a similar manner to that described above with reference to fig. 9B, at least with the difference that two shift register units supply display driving signals to the same row of sub-pixels in cooperation with each other, and the distinguishing portions will be mainly described in detail below.

As shown in fig. 13C, the display driving circuit receives 8 narrow clock signals Clks1 to Clks8 and 8 wide clock signals Clkp1 to Clkp8, which are sequentially shifted. The narrow clock signals Clks1 to Clks8 have the same period as the wide clock signals Clkp1 to Clkp8, and the duty cycle of the narrow clock signals Clks1 to Clks8 is smaller than that of the wide clock signals Clkp1 to Clkp8. In fig. 13C, the duty ratio of the narrow clock signals Clks1 to Clks8 and the clock period of the wide clock signals Clkp1 to Clkp8 are 16H, the effective level duration of the narrow clock signals Clks1 to Clks16 is 1.5H, and the effective level duration of the wide clock signals Clkp1 to Clkp16 is 9H. The shift of the adjacent clock signal is 2H.

Referring to fig. 6, 13A and 13B, taking n=9 as an example, the n-th stage shift register unit GOA <9> is connected to the shift register unit GOA <1>, that is, the clock signal terminals CLK1 to CLK4 respectively receive the clock signals Clkp2, CLKs7, CLKs1 and the second power signal Gvdd2, the first control signal terminal CKA receives the first control signal Clka, and the second control signal terminal CKB receives the second control signal Clkb.

As shown IN fig. 13B, IN the period t1, the signal (i.e., CR <8 >) output from the cascade output terminal of the preceding shift register unit received by the input signal terminal IN of the shift register unit GOA <9> of fig. 13A is at a high level. In this period, since the first control signal clk received by the first control signal terminal CKA of the shift register unit GOA <9> is at a low level, the transistor T14 is in an off state, the pull-up node Q is maintained at a low level, the transistor T3 and the transistors t1_1, t1_2, t1_3 and t1_4 are all in an off state, and the cascade output terminal CR and the output signal terminals OUT1 to OUT4 are all maintained at the original potential.

In the period t2, the first control signal CKA received by the first control signal terminal CKA of the shift register unit GOA <9> is at a high level. Referring to fig. 6, the high level of the first control signal terminal CKA turns on the transistors T14 and T15, and the high level of the input signal terminal IN is supplied to the pull-up node Q and the node QH. The high level of the node QH turns on the transistor T13, and the pull-down node QB is pulled down to the low level of the first reference signal terminal VGL 1. The high level of the pull-up node Q turns on the transistor T3, thereby providing the high level of the first power signal terminal GVDD1 to the cascade output terminal CR. The high level of the pull-up node Q also turns on the transistors t1_1, t1_2, t1_3 and t1_4, and at this time, since the clock signals Clkp2, CLKs7 and CLKs1 received by the clock signal terminals CLK1 to CLK3 of the shift register unit GOA <9> are all at low level, the output signal terminals OUT1 to OUT3 are all at low level; since the second power signal Gvdd2 received by the clock signal terminal CLK4 of the shift register unit GOA <9> is at a high level, the output signal terminal OUT4 is at a high level.

In the period T3 to T5, the pull-up node Q is maintained at a high level, and the transistors t1_1, t1_2, t1_3, and t1_4 in the shift register unit GOA <9> are in an on state, thereby providing Clkp2, clks7, clks1, and Gvdd2 to the output signal terminals OUT1 and OUT4, respectively.

IN the period t6, the first control signal clk received by the first control signal terminal CKA of the shift register unit GOA <9> is at a high level, and the input signal terminal IN is at a low level. Referring to fig. 6, transistors T14 and T15 are turned on, and a low level of an input signal terminal IN is supplied to the pull-up node Q and the node QH. The high level of the first control signal terminal CKA also turns on the transistor T10, thereby providing the high level of the first control signal terminal CKA to the pull-down node QB. The high level of the pull-down node QB turns on the transistor T4 and the transistors t2_1, t2_2, t2_3, and t2_4, thereby outputting a low level at the cascade output terminal CR, the output signal terminals OUT2, OUT3, and OUT4, and outputting a high level at the output signal terminal OUT 1.

Thus far, the shift register GOA <9> completes the output of the display driving signal.

The other stages of shift registers operate in a similar manner to generate output signals at respective four output terminals OUT1 to OUT4.

The output signals of the four output terminals OUT1 to OUT4 of each stage of the shift register may serve as the light emission control signal EM, the first gate driving signal G1, the third gate driving signal G3, and the second gate driving signal G2, respectively. A part of the output signal of one shift register unit may constitute a display driving signal required for a single sub-pixel with a part of the output signal of another shift register unit. For example, the signals output from the output signal terminals OUT1 to OUT3 of the n-th stage shift register GOA < n > may be used as the light emission control signal EM < n-2>, the first gate driving signal G1< n-2>, and the third gate driving signal G3< n-2>, respectively, and the output signal of the output signal terminal OUT4 of the n-2 stage shift register GOA < n-2> may be used as the second gate driving signal G2< n-2> for driving the n-2 th row of sub-pixels. As shown in fig. 13A and 13B, the shift register unit GOA <1> and the shift register unit GOA <3> supply the first row of subpixels with their required display driving signals, specifically, the output signal of the output signal terminal OUT4 of the shift register unit GOA <1> serves as the second gate driving signal G2<1> for driving the first row of subpixels, and the output signals of the output signal terminals OUT1 to OUT3 of the shift register unit GOA <3> serve as the light emission control signals EM <1>, the first gate driving signal G1<1> and the third gate driving signal G3<1> for driving the first row of subpixels. In a similar manner, the output signal terminal OUT4 of the shift register unit GOA <2> and the output signals of the output signal terminals OUT1 to OUT3 of the shift register unit GOA <4> serve as the second gate driving signal G2<2>, the light emission control signal EM <2>, the first gate driving signal G1<2> and the third gate driving signal G3<2> for driving the second row of sub-pixels, and so on. The output signal terminals OUT1 to OUT3 of the first two stages of shift register units GOA <1> and GOA <2> may be set to be redundant (Dummy), i.e., not connected to any sub-pixel.

The embodiment of the disclosure also provides a control method of the shift register unit, which is applicable to the shift register unit of any embodiment. The method may include an input phase, an output phase, and a reset phase.

In the input stage, the input circuit inputs a signal of a first level of an input signal terminal to the pull-up node. In the output stage, the potential of the pull-up node enables the pull-down circuit to pull down the potential of the pull-down node, the potentials of the pull-up node and the pull-down node enable the cascade output circuit to provide signals of the power supply signal end to the cascade output end, and the K output units of the signal output circuit respectively provide signals of the clock signal ends connected respectively to the corresponding output signal ends. In the reset stage, the input circuit inputs a signal of a second level of the input signal end to the pull-up node, the pull-up circuit pulls up the potential of the pull-down node based on the potential of the input signal end, the potentials of the pull-up node and the pull-down node enable the cascade output circuit to provide signals of the reference signal end to the cascade output end, and the K output units of the signal output circuit respectively provide signals of the power signal end or the reference signal end which are respectively connected to the corresponding output signal ends.

Taking the various embodiments described above with reference to fig. 9A to 12B as an example, the input phase may include a period t1, the output phase may include a period t2 to t6, and the reset phase may include a period t7. Taking the embodiment described above with reference to fig. 13A to 13C as an example, the input phase may include a period t1, the output phase may include a period t2 to t5, and the reset phase may include a period t6. The first level may be a high level, and the second level may be a low level.

Fig. 14 shows a schematic view of a display panel according to an embodiment of the present disclosure.

As shown in fig. 14, the display panel displays a driving circuit 410 and a plurality of subpixels 420 arranged in an array. The display driving circuit 410 may be the display driving circuit of any of the above embodiments, for example, the display driving circuit described above with reference to fig. 9A to 12B.

The K output signal terminals of the n-th shift register unit in the display driving circuit 410 are connected to the n-th row of sub-pixels to supply the n-th row of sub-pixels with K display driving signals required by the n-th row of sub-pixels. Taking the display driving circuit 410 implemented by the display driving circuit described above with reference to fig. 9A and 9B as an example, as shown in fig. 14, the 4 output signal terminals of the first stage shift register unit GOA <1> are connected to the first row of sub-pixels through, for example, four signal lines, respectively, to supply the first row of sub-pixels with the first gate driving signal G1<1>, the second gate driving signal G2<1>, the third gate driving signal G3<1> and the light emission control signal EM <1>; the 4 output signal terminals of the second stage shift register unit GOA <2> are connected to the second row of sub-pixels to provide the first gate driving signal G1<2>, the second gate driving signal G2<2>, the third gate driving signal G3<2> and the emission control signal EM <2> to the second row of sub-pixels, and so on. However, embodiments of the present disclosure are not limited thereto, and different display driving circuits may be provided as needed. For example, in the case where the sub-pixel 420 has the circuit structure of the pixel circuit 10B described above, the display driving circuit 410 may be implemented as the display driving circuit described above with reference to fig. 10A and 10B, and each stage of shift register unit supplies the first light emission control signal EM1, the second light emission control signal EM2, the first gate driving signal G1, and the second gate driving signal G2 to the corresponding one row of sub-pixels. For another example, in the case where the sub-pixel 420 has the circuit structure of the pixel circuit 10C described above, the display driving circuit 410 may be implemented as the display driving circuit described above with reference to fig. 11A and 11B, or the like.

The plurality of subpixels 420 also receive data signals through the plurality of data signal lines D1 to DM. Each row of the subpixels 420 emits light based on the received data signal under the control of the display driving signal output from the display driving circuit 410, thereby realizing picture display.

Fig. 15 shows a schematic view of a display panel according to another embodiment of the present disclosure. Unlike fig. 14, the K1 output signal terminals of the n-th stage shift register unit and the K2 output signal terminals of the n+j-th stage shift register unit are connected to the n-th row of sub-pixels to supply K display driving signals to the n-th row of sub-pixels, wherein k1+k2=k, j is an integer greater than 1.

As shown in fig. 15, the display panel displays a driving circuit 510 and a plurality of subpixels 520 arranged in an array. The display driving circuit 510 may be the display driving circuit of any of the above embodiments, for example, the display driving circuit described above with reference to fig. 13A to 13C. In this case, j=2, k1=1, k2=3. Referring to fig. 13A and 13B, one output terminal of the first stage shift register unit GOA <1> and three output terminals of the third stage shift register unit GOA <3> are connected to the first row of sub-pixels to supply display driving signals EM1<1>, G2<1> and G3<1> to the first row of sub-pixels. Specifically, the fourth output signal terminal OUT4 of the shift register unit GOA <1> is connected to the first row of sub-pixels to supply the second gate driving signal G2<1> to the first row of sub-pixels, and the output signal terminals OUT1 to OUT3 of the shift register unit GOA <3> are connected to the first row of sub-pixels to supply the light emission control signal EM <1>, the first gate driving signal G1<1> and the third gate driving signal G3<1> to the first row of sub-pixels. In a similar manner, the output signal terminal OUT4 of the second stage shift register unit GOA <2> and the output signal terminals OUT1 to OUT3 of the fourth stage shift register unit GOA <4> are connected to the second row of sub-pixels to provide the second gate driving signal G2<2>, the light emission control signal EM <2>, the first gate driving signal G1<2> and the third gate driving signal G3<2>, and so on, which are required to drive the second row of sub-pixels. The output signal terminals OUT1 to OUT3 of the first two stages of shift register units GOA <1> and GOA <2> may be set to be redundant (Dummy), i.e., not connected to any sub-pixel.

Those skilled in the art will appreciate that the embodiments described above are exemplary and that modifications may be made by those skilled in the art, and that the structures described in the various embodiments may be freely combined without conflict in terms of structure or principle.

Having described the preferred embodiments of the present disclosure in detail, those skilled in the art will readily appreciate that various changes and modifications may be made without departing from the scope and spirit of the following claims, and that the present disclosure is not limited to the implementations of the exemplary embodiments set forth in the specification.

Claims

1. A shift register unit comprising:

2. The shift register unit according to claim 1, wherein each output unit comprises a first output sub-circuit and a second output sub-circuit, each of the first and second output sub-circuits having a control terminal, an input terminal and an output terminal and being adapted to supply a signal of the input terminal to the output terminal under control of the control terminal;

wherein:

3. The shift register cell according to any one of claims 1 or 2, wherein,

The first output sub-circuit comprises a first transistor and a first capacitor, wherein the grid electrode of the first transistor is used as the control end of the first output sub-circuit, the first pole of the first transistor is used as the input end of the first output sub-circuit, the second pole of the first transistor is used as the output end of the output sub-circuit, the first pole of the first capacitor is connected with the grid electrode of the first transistor, and the second pole of the first capacitor is connected with the second pole of the first transistor;

4. A shift register unit according to any one of claims 1 to 3, wherein one of the K clock signal terminals is electrically connected to a power supply signal terminal.

5. The shift register unit according to any one of claims 1 to 4, wherein the cascade output circuit includes:

6. The shift register cell of claim 5, wherein,

the first cascade sub-circuit comprises a third transistor and a second capacitor, wherein a gate electrode of the third transistor is connected with the pull-up node, a first electrode of the third transistor is connected with the power supply signal end, a second electrode of the third transistor is connected with the cascade output end, a first electrode of the second capacitor is connected with the gate electrode of the third transistor, and a second electrode of the second capacitor is connected with a second electrode of the third transistor;

7. The shift register cell of claim 6, wherein the second cascode sub-circuit further comprises a fifth transistor and a sixth transistor,

8. The shift register unit of any one of claims 1 to 7, wherein the power supply signal terminals comprise a first power supply signal terminal and a second power supply signal terminal, and the reference signal terminal comprises a first reference signal terminal and a second reference signal terminal;

9. The shift register unit according to any one of claims 1 to 8, wherein the pull-up circuit includes:

10. The shift register unit according to claim 9, wherein the first control sub-circuit includes a seventh transistor and an eighth transistor, a gate of the seventh transistor being connected to the second control signal terminal, a first pole of the seventh transistor being connected to the power supply signal terminal, a second pole of the seventh transistor being connected to the intermediate node, a gate of the eighth transistor being connected to the input signal terminal, a first pole of the eighth transistor being connected to the second control signal terminal, a second pole of the eighth transistor being connected to the intermediate node;

11. The shift register cell of claim 10, wherein the first control sub-circuit further comprises an eleventh transistor and a twelfth transistor,

12. The shift register cell of any one of claims 1 to 11, wherein the pull-down circuit comprises a thirteenth transistor having a gate connected to the pull-up node, a first pole connected to the reference signal terminal, and a second pole connected to the pull-down node.

13. A shift register cell according to any one of claims 1 to 12, wherein the input circuit comprises a fourteenth transistor, a gate of the fourteenth transistor being connected to the first control signal terminal of the shift register cell, a first pole of the fourteenth transistor being connected to the input signal terminal, a second pole of the fourteenth transistor being connected to the pull-up node.

14. The shift register cell of claim 13, wherein the input circuit further comprises a fifteenth transistor, a second pole of the fourteenth transistor being connected to the pull-up node through the fifteenth transistor, wherein a gate of the fifteenth transistor is connected to the power supply signal terminal or the first control signal terminal, a first pole of the fifteenth transistor is connected to the second pole of the fourteenth transistor, and a second pole of the fifteenth transistor is connected to the pull-up node.

15. The shift register unit according to any one of claims 1 to 14, further comprising: and the reset circuit is connected with the pull-up node, the pull-down node, the power signal end, the reference signal end and the reset signal end of the shift register unit and is used for providing the signal of the reference signal end to the pull-up node and providing the signal of the power signal end to the pull-down node under the control of the reset signal end.

16. The shift register unit of claim 15, wherein the reset circuit comprises:

17. The shift register cell of claim 16, wherein the reset circuit further comprises an eighteenth transistor, a first pole of the sixteenth transistor being connected to the reference signal terminal through the eighteenth transistor, wherein a gate of the eighteenth transistor is connected to the reset signal terminal, a first pole of the eighteenth transistor is connected to the reference signal terminal, and a second pole of the eighteenth transistor is connected to the first pole of the sixteenth transistor.

18. A shift register unit according to any one of claims 1 to 17, wherein K = 4, wherein one or both of the output units are configured to provide a signal of one of the connected clock signal terminal and the power supply signal terminal to the connected output signal terminal under control of the pull-up node and the pull-down node, and the other output units are configured to provide a signal of one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under control of the pull-up node and the pull-down node.

19. The shift register unit according to any one of claims 1 to 17, wherein K = 3, wherein one of the output units is configured to provide a signal of one of the connected clock signal terminal and power supply signal terminal to the connected output signal terminal under control of the pull-up node and the pull-down node; the other output unit is configured to supply a signal of one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

20. A shift register unit according to any one of claims 1 to 17, wherein the signal output circuit is adapted to generate some or all of K drive signals required to drive a single sub-pixel.

21. A display driving circuit comprising N shift register units connected in cascade, the shift register units being as claimed in any one of claims 1 to 19, wherein a cascade output terminal of an N-th shift register unit is connected to an input signal terminal of an n+i-th shift register unit, wherein N, N and i are both positive integers, and N < N.

22. The display drive circuit of claim 21, wherein the display drive circuit receives M narrow clock signals and M wide clock signals, the narrow clock signals and the wide clock signals having the same period, a duty cycle of the narrow clock signals being less than a duty cycle of the wide clock signals, wherein M is an integer multiple of K;

23. The display drive circuit according to claim 22, wherein k=4, i=1, m=4;

24. The display drive circuit according to claim 22, wherein k=4, i=1, m=4;

25. The display drive circuit according to claim 22, wherein k= 3,i =1, m=4;

26. The display drive circuit according to claim 22, wherein k=4, i=1, m=8;

27. The display drive circuit according to claim 22, wherein k=4, i=1, m=16;

28. A display panel comprising a display drive circuit as claimed in any one of claims 21 to 27 and a plurality of sub-pixels arranged in an array, the display drive circuit being connected to the plurality of sub-pixels to provide display drive signals to the plurality of sub-pixels.

29. The display panel of claim 28, wherein K output signal terminals of the nth stage shift register unit are connected to the nth row of sub-pixels to provide K display driving signals to the nth row of sub-pixels, the K display driving signals including a gate driving signal and a light emission control signal required to drive the row of sub-pixels.

30. The display panel of claim 28, wherein K1 output signal terminals of the n-th stage shift register unit and K2 output signal terminals of the n+j-th stage shift register unit are connected to the n-th row of sub-pixels to supply K display driving signals to the n-th row of sub-pixels, wherein k1+k2=k, j is an integer greater than 1.

31. A control method of a shift register unit according to any one of claims 1 to 20, comprising:

in the input stage, an input circuit inputs a signal of a first level of an input signal end to a pull-up node;

in the output stage, the potential of the pull-up node enables the pull-down circuit to pull down the potential of the pull-down node, the potentials of the pull-up node and the pull-down node enable the cascade output circuit to provide signals of the power supply signal end to the cascade output end, and K output units of the signal output circuit respectively provide signals of the clock signal ends which are respectively connected to the corresponding output signal ends;

in the reset stage, the input circuit inputs a signal of a second level of the input signal end to a pull-up node, the pull-up circuit pulls up the potential of the pull-down node based on the potential of the input signal end, the potentials of the pull-up node and the pull-down node enable the cascade output circuit to provide signals of the reference signal end to the cascade output end, and the K output units of the signal output circuit respectively provide signals of the power signal end or the reference signal end which are respectively connected to the corresponding output signal ends.