CN117275393A

CN117275393A - Pixel circuit, driving method thereof and display panel

Info

Publication number: CN117275393A
Application number: CN202311220394.7A
Authority: CN
Inventors: 袁粲; 李永谦; 王欣欣; 万想
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2023-09-20
Filing date: 2023-09-20
Publication date: 2023-12-22

Abstract

The application discloses a pixel circuit and driving method thereof, and display panel, the pixel circuit of this application embodiment includes: the pixel driving unit comprises at least two light emitting sub-units connected in series, the pixel driving unit comprises a driving control module and a passage selection module, wherein the light emitting unit is electrically connected to a first node and a first power supply signal end, the driving control module is configured to generate driving current based on signals of a row scanning end, and the passage selection module comprises passage selection sub-modules which are in one-to-one correspondence with the light emitting sub-units, each passage selection sub-module is electrically connected to the passage selection end, a control end of the corresponding light emitting sub-unit, and an anode and a cathode of the corresponding light emitting sub-unit, and is configured to select a passage through which the driving current flows based on the signals of the passage selection end and each control end so as to enable the corresponding light emitting sub-unit to emit light. The pixel circuit of the embodiment of the application selects the driving current path through the path selection module, so that the driving circuit is simplified.

Description

Pixel circuit, driving method thereof and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display panel.

Background

Currently, in a display product, a display panel includes a plurality of RGB light emitting units, each of which needs to be designed with an independent light emitting area, and each of which is driven to emit light by a separate pixel driving circuit. However, as resolution requirements for display products become higher, higher requirements are placed on the pixel size of the display products. However, the pixel driving circuit has a complex structure, and the independent pixel driving circuit of each RGB light emitting unit has great difficulty in simplifying the design and the process for the high PPI design, and has great challenges, which restricts the development of the high PPI display field.

Disclosure of Invention

In order to solve at least one of the above problems, a first aspect of the present application provides a pixel circuit, comprising: a pixel driving unit and a light emitting unit, the light emitting unit includes at least two light emitting sub-units connected in series, the pixel driving unit includes a driving control module and a path selection module, wherein

The light emitting unit is electrically connected to the first node and the first power signal terminal,

a driving control module electrically connected to the second power signal terminal, the data input terminal, the reset signal terminal, the row scanning terminal, and the first node, configured to generate a driving current based on the signal of the row scanning terminal, and

The path selection module comprises path selection sub-modules which are in one-to-one correspondence with the light emitting sub-units, each path selection sub-module is electrically connected to the path selection end, the control end of the corresponding light emitting sub-unit, and the anode and the cathode of the corresponding light emitting sub-unit, and the path selection module is configured to select a path through which driving current flows based on signals of the path selection end and the control ends so as to enable the corresponding light emitting sub-unit to emit light.

In some alternative embodiments, the light emitting unit includes a first light emitting subunit, a second light emitting subunit, and a third light emitting subunit, and the path selection module includes: a first path selection sub-module, a second path selection sub-module, and a third path selection sub-module, wherein,

a first path selection sub-module electrically connected to the path selection terminal, the first control terminal, the first node, the third node, and the third power signal terminal, configured to short-circuit the first node with the third node based on a signal of the first control terminal,

a second path selecting sub-module electrically connected to the path selecting terminal, the second control terminal, the third node, the fifth node, and the third power signal terminal, configured to short-circuit the third node with the fifth node based on a signal of the second control terminal,

A third path selecting sub-module electrically connected to the path selecting terminal, the third control terminal, the fifth node, the first power signal terminal, and the third power signal terminal, configured to short-circuit the fifth node with the first power signal terminal based on the signal of the third control terminal, and

the anode of the first light-emitting subunit is electrically connected to the first node, the cathode is electrically connected to the third node, the anode of the second light-emitting subunit is electrically connected to the third node, the cathode is electrically connected to the fifth node, the anode of the third light-emitting subunit is electrically connected to the fifth node, and the cathode is electrically connected to the first power signal terminal.

In some alternative embodiments, the method may include, among other things,

the first path selection submodule includes: the first electrode of the first transistor is electrically connected to the path selection end, the second electrode of the first transistor is electrically connected to the second node, the control electrode of the second transistor is electrically connected to the first control end, the first electrode of the second transistor is electrically connected to the first node, the second electrode of the second transistor is electrically connected to the third node, the control electrode of the second transistor is electrically connected to the second node, the first electrode of the first capacitor is electrically connected to the second node, the second electrode of the first capacitor is electrically connected to the third power signal end,

the second path selection submodule includes: a third transistor, a fourth transistor and a second capacitor, wherein the first electrode of the third transistor is electrically connected to the path selection terminal, the second electrode is electrically connected to the fourth node, the control electrode is electrically connected to the second control terminal, the first electrode of the fourth transistor is electrically connected to the third node, the second electrode is electrically connected to the fifth node, the control electrode is electrically connected to the fourth node, the first electrode of the second capacitor is electrically connected to the fourth node, the second electrode is electrically connected to the third power signal terminal, and

The third path selection submodule includes: the first electrode of the fifth transistor is electrically connected to the path selection end, the second electrode of the fifth transistor is electrically connected to the sixth node, the control electrode of the fifth transistor is electrically connected to the third control end, the first electrode of the sixth transistor is electrically connected to the fifth node, the second electrode of the sixth transistor is electrically connected to the first power supply signal end, the control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the third capacitor is electrically connected to the sixth node, and the second electrode of the third capacitor is electrically connected to the third power supply signal end.

In some alternative embodiments, the drive control module includes: a data writing module, a driving module and a resetting module, wherein,

a data writing module electrically connected to the data input terminal, the row scanning terminal, and the first node, configured to write a signal accessed by the data input terminal into the seventh node based on a signal of the row scanning terminal,

a driving module electrically connected to the second power signal terminal, the first node, and the seventh node and configured to generate a driving current based on a potential of the seventh node, an

The reset module is electrically connected to the row scanning end, the reset signal end and the first node and is configured to reset the first node by using a signal accessed by the reset signal end based on a signal of the row scanning end.

In some alternative embodiments, the method may include, among other things,

the data writing module comprises a seventh transistor, a first electrode of the seventh transistor is electrically connected to the data input end, a second electrode is electrically connected to the seventh node, a control electrode is electrically connected to the row scanning end,

the driving module comprises an eighth transistor and a fourth capacitor, wherein a first electrode of the eighth transistor is electrically connected to the second power supply signal end, a second electrode of the eighth transistor is electrically connected to the first node, a control electrode of the eighth transistor is electrically connected to the seventh node, a first electrode of the fourth capacitor is electrically connected to the seventh node, and a second electrode of the fourth capacitor is electrically connected to the first node.

In some alternative embodiments, the reset module includes a ninth transistor, a first electrode of the ninth transistor is electrically connected to the reset signal terminal, a second electrode of the ninth transistor is electrically connected to the first node, and a control electrode of the ninth transistor is electrically connected to the row scan terminal.

A second aspect of the present application provides a display panel, including: the pixel circuit described above in M rows by N columns, wherein M, N is a positive integer, M, N is greater than 1.

In some alternative embodiments, the via select terminal is electrically connected to a via select signal line, the 2n-1 column and the 2n column pixel circuits share the same via select signal line,

wherein N, N is a positive integer, N is greater than 1, and N is greater than or equal to 1.

In an alternative embodiment, the via select terminal is electrically connected to the via select signal line, the data input terminal is electrically connected to the data signal line, wherein,

the 2n-1 th column and the 2n th column pixel circuits share the same channel selection signal line and share the same data signal line,

in the m-th row pixel circuit, the row scanning end of the 2n-1 th column pixel circuit is electrically connected to the 2m-1 th row scanning line, the row scanning end of the 2 n-th column pixel circuit is electrically connected to the 2 m-th row scanning line,

wherein m and n are positive integers.

A third aspect of the present application provides a driving method for the pixel circuit described above, including, within each image frame: in each of the first period corresponding to the first light emitting subunit, the second period corresponding to the second light emitting subunit, and the third period corresponding to the third light emitting subunit, the driving method includes:

a path selection stage: generating a driving current based on signals of the row scanning end, switching off a path selection module of a light emitting subunit to be emitted in the light emitting unit based on signals of the path selection end and each control end, and shorting anodes and cathodes of the light emitting subunits other than the light emitting subunit to be emitted to select a path through which the driving current flows,

And (3) a light-emitting stage: based on the signal of the line scanning end, the driving current is transmitted to the light emitting subunit to be emitted so as to drive the light emitting subunit to emit light.

The beneficial effects of this application are as follows:

aiming at the existing problems at present, the pixel circuit, the driving method thereof and the display panel are formulated, and the channel selection module of the channel selection sub-module corresponding to the light emitting sub-units one by one and at least two light emitting sub-units connected in series is provided, so that the flowing channel of the driving current is selected in the display process, full-color display can be realized only through channel selection by one pixel circuit, the driving circuit corresponding to each light emitting unit is simplified, the resolution of the display panel is improved, and the display panel has wide application prospect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 illustrates a block diagram of a pixel circuit according to an embodiment of the present application;

FIG. 2 illustrates a schematic diagram of a pixel circuit in accordance with one embodiment of the present application;

FIG. 3 illustrates a key port timing diagram of a pixel circuit according to an embodiment of the present application;

FIGS. 4-15 illustrate circuit on-off schematic diagrams of a pixel circuit according to an embodiment of the present application;

fig. 16 shows a monochrome gradation development view when the pixel circuit according to the embodiment of the present application realizes full-color display;

fig. 17 shows a circuit schematic of a pixel circuit included in a display panel according to another embodiment of the present application;

fig. 18 shows a circuit schematic of a pixel circuit included in a display panel according to another embodiment of the present application;

fig. 19 shows a timing diagram of key ports of the display panel according to the embodiment shown in fig. 18.

Detailed Description

For a clearer description of the present application, the present application is further described below with reference to preferred embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is intended to be illustrative, and not restrictive, and that this invention is not to be limited to the specific embodiments shown.

It is to be noted that unless otherwise defined, technical or scientific terms used in the present disclosure should be taken in a general sense as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used are symmetrical, the source and drain are indistinguishable. In the embodiment of the invention, in order to distinguish the source electrode and the drain electrode of the transistor, one electrode is called a first electrode, the other electrode is called a second electrode, and the gate electrode is called a control electrode. In addition, the transistors may be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, N-type transistors are described, where when N-type transistors are used, the first electrode is the drain of the N-type transistor, the second electrode is the source of the N-type transistor, when the gate inputs a high level, the source and drain are turned on, the P-type is opposite, and when the gate inputs a low level, the source and drain are turned on. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without undue burden and therefore are within the scope of embodiments of the present invention.

To solve at least one of the above problems, an embodiment of the present application provides a pixel circuit, including: a pixel driving unit and a light emitting unit, the light emitting unit includes at least two light emitting sub-units connected in series, the pixel driving unit includes a driving control module and a path selection module, wherein

the path selection module comprises path selection sub-modules which are in one-to-one correspondence with the light emitting sub-units, each path selection sub-module is electrically connected to the path selection end, the control end of the corresponding light emitting sub-unit and the anode and the cathode of the corresponding light emitting sub-unit, and the path selection module is configured to select a path through which driving current flows based on signals of the path selection end and the control ends so as to enable the corresponding light emitting sub-unit to emit light.

In this embodiment, by providing at least two light emitting subunits connected in series and a path selection module of a path selection sub-module corresponding to the light emitting subunits one by one, a flowing path of a driving current is selected in a display process, so that full color display can be realized only by path selection through one pixel circuit, a driving circuit corresponding to each light emitting unit is simplified, thereby improving resolution of a display panel and having a wide application prospect.

In order to describe in detail the structural and functional advantages of the redundant pixel circuits in the embodiments of the present application, a detailed description is provided below in connection with specific examples.

In a specific example, with continued reference to fig. 1 and 2, the pixel circuit includes: a pixel driving unit including a driving control module 10 and a path selection module 20, and a light emitting unit 30 including three light emitting sub-units D1, D2, and D3 connected in series. The light emitting units may be organic light emitting diodes connected in series, micro light emitting diodes (Micro Light Emitting Diodes, abbreviated as Micro LEDs) connected in series, or other light emitting devices which emit light of different colors through a plurality of sub light emitting units to synthesize full color pixels.

In addition, it should be noted that, although the light emitting unit 30 includes three light emitting sub-units D1, D2, and D3 connected in series in this example, the purpose of this is to illustrate that the embodiments of the present application can drive three color light emitting sub-units simultaneously with one pixel driving module to realize full color display in cooperation, so that full color display with one pixel opening can be realized with the design of the present application.

This is by way of example only and is not intended to be limiting. In some application products, the pixel circuit of the embodiment of the application may be used in combination with a conventional pixel circuit, that is, one light emitting unit includes two light emitting sub-units connected in series, and by combining with another light emitting unit, a pixel is formed, and by combining the two light emitting sub-units, full-color display is achieved together. That is, one pixel of full-color display includes at least two pixel openings, for example, one emitting red light and blue light and the other emitting green light, thereby simplifying a driving circuit and improving resolution relative to the related art. It will also be appreciated by those skilled in the art that when the light emitting unit comprises two light emitting sub-units connected in series, the number of corresponding path selection modules is also two. The following description will take as an example that the light emitting unit comprises three light emitting sub-units connected in series.

Specifically, the light emitting unit 30 is electrically connected to the first node N1 and the first power signal terminal VSS. The driving control module 10 is electrically connected to the second power signal terminal VDD, the Data input terminal Data, the reset signal terminal Sense, the row scan terminal G1, and the first node N1, and configured to generate a driving current based on a signal of the row scan terminal G1. The path selection module 20 includes path selection sub-modules 21, 22, and 23 in one-to-one correspondence with the light emitting sub-units D1, D2, and D3, each of which is electrically connected to the path selection terminal DA, the control terminal G2 or G3 or G4 of the corresponding light emitting sub-unit, and the anode and cathode of the corresponding light emitting sub-unit, and is configured to select a path through which a driving current flows based on signals of the path selection terminal GA and the respective control terminals to cause the corresponding light emitting sub-unit to emit light.

The specific circuit configuration of the present example is described below with reference to fig. 1 and 2.

Referring to fig. 2, the drive control module 10 includes: a data writing module 11, a driving module 12, and a resetting module 13. The Data writing module 11 is electrically connected to the Data input terminal Data, the line scanning terminal G1, and the first node N1, and configured to write a signal accessed by the Data input terminal Data into the seventh node N7 based on a signal of the line scanning terminal G1; the driving module 12 is electrically connected to the second power signal terminal VDD, the first node N1, and the seventh node N7, and configured to generate a driving current based on a potential of the seventh node N7; the reset module 13 is electrically connected to the line scan terminal G1, the reset signal terminal Sense, and the first node N1, and is configured to reset the first node N1 by using a signal accessed by the reset signal terminal Sense based on a signal of the line scan terminal G1.

It should be noted that, although fig. 2 shows that the driving control module is composed of 3 transistors and one capacitor (3T 1C architecture), the present application is not intended to limit the specific circuit structure of the driving control module, as long as the circuit capable of generating the driving current based on the control of the row scanning terminal G1 is all possible. The specific functions of the module will be further described below with reference to timing diagrams, which are not described herein.

In particular, referring to fig. 1, the path selection module 20 includes: the light emitting unit 30 includes a first light emitting sub-unit D1, a second light emitting sub-unit D2, and a third light emitting sub-unit D2, a first path selecting sub-module 21, a second path selecting sub-module 22, and a third path selecting sub-module 23.

Referring to fig. 1, the first path selecting sub-module 21 is electrically connected to the path selecting terminal DA, the first control terminal G2, the first node N1, the third node, and the third power signal terminal, for example, ground (not specifically labeled), and configured to short-circuit the first node N1 and the third node N3 based on the signal of the first control terminal G2. The second path selecting sub-module 21 is electrically connected to the path selecting terminal DA, the second control terminal G3, the third node N3, the fifth node N5, and the third power signal terminal, and configured to short-circuit the third node N3 with the fifth node N5 based on the signal of the second control terminal G3. The third path selecting sub-module 23 is electrically connected to the path selecting terminal DA, the third control terminal G4, the fifth node N5, the first power signal terminal VSS, and the third power signal terminal, and configured to short-circuit the fifth node N5 with the second power signal terminal VSS based on the signal of the third control terminal G4.

In addition, the anode of the first light emitting subunit D1 is electrically connected to the first node N1, the cathode is electrically connected to the third node N3, the anode of the second light emitting subunit D2 is electrically connected to the third node N3, the cathode is electrically connected to the fifth node N5, the anode of the third light emitting subunit D3 is electrically connected to the fifth node N5, and the cathode is electrically connected to the first power signal terminal VSS.

Specifically to the present example, referring to fig. 2, the first path selection sub-module 21 includes: a first transistor T1, a second transistor T2 and a first capacitor Cst1. The first electrode of the first transistor T1 is electrically connected to the pass select terminal DA, the second electrode is electrically connected to the second node N2, the control electrode is electrically connected to the first control terminal G2, the first electrode of the second transistor T2 is electrically connected to the first node N1, the second electrode is electrically connected to the third node N3, the control electrode is electrically connected to the second node N2, the first electrode of the first capacitor Cst1 is electrically connected to the second node N2, and the second electrode is electrically connected to the third power signal terminal.

The second path selection sub-module 22 includes: a third transistor T3, a fourth transistor T4 and a second capacitor Cst2. The first electrode of the third transistor T3 is electrically connected to the pass select terminal DA, the second electrode is electrically connected to the fourth node N4, the control electrode is electrically connected to the second control terminal G3, the first electrode of the fourth transistor T4 is electrically connected to the third node N3, the second electrode is electrically connected to the fifth node N5, the control electrode is electrically connected to the fourth node N4, the first electrode of the second capacitor Cst2 is electrically connected to the fourth node N4, and the second electrode is electrically connected to the third power signal terminal.

The third path selection module 23 includes: a fifth transistor T5, a sixth transistor T6 and a third capacitor Cst3. The first pole of the fifth transistor T5 is electrically connected to the pass select terminal DA, the second pole is electrically connected to the sixth node N6, the control pole is electrically connected to the third control terminal G4, the first pole of the sixth transistor T6 is electrically connected to the fifth node N5, the second pole is electrically connected to the first power signal terminal VSS, the control pole is electrically connected to the sixth node N6, the first pole of the third capacitor Cst3 is electrically connected to the sixth node N6, and the second pole is electrically connected to the third power signal terminal.

Illustratively, further specifically to the drive control module 10, referring to fig. 2, in the drive control module 10, the Data writing module 11 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is electrically connected to the Data input terminal Data, a second electrode is electrically connected to the seventh node N7, and a control electrode is electrically connected to the row scan terminal G1. The driving module 12 includes an eighth transistor T8 and a fourth capacitor Cst4, wherein a first electrode of the eighth transistor T8 is electrically connected to the second power signal terminal VDD, a second electrode is electrically connected to the first node N1, a control electrode is electrically connected to the seventh node N7, a first electrode of the fourth capacitor Cst4 is electrically connected to the seventh node N7, and a second electrode is electrically connected to the first node N1. The reset module 13 includes a ninth transistor T9, a first electrode of the ninth transistor T9 is electrically connected to the reset signal terminal Sense, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the row scan terminal G1.

In order to further understand the structure and function of the pixel circuit according to the embodiment of the present application, the following refers to the timing chart of fig. 3 with respect to the example shown in fig. 2, and is described in detail with reference to the circuit on-off charts of fig. 4 to 15.

In this example, the light emitting unit 30 includes a first light emitting sub-unit D1, a second light emitting sub-unit D2, and a third light emitting sub-unit D3 connected in series, each of which emits light of a different color, for example, red light, blue light, and green light, respectively, under driving current. In the present example, it is assumed that the first light emitting sub-unit D1 emits red light R, the second light emitting sub-unit D2 emits blue light B, and the third light emitting sub-unit D3 emits green light G, though it should be understood by those skilled in the art that the light emitting types and order of the three light emitting sub-units are not limited.

In this embodiment, under the cooperation of the driving control module 10 and the path selection module 20, in one frame of image frame, the first current flow path is gated in a first period of time, the first light emitting subunit D1 is driven to emit light by the driving current with the first gray scale, and the second current flow path is gated in a second period of time, and the second light emitting subunit D2 is driven to emit light by the driving current with the second gray scale; and the third current flow path is gated in a third time period, the third light emitting subunit D3 is driven to emit light by the driving current with a third gray scale, and the first time period, the second time period and the third time period are the sum of the time lengths to form a complete image frame.

In each of the above periods, the specific driving process includes a path selection stage and a light emission stage.

Referring to fig. 3, in a first period, that is, a red R light emission period, the path selection phases t1 to t4 and the light emission phase t5.

It is to be noted that during the path selection stages t1 to t4, the process of producing the drive current by the drive control module 10 and the process of selecting the current path by the path selection module 20 are completed simultaneously.

Specifically, referring to fig. 3, for the driving control module 10, in the period t1 to t4, the row scan terminal G1 is connected to the high level signal, the Data input terminal Data is connected to the gray Data data_r of the red light R, and the reset signal terminal Sense is connected to the reset signal Vini. The seventh transistor T7 and the ninth transistor T9 are turned on, and the grayscale Data data_r of the red light R is written into the seventh node N7 and the reset signal Vini is written into the first node N1 in response to the row scan terminal G1 being connected to the high level signal. That is, the first node N1 is reset based on the reset signal Vini and data writing is performed through the seventh transistor T7.

Meanwhile, the eighth transistor T8 is turned on, and the potential of the first node N1, i.e., the source voltage of the eighth transistor T8, is sensed by the sensing signal line, to externally compensate the threshold voltage of the eighth transistor T8. The specific process may be that the Data signal written in by the Data input terminal Data has the reference potential Vref, the eighth transistor T8 is turned on, the signal of the second power signal terminal VDD charges the sensing signal line connected to the reset signal terminal Sense, the sensing signal line senses the potential of the first node N1 when the eighth transistor T8 is turned off, and transmits the potential to the analog-to-digital converter (ADC), the ADC performs analog-to-digital conversion to obtain the Source voltage of the eighth transistor T8, at this time, there is a relation Vref-vs=vth, the Vth at this time is compared with the voltage value obtained by the last sensing to obtain the drift value of the threshold voltage, for example, if the drift value is shifted by-1V, the drift value is fed back to the chip (Source IC) outputting the Data signal, and the gray-level Data data_r outputted last time is weighted by-1V as the new gray-level Data data_r is accessed to the first pole of the seventh transistor T7 to write the gate of the eighth transistor T8, thereby counteracting the drift effect, and completing the threshold voltage compensation.

In addition, referring to fig. 3, it can be seen that the light emitting unit 30 cannot emit light because the row scan terminal G1 is always turned on the high level signal and the ninth transistor T9 is always turned on the reset signal Vini in the period T1 to T4. That is, the ninth transistor T9 has both the reset function and the threshold compensation function in cooperation with the seventh transistor T7, and also the light emission control function in cooperation with the seventh transistor T7.

From the period t1 to the period t4, it is a process in which the path selection module 20 selects a current path.

Specifically, referring to fig. 3 and 4, in the period T1, the first control terminal G2 and the second control terminal G3 are connected to the high level signal, the third control terminal G4 is connected to the low level signal, the pass select terminal DA is connected to the high level signal Vgh, the fourth transistor T4 in the first pass select sub-module 21 is turned on, the high level signal is written into the second node N2, the second transistor T2 is turned on and charges the first capacitor Cst1, the sixth transistor T6 in the second pass select sub-module 22 is turned on, the high level signal is written into the fourth node N4, the fourth transistor T4 is turned on and charges the second capacitor Cst1, and the eighth transistor T8 in the third pass select sub-module 23 is turned off. In addition, as can be seen by the dashed path in the figure, the reset signal Vini simultaneously resets the third node N3 and the fifth node N5.

Referring to fig. 3 and 5, in the period t2, the first control terminal G2 and the second control terminal G3 still access the high level signal, the third control terminal G4 still access the low level signal, and the path selection terminal DA accesses the low level signal Vgl differently. At this time, the gates of the second transistor T2 and the fourth transistor T4 are turned off by the low level signal Vgl being turned on.

Referring to fig. 3 and 6, in the t3 period, the first control terminal G2 is connected to the low level, the second control terminal G3 and the third control terminal G4 are connected to the high level signal, and the signal connected to the path selection terminal DA becomes the high level Vgh. The first transistor T1 is turned off, the control electrode of the second transistor T2 is also a low level signal when the potential of the first capacitor Cst1 is maintained, and the second transistor T2 is still turned off. While the third and fourth transistors T3 and T4 in the second path selection sub-block 22 and the fifth and sixth transistors T5 and T6 in the third path selection sub-block 23 are all turned on, initially forming the light emitting path of the first light emitting sub-unit D1.

Referring to fig. 3 and 7, in a period t4, the first control terminal G2 and the second control terminal G3 access the low level signal, the third control terminal G4 access the high level signal, and the path selection terminal DA accesses the high level Vgh. The first transistor T1 and the second transistor T2 in the first path selection sub-module 21 are still turned off, the third transistor T3 in the second path selection sub-module 22 is turned off, the second capacitor Cst2 maintains a high potential, the fourth transistor T4 is still turned on, and the fifth transistor T5 and the sixth transistor T6 in the third path selection sub-module 23 are still turned on, thereby maintaining the light emitting path of the first light emitting sub-unit D1.

In the light emitting stage t5, referring to fig. 3 and 8, the row scan terminal G1 is connected to a low level signal, the first control terminal G2, the second control terminal G3 and the third control terminal G4 are connected to a low level signal, the second capacitor Cst2 keeps the potential of the fourth node N4 high, the third capacitor Cst3 keeps the potential of the sixth node N6 high, and other transistors in the path selection module 20 are turned off. The seventh transistor T7 and the ninth transistor T9 are turned off, the eighth transistor T8 operates in a saturation region, and the driving current follows a path indicated by a dotted line in fig. 8, i.e., the second transistor T2 is turned off, the cathodes and anodes of the second and third light emitting sub-units D2 and D2 are all short-circuited, and the first sub-light emitting unit D1 is driven to emit red light in the written data_r gray scale.

It can be seen that, in the period T2 in which the path selection terminal DA is a low level signal, the low level signal controlling the second transistor T2 is written, and in the next period T3, by changing the path selection terminal DA to a high level signal while ensuring that the first control terminal D2 to which the first transistor T1 in the first path selection sub-module 21 is connected is low level, the control terminals of the other path selection modules to which the high level is written are connected to high level, so that only the transistors connected across the anode and cathode of the first light emitting sub-unit D1 are disconnected, that is, the first path selection sub-module 21 is disconnected, the anodes and the cathodes of the second light emitting sub-unit D2 and the third light emitting sub-unit D2 are short-circuited, and the light emitting path corresponding to the first sub-light emitting unit D1 is selected.

With continued reference to fig. 3, in the second period, that is, the blue B light emission period, the path selection phases t6 to t9 and the light emission phase t10.

During the path selection stages t6 to t9, the process of producing the driving current by the driving control module 10 and the process of selecting the current path by the path selection module 20 are completed at the same time.

Specifically, referring to fig. 3, for the driving control module 10, in the period from t6 to t9, the row scan terminal G1 is connected to the high level signal, the Data input terminal Data is connected to the gray level data_b of the blue light B, and the reset signal terminal Sense is connected to the reset signal Vini. The seventh transistor T7 and the ninth transistor T9 are turned on, and the gray-scale Data data_b of the blue light B is written into the seventh node N7 in response to the row scan terminal G1 being connected to the high level signal, and the reset signal Vini is written into the first node N1. That is, the first node N1 is reset based on the reset signal Vini and data writing is performed through the seventh transistor T7.

Meanwhile, the eighth transistor T8 is turned on, and the potential of the first node N1, i.e., the source voltage of the eighth transistor T8, is sensed by the sensing signal line, to externally compensate the threshold voltage of the eighth transistor T8. The specific process may be that the Data signal written in by the Data input terminal Data has the reference potential Vref, the eighth transistor T8 is turned on, the signal of the second power signal terminal VDD charges the sensing signal line connected to the reset signal terminal Sense, the sensing signal line senses the potential of the first node N1 when the eighth transistor T8 is turned off, and transmits the potential to the analog-to-digital converter (ADC), the ADC performs analog-to-digital conversion to obtain the Source voltage of the eighth transistor T8, at this time, there is a relation Vref-vs=vth, the Vth at this time is compared with the voltage value obtained by the last sensing to obtain the drift value of the threshold voltage, for example, if the drift value is shifted by-1V, the drift value is fed back to the chip (Source IC) outputting the Data signal, and the gray-level Data data_b outputted last time is weighted by-1V as the new gray-level Data data_b is accessed to the first pole of the seventh transistor T7 to write the gate of the eighth transistor T8, thereby counteracting the drift effect, and completing the threshold voltage compensation.

In addition, referring to fig. 3, it can be seen that the light emitting unit 30 cannot emit light because the row scan terminal G1 is always turned on the high level signal and the ninth transistor T9 is always turned on the reset signal Vini in the period T6 to T9. That is, the ninth transistor T9 has both the reset function and the threshold compensation function, and also has the light emission control function.

From the period t6 to the period t9, it is a process in which the path selection module 20 selects a current path.

Specifically, referring to fig. 3, in the period t6, the first control terminal G2 and the second control terminal G3 access the high level signal, the third control terminal G4 access the low level signal, and the path selection terminal DA accesses the high level signal Vgh, and the circuit on-off condition is consistent with the period t1 shown in fig. 4. The fourth transistor T4 in the first path selection sub-module 21 is turned on to write a high level signal into the second node N2, the second transistor T2 is turned on and charges the first capacitor Cst1, the sixth transistor T6 in the second path selection sub-module 22 is turned on to write a high level signal into the fourth node N4, the fourth transistor T4 is turned on and charges the second capacitor Cst1, and the eighth transistor T8 in the third path selection sub-module 23 is turned off. In addition, as can be seen by the dashed path in the figure, the reset signal Vini simultaneously resets the third node N3 and the fifth node N5.

Referring to fig. 3 and 9, in the period t7, the first control terminal G2 and the second control terminal G3 still access the high level signal, the third control terminal G4 still access the low level signal, and the path selection terminal DA still access the high level signal Vgh. At this time, the pass select module 20 is turned on except for the fifth transistor T5.

Referring to fig. 3 and 10, in the t8 period, the first control terminal G2 is connected to the low level, the second control terminal G3 and the third control terminal G4 are connected to the high level signal, and the signal connected to the path selection terminal DA becomes the low level Vgl. The first transistor T1 is turned off, the control electrode of the second transistor T2 is still a high level signal under the potential of the first capacitor Cst1, and the second transistor T2 is still turned on. While the third transistor T3 in the second path selection sub-block 22 is turned on and writes a low level signal to the control electrode of the fourth transistor T4, the fourth transistor T4 is turned off, the fifth transistor T5 in the third path selection sub-block 23 is turned on and writes a low level signal to the control electrode of the sixth transistor T6, the sixth transistor T6 is turned off, shorting the anode and cathode of the first sub-light emitting unit D1, and turning the second path selection sub-block 22 off.

Referring to fig. 3 and 11, in a period t9, the first control terminal G2 and the second control terminal G3 access the low level signal, the third control terminal G4 accesses the high level signal, and the signal accessed by the path selection terminal DA becomes the high level Vgh. The first transistor T1 in the first path selection sub-module 21 is still turned off and the second transistor T2 is still turned on; the third transistor T3 in the second path selection sub-module 22 is turned off, the second capacitor Cst2 is kept at a low potential, and the fourth transistor T4 is still turned off; the fifth transistor T5 and the sixth transistor T6 in the third path selection sub-module 23 are turned on, thereby forming a light emitting path of the second light emitting sub-unit D2.

In the light emitting stage t10, referring to fig. 3 and 12, the row scan terminal G1 is connected to a low level signal, the first control terminal G2, the second control terminal G3 and the third control terminal G4 are connected to a low level signal, the first capacitor Cst1 keeps the potential of the second node N2 high, the third capacitor Cst3 keeps the potential of the sixth node N6 high, and other transistors in the path selection module 20 are turned off. The seventh transistor T7 and the ninth transistor T9 are turned off, the eighth transistor T8 operates in a saturation region, the driving current follows a path indicated by a dotted line in fig. 12, that is, the second transistor T2 and the sixth transistor T6 are turned on, the cathodes and anodes of the first light emitting sub-unit D1 and the third light emitting sub-unit D3 are both shorted, the fourth transistor T4 is turned off, and the second sub-light emitting unit D2 is driven to emit blue light in the written data_b gray scale.

It can be seen that, in the period T8 in which the path selection terminal DA is a low level signal, a low level signal for controlling the fourth transistor T4 is written, and in the next period T9, by changing the path selection terminal DA to a high level signal while ensuring that the second control terminal D3 to which the fourth transistor T4 in the second path selection sub-module 22 is connected is low level, and the third control terminal G4 is connected to high level, the second transistor T2 in the first path selection sub-module 21 is kept high level by the first capacitor Cst1, so that only the transistors connected across the anode and cathode of the second light emitting sub-unit D2 are turned off, and the anode and cathode of the first light emitting sub-unit D1 and the third light emitting sub-unit D3 are short-circuited, and the light emitting path corresponding to the second light emitting sub-unit D2 is selected.

With continued reference to fig. 3, in the third period, that is, the green G light emission period, the path selection phases t11 to t14 and the light emission phase t15.

During the path selection stages t11 to t14, the process of producing the driving current by the driving control module 10 and the process of selecting the current path by the path selection module 20 are completed at the same time.

Specifically, referring to fig. 3, for the driving control module 10, in the period t11 to t14, the row scan terminal G1 is connected to the high level signal, the Data input terminal Data is connected to the gray data_b of the green light G, and the reset signal terminal Sense is connected to the reset signal Vini. The seventh transistor T7 and the ninth transistor T9 are turned on, and the gray-scale Data data_g of the green light G is written into the seventh node N7 in response to the row scan terminal G1 being connected to the high level signal, and the reset signal Vini is written into the first node N1. That is, the first node N1 is reset based on the reset signal Vini and data writing is performed through the seventh transistor T7.

Meanwhile, the eighth transistor T8 is turned on, and the potential of the first node N1, i.e., the source voltage of the eighth transistor T8, is sensed by the sensing signal line, to externally compensate the threshold voltage of the eighth transistor T8. The specific process may be that the Data signal written in by the Data input terminal Data has the reference potential Vref, the eighth transistor T8 is turned on, the signal of the second power signal terminal VDD charges the sensing signal line connected to the reset signal terminal Sense, the sensing signal line senses the potential of the first node N1 when the eighth transistor T8 is turned off, and transmits the potential to the analog-to-digital converter (ADC), the ADC performs analog-to-digital conversion to obtain the Source voltage of the eighth transistor T8, at this time, there is a relation Vref-vs=vth, the Vth at this time is compared with the voltage value obtained by the last sensing to obtain the drift value of the threshold voltage, for example, if the drift value is shifted by-1V, the drift value is fed back to the chip (Source IC) outputting the Data signal, and the gray-level Data data_r outputted last time is weighted by-1V as the new gray-level Data data_g is accessed to the first pole of the seventh transistor T7 to write the gate of the eighth transistor T8, thereby counteracting the drift effect, and completing the threshold voltage compensation.

In addition, referring to fig. 3, it can be seen that the light emitting unit 30 cannot emit light because the row scan terminal G1 is always turned on the high level signal and the ninth transistor T9 is always turned on the reset signal Vini in the period T11 to T14. That is, the ninth transistor T9 has both the reset function and the threshold compensation function, and also has the light emission control function.

From the period t11 to the period t14, it is a process in which the path selection module 20 selects a current path.

Specifically, referring to fig. 3, in the period t11, the first control terminal G2 and the second control terminal G3 access the high level signal, the third control terminal G4 access the low level signal, and the path selection terminal DA accesses the high level signal Vgh, and the circuit on-off condition is consistent with the period t1 shown in fig. 4. The fourth transistor T4 in the first path selection sub-module 21 is turned on to write a high level signal into the second node N2, the second transistor T2 is turned on and charges the first capacitor Cst1, the sixth transistor T6 in the second path selection sub-module 22 is turned on to write a high level signal into the fourth node N4, the fourth transistor T4 is turned on and charges the second capacitor Cst1, and the eighth transistor T8 in the third path selection sub-module 23 is turned off. In addition, as can be seen by the dashed path in the figure, the reset signal Vini simultaneously resets the third node N3 and the fifth node N5.

Referring to fig. 3, in the period t12, the first control terminal G2 and the second control terminal G3 still access the high level signal, the third control terminal G4 still access the low level signal, and the path selection terminal DA still access the high level signal Vgh. At this time, the circuit on-off condition is the same as that shown in fig. 9, and referring to fig. 9, the other transistors except the fifth transistor T5 in the path selecting module 20 are turned on.

Referring to fig. 3 and 13, in the period t13, the first control terminal G2 is connected to the low level, the second control terminal G3 and the third control terminal G4 are connected to the high level signal, and the signal connected to the path selection terminal DA is still the high level Vgh. The first transistor T1 is turned off, the control electrode of the second transistor T2 is still a high level signal under the potential of the first capacitor Cst1, and the second transistor T2 is still turned on. While the third transistor T3 in the second path selecting sub-block 22 is turned on, and a high level signal is written to the control electrode of the fourth transistor T4, and the fourth transistor T4 is turned on; the fifth transistor T5 in the third path selection sub-module 23 is turned on and writes a high level signal to the control electrode of the sixth transistor T6, and the sixth transistor T6 is turned on to short-circuit the anodes and cathodes of the first and second light emitting sub-units D1 and D2.

Referring to fig. 3 and 14, in a period t14, the first control terminal G2 and the second control terminal G3 access the low level signal, the third control terminal G4 accesses the high level signal, and the signal accessed by the path selection terminal DA becomes the low level Vgl. The first transistor T1 in the first path selection sub-module 21 is still turned off and the second transistor T2 is still turned on; the third transistor T3 in the second path selection sub-module 22 is turned off, the second capacitor Cst2 is kept at a high potential, and the fourth transistor T4 is still turned on; the fifth transistor T5 in the third path selection sub-module 23 is turned on, and the low level signal Vgl written at the path control terminal DA is written at the control electrode of the sixth transistor T6, and the sixth transistor T6 is turned off, so that the third path selection sub-module 23 is turned off, thereby forming the light emitting path of the third light emitting sub-unit D3.

In the light emitting stage t15, referring to fig. 3 and 15, the row scan terminal G1 is connected to a low level signal, the first control terminal G2, the second control terminal G3 and the third control terminal G4 are connected to low level signals, the first capacitor Cst1 keeps the potential of the second node N2 high and the second capacitor Cst2 keeps the potential of the fourth node N4 high, the third capacitor Cst3 keeps the potential of the sixth node N6 low, and other transistors in the path selection module 20 are all turned off. The seventh transistor T7 and the ninth transistor T9 are turned off, the eighth transistor T8 operates in a saturation region, the driving current follows a path indicated by a dotted line in fig. 15, that is, the second transistor T2 and the fourth transistor T4 are turned on, the cathodes and anodes of the first light emitting sub-unit D1 and the second light emitting sub-unit D2 are both shorted, the sixth transistor T6 is turned off, and the third sub-light emitting unit D3 is driven to emit green light in the written data_g gray scale.

As can be seen, in the period T14 where the path selection terminal DA is a low level signal, the low level signal controlling the sixth transistor T6 is written, and the second transistor T2 in the first path selection sub-module 21 and the fourth transistor T4 in the second path selection sub-module 22 are ensured to maintain a high level by the first capacitor Cst1 and the second capacitor Cst2, so that only the transistors connected across the anode and the cathode of the third light emitting sub-unit D3 are turned off, the anode and the cathode of the first light emitting sub-unit D1 and the second light emitting sub-unit D2 are short-circuited, and the light emitting path corresponding to the third light emitting sub-unit D3 is selected.

As can be seen from the above analysis, in the embodiment of the present application, by providing the path selection modules corresponding to the first sub-light emitting unit D1, the second sub-light emitting unit D2 and the third sub-light emitting unit D3 one by one, each path selection module is composed of two transistors and one capacitor, and is matched with the path selection end through the control end, and the energy storage characteristic of the capacitor is utilized, the low level signal is selectively written to the transistor control electrode connected across the anode and the cathode of the light emitting sub-unit to be light-emitted, and the transistor control electrode connected across the anode and the cathode of the other light emitting sub-unit is maintained at the high level, so that the light emitting sub-units are short-circuited, so that each light emitting sub-unit is driven at a time interval in one image frame according to the respective gray scale light emission, thereby completing the full color display driving of three sub-pixels with one pixel driving unit.

Referring to the single-color gray scale development diagram in fig. 16, in the embodiment of the present application, when driving and displaying the light emitting sub-units with different colors according to their respective gray scales in one image frame in a time period, continuous current can be realized, so that full gray scale display can be realized, and a good display effect is achieved.

In addition, it should be noted that, in the pixel circuit of the embodiment of the application, since each light-emitting subunit is connected in series, and each subpixel is used for driving light to emit light in a time-sharing manner in one image frame to form full-color display, a pixel of full-color display can be formed by one pixel opening, so that the pixel density of the display panel is greatly improved, and the resolution is greatly improved under the same display panel size.

It should be further noted that, in conjunction with the above analysis, it is found that, in the period from t1 to t4, the path selection of the first light emitting subunit D1 is substantially already implemented in the period from t3, but in this embodiment, the period from t4 is still added, which is aimed at, referring to fig. 3, completing the path selection in the process of path selection of the second light emitting subunit D2 and the third light emitting subunit D3 in four periods, and setting the path selection stage of the first light emitting subunit D1 to 4 periods, so that the signal waveforms of the first control end D2, the second control end D3 and the third control end D4 form a shift relationship, and thus, by means of the GOA circuit structure of the display panel row scanning signal, the corresponding control signal is given only by adding the output stage and the corresponding clock, without adding excessive circuit structure, so that the size and the wiring difficulty of the frame are not increased, and the narrow frame design is facilitated.

Based on the same inventive concept, embodiments of the present application also provide the display panel described above, including: the pixel circuit described above in M rows by N columns, wherein M, N is a positive integer, M, N is greater than 1.

It should be noted that, the specific structure of the pixel circuit in the display panel has been described in detail in the above description of the specific circuit structure and function, and will not be described herein.

Through the arrangement, at least two light-emitting subunits can be driven by one pixel driving unit to perform color display, a circuit is simplified, and at least 1/3 pixel openings can be reduced, so that the pixel density is greatly improved.

In some alternative embodiments, referring to fig. 17, the path selection terminal DA is electrically connected to the path selection signal line DA, and the 2N-1 th column and the 2N-th column pixel circuits share the same path selection signal line DA, where N, N is a positive integer, N is greater than 1, and N is greater than or equal to 1, so as to facilitate understanding that the signal ports are identical to the corresponding signal line identifications.

Through the arrangement, the odd-numbered and even-numbered columns of pixels share the same channel selection signal line DA, so that the wiring quantity of the pixel circuits is further reduced, the wiring difficulty and the wiring density are reduced, and the pixel density can be further improved.

Further alternatively, referring to fig. 18, the path selection terminal DA is electrically connected to the path selection signal line DA, the Data input terminal Data is electrically connected to the Data signal line Data, and for convenience of understanding that the signal ports are identical to the corresponding signal line identifications, wherein the 2n-1 th column and the 2 n-th column pixel circuits share the same path selection signal line and share the same Data signal line, the m-th row in the pixel circuits, the 2n-1 th column row scanning terminal of the pixel circuits is electrically connected to the 2m-1 th row scanning line, and the 2 n-th column row scanning terminal of the pixel circuits is electrically connected to the 2 m-th row scanning line, wherein m, n are positive integers.

As can be seen from fig. 18, which shows the pixel circuits of the mth row 2n-1 column and the pixel circuits of the mth row 2n column, fig. 19 shows the timing charts of the critical ports in the two pixel circuits, and in combination with the timing charts, in the first period in one image frame, the 2m-1 th row scanning line is connected to the high level signal to write the gray level Data data_r to the pixel circuits of the mth row 2n-1 column using the common Data signal line, and the 2m th row scanning line is connected to the high level signal to write the gray level Data data_r to the pixel circuits of the mth row 2n column using the common Data signal line in the t1 period and the t2 period; similarly, in the second period, in the t6 period and the t7 period, the 2m-1 th row scanning line is connected with a high-level signal to write the gray-scale Data data_B to the pixel circuit of the 2n-1 th column of the m-th row by using the shared Data signal line, and in the t8 period and the t9 period, the 2 m-th row scanning line is connected with a high-level signal to write the gray-scale Data data_B to the pixel circuit of the 2 n-th column of the m-th row by using the shared Data signal line; in the third period, the 2m-1 th row scanning line is connected to a high level signal to write the gray scale Data data_g to the pixel circuits of the m-th row and the 2n-1 th column by using a common Data signal line in the t11 period and the t12 period, and the 2 m-th row scanning line is connected to a high level signal to write the gray scale Data data_g to the pixel circuits of the m-th row and the 2 n-th column by using a common Data signal line in the t13 period and the t14 period.

With this arrangement, the odd-numbered and even-numbered columns of pixels are shared with the same access selection signal line DA and further shared with the same Data signal line Data, and different Data signals are supplied to the adjacent columns of pixel circuits in a time-division manner by adding one row scanning line, so that the wiring difficulty and the wiring density are reduced, and at the same time, the number of Source ICs is reduced by half, or the number of Source ICs is reduced by half, and the product cost is greatly reduced.

Based on the same inventive concept, embodiments of the present application also provide a driving method using the display panel described in the above embodiments, including, within each image frame: in each of the first period corresponding to the first light emitting subunit, the second period corresponding to the second light emitting subunit, and the third period corresponding to the third light emitting subunit, the driving method includes:

The above driving method and process have been described in detail in describing the functions of the specific pixel circuit in the display panel, and will not be described herein.

According to the driving method, the luminous paths aiming at different luminous sub-pixels are controlled and selected in one image frame according to the time periods, so that the time-period full-color display of a plurality of luminous sub-pixels can be realized through one pixel circuit, the pixel density is greatly improved, and the driving method has a wide application prospect.

It should be apparent that the foregoing examples of the present application are merely illustrative of the present application and not limiting of the embodiments of the present application, and that various other changes and modifications may be made by one of ordinary skill in the art based on the foregoing description, and it is not intended to be exhaustive of all embodiments, and all obvious changes and modifications that come within the scope of the present application are intended to be embraced by the technical solution of the present application.

Claims

1. A pixel circuit, comprising: a pixel driving unit and a light emitting unit, the light emitting unit including at least two light emitting sub-units connected in series, the pixel driving unit including a driving control module and a path selection module, wherein

the driving control module is electrically connected to the second power signal terminal, the data input terminal, the reset signal terminal, the row scanning terminal, and the first node, and is configured to generate a driving current based on the signal of the row scanning terminal

The path selection module comprises path selection sub-modules which are in one-to-one correspondence with the light emitting sub-units, each path selection sub-module is electrically connected to a path selection end, a control end of a corresponding light emitting sub-unit, and an anode and a cathode of the corresponding light emitting sub-unit, and is configured to select a path through which the driving current flows based on signals of the path selection end and each control end so as to enable the corresponding light emitting sub-unit to emit light.

2. The pixel circuit of claim 1, wherein the light emitting unit comprises a first light emitting subunit, a second light emitting subunit, and a third light emitting subunit, the path selection module comprising: a first path selection sub-module, a second path selection sub-module, and a third path selection sub-module, wherein,

The first path selection sub-module is electrically connected to the path selection terminal, the first control terminal, the first node, the third node, and the third power signal terminal, configured to short-circuit the first node with the third node based on a signal of the first control terminal,

the second path selecting sub-module is electrically connected to the path selecting terminal, the second control terminal, the third node, the fifth node, and the third power signal terminal, configured to short-circuit the third node with the fifth node based on a signal of the second control terminal,

the third path selection sub-module is electrically connected to the path selection terminal, a third control terminal, the fifth node, the first power signal terminal, and the third power signal terminal, configured to short-circuit the fifth node with the first power signal terminal based on the signal of the third control terminal, and

the anode of the first light-emitting subunit is electrically connected to the first node, the cathode of the first light-emitting subunit is electrically connected to the third node, the anode of the second light-emitting subunit is electrically connected to the third node, the cathode of the second light-emitting subunit is electrically connected to the fifth node, the anode of the third light-emitting subunit is electrically connected to the fifth node, and the cathode of the third light-emitting subunit is electrically connected to the first power signal terminal.

3. The pixel circuit of claim 2, wherein,

the first path selection submodule includes: a first transistor, a second transistor and a first capacitor, wherein a first pole of the first transistor is electrically connected to the path selection terminal, a second pole is electrically connected to a second node, a control pole is electrically connected to the first control terminal, a first pole of the second transistor is electrically connected to the first node, a second pole is electrically connected to the third node, a control pole is electrically connected to the second node, a first pole of the first capacitor is electrically connected to the second node, a second pole is electrically connected to the third power signal terminal,

the second path selection submodule includes: a third transistor, a fourth transistor and a second capacitor, wherein a first pole of the third transistor is electrically connected to the path selection terminal, a second pole is electrically connected to a fourth node, a control pole is electrically connected to the second control terminal, a first pole of the fourth transistor is electrically connected to the third node, a second pole is electrically connected to the fifth node, a control pole is electrically connected to the fourth node, a first pole of the second capacitor is electrically connected to the fourth node, a second pole is electrically connected to the third power signal terminal, and

4. The pixel circuit of claim 1, wherein the drive control module comprises: a data writing module, a driving module and a resetting module, wherein,

the data writing module is electrically connected to the data input end, the row scanning end and the first node and is configured to write the signal accessed by the data input end into the seventh node based on the signal of the row scanning end,

the driving module is electrically connected to the second power supply signal terminal, the first node, and the seventh node, configured to generate the driving current based on a potential of the seventh node, and

The reset module is electrically connected to the row scanning end, the reset signal end and the first node, and is configured to reset the first node by using a signal accessed by the reset signal end based on a signal of the row scanning end.

5. The pixel circuit of claim 4, wherein,

the data writing module comprises a seventh transistor, a first electrode of the seventh transistor is electrically connected to the data input terminal, a second electrode is electrically connected to the seventh node, a control electrode is electrically connected to the row scanning terminal,

the driving module comprises an eighth transistor and a fourth capacitor, wherein a first pole of the eighth transistor is electrically connected to the second power supply signal end, a second pole of the eighth transistor is electrically connected to the first node, a control pole of the eighth transistor is electrically connected to the seventh node, a first pole of the fourth capacitor is electrically connected to the seventh node, and a second pole of the fourth capacitor is electrically connected to the first node.

6. The pixel circuit of claim 5, wherein the reset module comprises a ninth transistor having a first electrode electrically connected to the reset signal terminal, a second electrode electrically connected to the first node, and a control electrode electrically connected to the row scan terminal.

7. A display panel, comprising: the pixel circuit according to any one of claims 1 to 6,

wherein M, N is a positive integer, M, N is greater than 1.

8. The display panel according to claim 7, wherein the via selection terminal is electrically connected to a via selection signal line, the pixel circuits of columns 2n-1 and 2n share the same via selection signal line,

9. The display panel of claim 7, wherein the via select terminal is electrically connected to a via select signal line, the data input terminal is electrically connected to a data signal line, wherein,

the pixel circuits in columns 2n-1 and 2n share the same channel selection signal line and share the same data signal line,

in the pixel circuit of the m-th row, the row scanning end of the pixel circuit of the 2n-1 th column is electrically connected to the 2m-1 th row scanning line, the row scanning end of the pixel circuit of the 2 n-th column is electrically connected to the 2 m-th row scanning line,

wherein m and n are positive integers.

10. A driving method for the pixel circuit according to claim 1 to 6, comprising, in each image frame: in each of a first period of time corresponding to a first light emitting subunit, a second period of time corresponding to a second light emitting subunit, and a third period of time corresponding to a third light emitting subunit, the driving method includes:

A path selection stage: generating a driving current based on signals of the row scanning end, switching off a path selection module of a light emitting subunit to be emitted in the light emitting unit based on signals of the path selection end and the control ends, and short-circuiting anodes and cathodes of the light emitting subunits other than the light emitting subunit to be emitted to select a path through which the driving current flows,

and (3) a light-emitting stage: and transmitting the driving current to the light emitting subunit to be emitted so as to drive the light emitting subunit to emit light based on the signal of the line scanning end.