CN117274239A - Method for rapidly detecting defects of chip packaging technology - Google Patents
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Abstract
The invention relates to the technical field of defect detection, and provides a method for rapidly detecting defects in a chip packaging process, which comprises the following steps: determining detection positioning features by target feature analysis, performing precision analysis on multiple detection targets to obtain multi-level detection requirements, and constructing a multi-level identification structure by combining defect features; the method comprises the steps of collecting an image of a packaged chip, carrying out region positioning and identification based on positioning characteristics, calibrating the image, carrying out defect identification through a multi-level identification structure, determining process defect information, solving the problem that the defect detection of the conventional chip packaging process can only be carried out after the production of products is finished, and once the defect is found, returning all chips in the same batch of chips to factories, increasing the production cost, reducing the technical problem of production efficiency, realizing the rapid detection of the defects of the chip packaging process, greatly improving the detection efficiency and accuracy, reducing the false detection rate, rapidly and accurately detecting the defects in the chip packaging process, and improving the stability and reliability technical effect of detection results.
Description
Technical Field
The invention relates to the technical field related to defect detection, in particular to a method for rapidly detecting defects in a chip packaging process.
Background
In the current chip packaging process, with miniaturization, chip formation and high performance of package size, the requirements for defect detection of chip packaging become higher and higher. Commonly, the chip packaging production line can adopt the X-ray microscopy technology to identify defects such as lead deformation, cavity and chip base offset, but the X-ray microscopy technology needs to use professional equipment and instruments, and has higher requirements on the skills of operators.
In summary, the defect detection of the conventional chip packaging process in the prior art can only be performed after the production of the product is completed, and once the defect is found, the chips in the same batch of chips need to be returned to the factory, so that the production cost is increased, and the production efficiency is reduced.
Disclosure of Invention
The application provides a rapid detection method for defects of a chip packaging process, and aims to solve the technical problems that conventional defect detection of the chip packaging process in the prior art can only be performed after product production is completed, and once defects are found, chips in the same batch of chips need to be returned to factories, so that production cost is increased and production efficiency is reduced.
In view of the above, the present application provides a method for rapidly detecting defects in a chip packaging process.
In a first aspect of the present disclosure, a method for rapidly detecting a chip packaging process defect is provided, where the method includes: performing detection target feature analysis on a detection packaging process to determine detection positioning features; performing detection precision analysis on multiple detection targets to obtain a multi-level detection requirement; constructing a multi-level identification structure based on the multi-level detection requirement and the detection target defect characteristic, wherein the multi-level identification structure comprises a multi-level identification window; acquiring a detection image of the packaged chip by using detection equipment to obtain a detection image of the packaged chip; constructing a positioning identification module based on the detection positioning characteristics, positioning a detection area of the detection image of the packaged chip by using the positioning identification module, and determining an identification positioning area; performing region calibration on the detection image of the packaged chip by using the identification positioning region; and carrying out defect identification through the calibrated detection image of the packaged chip and the multi-level identification structure to determine process defect information.
In another aspect of the disclosure, a system for rapidly detecting defects in a chip packaging process is provided, where the system includes: the feature analysis module is used for carrying out detection target feature analysis on the detection packaging process and determining detection positioning features; the detection precision analysis module is used for carrying out detection precision analysis on multiple detection targets to obtain multi-level detection requirements; the defect feature detection module is used for constructing a multi-level identification structure based on the multi-level detection requirements and combining detection target defect features, wherein the multi-level identification structure comprises a multi-level identification window; the detection image acquisition module is used for acquiring detection images of the packaged chips by using detection equipment to obtain detection images of the packaged chips; the detection area positioning module is used for constructing a positioning identification module based on the detection positioning characteristics, positioning the detection area of the detection image of the packaged chip by using the positioning identification module, and determining an identification positioning area; the area calibration module is used for carrying out area calibration on the detection image of the packaged chip by utilizing the identification positioning area; and the defect identification module is used for carrying out defect identification through the calibrated packaging chip detection image and the multi-level identification structure to determine process defect information.
One or more technical solutions provided in the present application have at least the following technical effects or advantages:
because the target feature analysis is performed on the packaging technology, the detection positioning feature is determined, the precision analysis is performed on multiple detection targets, the multi-level detection requirement is obtained, and the multi-level identification structure is built by combining the defect feature. The method comprises the steps of collecting and packaging chip images by using detection equipment, carrying out region positioning and identification based on positioning features, calibrating the images, carrying out defect identification through a multi-level identification structure, determining process defect information, realizing rapid detection of chip packaging process defects, greatly improving detection efficiency and accuracy, reducing false detection rate, rapidly and accurately detecting defects in a chip packaging process, and improving the stability and reliability of detection results.
The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.
Drawings
Fig. 1 is a schematic flow chart of a possible method for rapidly detecting defects in a chip packaging process according to an embodiment of the present application;
Fig. 2 is a schematic flow chart of a method for quickly detecting defects in a chip packaging process, where the method may determine detection positioning features;
fig. 3 is a schematic diagram of a possible structure of a system for rapidly detecting defects in a chip package process according to an embodiment of the present application.
Reference numerals illustrate: the device comprises a feature analysis module 100, a detection precision analysis module 200, a defect feature detection module 300, a detection image acquisition module 400, a detection region positioning module 500, a region calibration module 600 and a defect identification module 700.
Detailed Description
Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, in which various details of the embodiments of the present invention are included to facilitate understanding, and are to be considered merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Example 1
As shown in fig. 1, an embodiment of the present application provides a method for rapidly detecting a chip packaging process defect, where the method includes:
Step-1: performing detection target feature analysis on a detection packaging process to determine detection positioning features;
step-2: performing detection precision analysis on multiple detection targets to obtain a multi-level detection requirement;
step-3: constructing a multi-level identification structure based on the multi-level detection requirement and the detection target defect characteristic, wherein the multi-level identification structure comprises a multi-level identification window;
first, the specific process of the chip packaging process and possible defects are thoroughly understood, including knowing the flow of the packaging process, materials and equipment used, and possible problems; then, performing feature analysis to extract features such as shape, size, color, texture, etc. that can be used for detection; the detection positioning feature is a characteristic used for determining the position and the shape of each detection target in the defect detection process, and can provide enough information about the detection targets for subsequent defect detection and identification;
for each inspection target, the requirement of the inspection precision is required to be clear, and can be determined according to the strict degree of the product on the packaging quality, for example, if the packaging quality of one product directly affects the performance and the reliability, the requirement of the inspection precision is higher. Furthermore, the detection accuracy requirements may also be different for different detection targets. Therefore, independent precision analysis is required for each detection target, so that the multi-stage detection requirement is obtained.
After the detection precision requirement of each detection target and the corresponding defect characteristics of each detection target are defined, a multi-level identification structure can be built, and in general, the multi-level identification structure can be a multi-level classifier, the input of the multi-level classifier is a detection image of a packaged chip, and the output of the multi-level classifier is defect information of each detection target. Each level corresponds to a particular inspection accuracy requirement, and each level uses a particular defect signature for defect identification. Thus, the requirement of multi-stage detection can be met.
Each level contains one or more identification windows that correspond to the defective features of that level, e.g., if the defective feature of the first level is a color, then its identification windows may be windows that are classified according to color; each window is then identified for defects using a particular algorithm or model,
the detection target feature analysis is carried out on the detection packaging technology, so that the characteristics and defect types of each detection target can be more deeply known, and basic data are provided for subsequent defect detection and identification; the detection precision analysis is carried out on the multiple detection targets, and different precision requirements can be determined according to different detection targets so as to carry out subsequent grading detection and defect identification; based on the combination of the multi-level detection requirements and the detection target defect characteristics, a multi-level identification structure can be built, so that multi-level defect detection and identification of a packaging process to be detected are realized, and the detection precision and efficiency are improved; through the design and application of the multi-level recognition window, multi-level defect detection and recognition of the packaging process to be detected can be realized, and the detection precision and reliability are improved.
Step-4: acquiring a detection image of the packaged chip by using detection equipment to obtain a detection image of the packaged chip;
step-5: constructing a positioning identification module based on the detection positioning characteristics, positioning a detection area of the detection image of the packaged chip by using the positioning identification module, and determining an identification positioning area;
step-6: performing region calibration on the detection image of the packaged chip by using the identification positioning region;
step-7: and carrying out defect identification through the calibrated detection image of the packaged chip and the multi-level identification structure to determine process defect information.
And using special detection equipment, such as a camera or a scanner, and the like, to acquire images of products of the chip packaging process. The packaged chip inspection image includes various angle views of the packaged chip, or specific functional views, such as pin views, internal structure views, etc., and the acquired image is stored in a digital form in a computer or database for subsequent processing and analysis.
The positioning recognition module is a positioning module constructed based on detection positioning characteristics and is used for positioning detection areas of the detection image of the packaged chip and determining the position and the size of each detection area; on the basis of understanding the structure of the packaged chip and the defect type, a positioning and identifying module is constructed according to the specific characteristics of the defect, the positioning and identifying module can automatically position a corresponding defect area in a detection image through image processing and computer vision technology, and can identify the specific shape, color, texture and other characteristics in the image, so that the possible defect position and shape can be determined.
And (3) calibrating the detection image of the packaged chip by using the defect position information obtained in the last step, and marking the image so that the subsequent processing can be more accurate. Specifically, the image may be divided into different areas by the identified defect area, and each area is marked with information such as what type of defect it belongs to, the degree of defect, and the like.
Inputting the calibrated detection image of the packaged chip into a multi-level identification structure for defect identification, and carrying out multi-level analysis and processing on the image through different levels and hierarchical structures so as to determine different types of defects and corresponding process defect information thereof, wherein the process defect information can comprise the types, positions, sizes, shapes, colors and the like of the defects, and the information of process problems, production reasons and the like deduced according to the information.
The detection equipment is used for carrying out detection image acquisition on the packaged chip, so that a high-quality packaged chip detection image can be obtained, and basic data is provided for subsequent defect detection and identification; a positioning identification module is constructed based on the detection positioning characteristics, so that the module can be used for rapidly and accurately positioning a detection area of a detection image of the packaged chip, and the detection precision and efficiency are improved; the detection image of the packaged chip is subjected to area calibration through the identification positioning area, so that the accurate positioning and identification of the packaging technology to be detected can be realized, and the detection accuracy and reliability are improved; through the calibrated detection image of the packaged chip, defect identification is carried out through a multi-level identification structure, so that comprehensive defect information feedback in the manufacturing process of the packaged chip can be obtained, process optimization and quality control are guided, and the quality and reliability of products are improved.
Further, in the method, as shown in fig. 2, the detecting and encapsulating process is performed with detection target feature analysis to determine detection positioning features, which includes:
performing process stage package analysis on the packaging process to be detected to obtain a process packaging product;
acquiring a product image sample based on the process packaging product to obtain image binarization;
and carrying out binary characteristic analysis according to the image binarization to determine the detection positioning characteristic.
In the process of analyzing the detection target characteristics of the detection packaging process and determining the detection positioning characteristics, the method comprises the following steps: the detection packaging process refers to checking and testing the quality of a chip packaging process to ensure that the product achieves expected performance and reliability; the detection target feature analysis refers to identifying possible defect types and corresponding features of the defects through understanding and analyzing the packaging process for subsequent detection and identification processes; the detection positioning feature is used for accurately positioning possible defects in the packaging process and is a key input in the subsequent detection process; the process stage package analysis refers to analyzing each stage of the chip packaging process, understanding influencing factors and possible defects of each stage, and providing assistance for subsequent feature extraction and detection; the process packaging product refers to a final product after the chip packaging process is finished, and the effect and possible problems of the whole process can be known by analyzing the final product; the process stage package analysis is performed on the packaging process to be tested to know the information of the type, quantity, position and the like of the packages at each stage, which is helpful for determining the testing target.
The image binarization is an image processing technology, and can convert a color image into a black-and-white binary image, so that objects and backgrounds in the image are easier to distinguish, and subsequent feature extraction and detection are facilitated; the binary feature analysis refers to the process of extracting and analyzing features of a binary image after binarizing the image, and can reflect the effect of a packaging process and possible defects; and acquiring a product image sample based on the process packaging product, and performing image binarization processing. Binarization is a method for converting a gray level image into a black-and-white image, and can highlight edge features of the image, so that subsequent feature extraction is more convenient; and (3) performing binary feature analysis according to image binarization to determine detection positioning features. These features may include, but are not limited to, the shape, size, location, color, etc. of the package that may be used to locate and identify defects in the packaging process.
Through collecting the product image sample and binarizing, each part of the packaging process product can be clearly distinguished, possible defect characteristics are extracted, and effective data input is provided for subsequent detection and identification; through binary feature analysis, the detection positioning feature can be accurately determined, an accurate basis is provided for subsequent defect detection and identification, and the detection accuracy and efficiency are effectively improved. In general, the comprehensive analysis of the packaging technology to be detected is realized, the detection positioning characteristics are accurately determined, and the subsequent defect detection and identification support is realized.
Further, the method of the present application performs binary feature analysis according to the image binarization, and determines the detection positioning feature, including:
performing binary numerical distribution feature analysis according to image binarization to determine binary partition features;
collecting the characteristic area of the binary partition to obtain an area difference value;
when the area difference value reaches a preset requirement, determining the partition characteristic with the largest area as the detection positioning characteristic;
when the area difference value does not reach the preset requirement, two adjacent subareas with the largest adjacent area binarization difference degree are determined, and after subarea combination is carried out, the subareas are used as the detection positioning characteristics.
Performing binary feature analysis according to image binarization, and determining detection positioning features, wherein the method comprises the following steps of: image binarization refers to a process of converting a color image into a black-and-white image, and is also called binarization processing of an image. In the binarized image, all pixels have only two possible values, which are typically used to simplify the image data for more efficient computation and analysis; binary feature analysis is to analyze features in an image, such as shape, size, texture and the like, on the basis of a binary image; dividing the image into different areas or objects through binary value distribution characteristic analysis, wherein the areas or objects are called binary partition characteristics; and carrying out binary numerical distribution characteristic analysis according to image binarization to determine binary partition characteristics. Specifically, the numerical distribution of the binarized image can be observed, and through statistics and analysis, areas with more concentrated numerical distribution in the image can be found, and the areas can be the manifestations of different encapsulants or specific parts in the encapsulation process.
The area difference value is obtained by calculating the area of each binary partition characteristic, and finding out two or more adjacent partitions with the largest area difference; and acquiring the characteristic area of the binary partition, and obtaining an area difference value. By calculating the areas of the different binary partition features, partition features with significant differences in area can be found, which may be specific parts or abnormal areas in the encapsulation process.
The partition feature with the largest area is that among all binary partition features, the partition feature with the largest area usually contains more information and is selected as a detection positioning feature; the binarization difference degree of the adjacent areas is an index for measuring the difference degree of the two adjacent partitions after binarization, and when the area difference of the two adjacent partitions is maximum, the binarization difference degree between the two adjacent partitions is also maximum; when the area difference value reaches a preset requirement, the partition characteristic with the largest area can be determined as the detection positioning characteristic. If the area difference of the features of different binary partitions is smaller and does not meet the preset requirement, two adjacent partitions with the largest adjacent area binarization difference degree can be determined through further calculation and analysis. The two adjacent partitions are combined in a partition mode and can be used as detection positioning features. The combination of these two adjacent partitions can better reflect specific portions or abnormal areas in the encapsulation process, thereby more accurately performing defect detection.
Through binarization processing of the image, the image can be converted into a binarized image which is easier to analyze and process; different areas or objects in the image can be effectively identified through binary numerical distribution feature analysis; the saliency of different partitions can be quantitatively evaluated by calculating the areas of the features of each binary partition, and the method is very helpful for determining the detection positioning features; when the area difference value reaches a preset requirement, selecting the partition with the largest area as a detection positioning feature, so that possible defects can be accurately positioned; when the area difference value does not reach the preset requirement, two adjacent subareas with the largest adjacent area binarization difference degree are selected for combination, so that defects can be effectively positioned to areas with finer granularity, and the detection precision is improved; in general, this process can accurately determine the detected positional features by binarizing and feature analysis of the image.
Furthermore, in the method of the present application, the detecting accuracy analysis is performed on the multiple detecting targets to obtain a multi-stage detecting requirement, which includes:
acquiring a plurality of detection targets of a multi-detection packaging process;
performing defect detection feature analysis on the plurality of detection targets to determine target detection defects and detection precision requirements;
And classifying according to the detection precision requirements based on target detection defects and the detection precision requirements of multiple detection targets to obtain the multi-stage detection requirements.
The detection precision analysis is carried out on the multiple detection targets, and the multi-stage detection requirements are obtained, specifically: the multi-detection packaging process refers to the need to detect a plurality of packaging processes, which may be caused by different packaging process steps, different packaging materials or different packaging devices; the detection target refers to quality characteristics or performance indexes to be detected in the multi-detection packaging process, for example, the yield, the packaging size precision, the characteristics of packaging materials and the like of the packaging process can be the detection target; the defect detection feature analysis refers to deep understanding and analysis of defects of each detection target, and the form, the property, the generation reason, the influence on the product performance and the like of each defect are clear, so that a basis is provided for subsequent detection and identification; the target detection defect refers to a method for detecting possible defects of each detection target and determination of characteristics after defect detection feature analysis, for example, for detecting the size precision of the package, the position, the size, the shape and the like of the packaged chip may need to be detected to determine whether defects such as position deviation, size deviation and the like exist; the detection accuracy requirement refers to a detection accuracy standard which needs to be achieved when detecting the defects of each detection target, and the detection accuracy requirement may be influenced by various factors such as product performance requirement, market demand, production cost and the like.
Acquiring a plurality of detection targets of the multi-detection packaging process, including various packages, structures, functions and the like, and needing to be understood and analyzed in detail so as to determine the characteristics and requirements of each detection target; performing defect detection feature analysis on a plurality of detection targets, determining the requirements of target detection defects and detection precision, namely simply needing to know the defect type and the characteristics of each detection target in depth, analyzing the influence of the defects on the performance of a product, and determining the required detection precision;
based on the target detection defects and the detection precision requirements of multiple detection targets, grading is carried out according to the detection precision requirements to obtain multi-stage detection requirements, namely the precision requirements of each detection target are simply required to be analyzed and evaluated, the detection targets are classified into different grades according to the difference of the precision requirements, and then corresponding detection strategies and methods are determined for each stage to form the multi-stage detection requirements.
The defect detection characteristic analysis is carried out on a plurality of detection targets, so that the form, the property, the generation reason, the influence on the product performance and the like of each defect can be clarified, and the accuracy and the efficiency of detection can be improved; the defects can be classified and ordered according to different detection precision requirements based on target detection defects and detection precision requirements of multiple detection targets, and clear basis and guidance are provided for subsequent multi-stage detection; in general, the process can realize comprehensive and systematic analysis of the packaging technology to be detected, accurately determine the defects and the detection method of each detection target, classify and sort the targets according to the precision requirement, and provide effective help for subsequent multi-stage detection.
Furthermore, the method of the present application builds a multi-level recognition structure based on the multi-level detection requirement in combination with the detection target defect feature, wherein the multi-level recognition structure comprises a multi-level recognition window, and the method comprises:
determining target detection defects and detection precision requirements based on the multi-level detection requirements, and acquiring the detection target defect characteristics and recognition window parameters from a training database according to the target detection defects and detection precision requirements;
performing window parameter fusion optimization analysis according to a plurality of identification window parameters corresponding to the multiple detection targets, and determining multi-level window parameters;
and constructing a multi-level recognition window based on the multi-level window parameters, and constructing the multi-level recognition structure according to the connection of the multi-level recognition window from small to large.
Based on the combination of multi-level detection requirements and detection target defect characteristics, a multi-level identification structure is built, wherein the multi-level identification structure comprises a multi-level identification window, and the specific refinement steps comprise: the multi-stage detection requirements are obtained by classifying the detection precision requirements of a plurality of detection targets, are formulated aiming at the defect detection characteristics and the detection precision requirements of each detection target, and provide guidance for subsequent defect detection; the training database is a database containing known, labeled sample data for training machine learning or deep learning models so that the models can learn how to identify and classify different defects and features; the defect characteristics and the identification window parameters of the detection targets are obtained by machine learning and training aiming at the defects of each detection target in a training database, and are used for identifying and classifying different defects; the window parameter fusion optimization analysis is a process of carrying out fusion analysis on a plurality of identification window parameters, and optimal multi-level window parameters are optimized and selected by comprehensively considering the advantages and disadvantages of different window parameters; the multi-level window parameters are parameters of the multi-level identification window determined after fusion optimization analysis and are used for constructing the multi-level identification window; the multi-level recognition windows are constructed based on multi-level window parameters, each window has own recognition targets and precision requirements, and the windows are connected in sequence from small to large to form a multi-level recognition structure.
Analyzing the characteristics and the requirements of each detection target, and determining the defect type and the required detection precision of each detection target; searching and analyzing defect characteristics and recognition window parameters in a training database, and finding out characteristics and parameters matched with the defect type and precision requirements of the current detection target; analyzing and optimizing the identification window parameters of each detection target, and finding out the optimal multi-level window parameter combination; constructing corresponding multi-level identification windows according to the determined multi-level window parameters, wherein each window corresponds to the defect characteristic and the precision requirement of one detection target; and connecting and analyzing each hierarchical recognition window to construct a complete multi-level recognition structure.
The defect detection method has the advantages that the defect detection and the detection precision requirements of the target are determined based on the multi-level detection requirements, and corresponding defect characteristics and recognition window parameters of the detection target are obtained from the training database, so that the defect detection is more accurate and efficient; fusion optimization analysis is carried out on a plurality of identification window parameters, and multi-level window parameters are determined, so that defect detection is more accurate and reliable, and the quality and reliability of products are improved; the multi-level recognition windows are constructed based on the multi-level window parameters and are connected in sequence from small to large, so that a multi-level recognition structure can be formed, and defect detection is more comprehensive; in general, the process can realize comprehensive, systematic and accurate defect detection of the packaging process to be detected by determining the multi-level detection requirements, acquiring corresponding detection target defect characteristics and recognition window parameters, carrying out window parameter fusion optimization analysis and constructing a multi-level recognition structure.
Further, according to the method of the present application, the window parameter fusion optimization analysis is performed according to a plurality of identification window parameters corresponding to multiple detection targets, and a multi-level window parameter is determined, including:
according to a plurality of the identification window parameters, sequencing from small to large according to the parameters to obtain a window parameter sequence;
acquiring a minimum recognition window parameter based on the window parameter sequence;
performing iterative decomposition on a second window parameter based on the minimum recognition window parameter, and determining a second window decomposition parameter, wherein the iterative result of the second window decomposition parameter and the minimum recognition window parameter is the same as the second window parameter;
and similarly, completing iterative analysis of all parameters in the window parameter sequence, and constructing the multi-level window parameters.
According to a plurality of identification window parameters corresponding to a plurality of detection targets, window parameter fusion optimization analysis is carried out, and the method for determining the multi-level window parameters is specifically thinned as follows: the plurality of recognition window parameters are obtained by performing detection feature analysis and determination of accuracy requirements on defects of each detection target. The parameters are used for constructing a multi-level identification window to identify and classify defects; the window parameter sequence is a sequence obtained by sequencing a plurality of identification window parameters according to the sequence of the parameters from small to large; the minimum recognition window parameter is the first parameter in the window parameter sequence and is also the minimum precision requirement of defect recognition; the second window decomposition parameter is obtained in the process of carrying out iterative decomposition on the rest window parameters after the minimum recognition window parameter is determined, and the parameter is the same as the iterative result of the minimum recognition window parameter and is used for ensuring the precision requirement of the multi-level recognition window.
Sequencing the identification window parameters of each detection target from small to large to form a window parameter sequence; finding out the minimum window parameter in the sequence, wherein the minimum defect characteristic and the detection precision requirement of the detection target correspond to the minimum window parameter; based on the minimum recognition window parameter, decomposing and calculating the second window parameter to find out the same decomposition parameter; and sequentially carrying out iterative decomposition on each window parameter, finding out the corresponding decomposition parameter, and forming a complete multi-stage window parameter.
According to a plurality of identification window parameters, sequencing from small to large according to the parameters to obtain a window parameter sequence, so that the accuracy requirement of defect detection can be gradually improved, and a multi-level identification structure is formed; acquiring a minimum recognition window parameter, which is the minimum precision requirement of defect recognition and is also the starting point of a multi-level recognition structure; performing iterative decomposition on the second window parameters based on the minimum recognition window parameters, and determining the second window decomposition parameters, so that the precision requirement of the multi-level recognition structure can be gradually improved, and the precision requirement of each level is ensured to meet the expectations; by analogy, the iterative analysis of all parameters in the window parameter sequence is completed, multi-level window parameters are constructed, a multi-level identification structure meeting expectations can be obtained, and accurate defect detection of each detection target is realized; in general, a multi-level recognition structure meeting expectations can be obtained by performing fusion optimization analysis on a plurality of recognition window parameters, determining multi-level window parameters, and performing iterative decomposition on the multi-level window parameters.
Further, the method of the present application, the obtaining the defect feature of the detection target and the identification window parameter from the training database, previously includes:
collecting a detection target defect sample of a detection packaging process, carrying out defect detection on the detection target defect sample, and determining a defect detection characteristic sample and corresponding identification window parameters;
performing defect recognition training based on the defect detection feature sample to obtain the detection target defect feature and a corresponding recognition window parameter;
and establishing a mapping relation between the defect characteristics of the detection target and the corresponding recognition window parameters, and constructing the training database.
The process of obtaining the defect characteristics of the detection target and the identification window parameters from the training database further comprises the following steps: the detection target defect sample is sample data which is acquired from the actual packaging process production process and contains different types of defects and is used for inputting a training model; the defect detection characteristic sample is a characteristic sample of the defect extracted in the defect detection process and is used for inputting a training model; the identification window parameter is a set of parameters that need to be set for each feature of the detection target defect in the defect detection process, and is used for determining the window size, the threshold value, and the like of defect identification.
Sampling defects in the detection packaging process to obtain representative defect samples, wherein the samples cover various possible defect types and characteristics; detecting and analyzing the collected defect samples, finding out the characteristics capable of accurately identifying the defects, and determining corresponding identification window parameters; training and learning the defect detection feature sample by using a training data set and a machine learning algorithm to obtain an accurate defect recognition model, and obtaining recognition window parameters corresponding to each defect type and feature; and establishing a mapping relation between the defect characteristics and the recognition window parameters according to the defect recognition model and the training result, and storing the mapping relation in a training database so as to facilitate subsequent defect detection and recognition.
The defect detection characteristic samples and the corresponding identification window parameters can be obtained by collecting detection target defect samples of a detection packaging process and carrying out defect detection on the samples, so that data input is provided for subsequent training; performing defect recognition training based on the defect detection feature samples can enable the model to learn how to perform defect recognition according to the feature samples and how to adjust recognition window parameters to achieve higher accuracy; by establishing a mapping relation between the defect characteristics of the detection target and the corresponding identification window parameters, the model can quickly find the corresponding identification window parameters according to different characteristic samples in the defect identification process, and efficient defect identification is realized; the training database is constructed, enough data can be provided for training and learning of the model, so that the accuracy and the robustness of the model are improved, and powerful support is provided for subsequent defect detection and identification; in general, defect recognition training is performed and a mapping relation is established through collecting and detecting a detection target defect sample of a packaging process, and a training database is constructed, so that powerful data support is provided for the subsequent construction of a multi-stage detection structure.
Further, in the method of the present application, the detecting the image by the calibrated packaged chip, performing defect identification by using the multi-level identification structure, and determining process defect information includes:
extracting identification window parameters of a detection target according to calibration information of the detection positioning features, and setting an identification threshold value based on the identification window parameters;
and determining an execution processing layer of the multi-level identification structure according to the identification threshold, identifying a defect identification area through the execution processing layer according to calibration, and carrying out defect identification to obtain the process defect information.
The method for determining the process defect information by detecting the image through the calibrated packaged chip and carrying out defect identification through a multi-level identification structure comprises the following steps of: the calibrated package chip detection image is image data which is obtained by correcting and standardizing the package chip detection image through an image calibration technology and improves the image quality and analysis accuracy; the calibration information of the detection positioning features refers to the calibration information of each detection positioning feature, which is determined through image binarization and feature analysis, and comprises the shape, the size, the position and the like; the recognition window parameters are window parameters for defect recognition of each level in a multi-level recognition structure, and the window parameters comprise window size, threshold value and the like; the recognition threshold is a group of thresholds used for determining whether the defect exists in the defect recognition process, and the image can be subjected to binarization processing according to the group of thresholds so as to determine whether the defect exists; the execution processing layer is a specific execution processing layer determined according to the identification threshold in the multi-level identification structure and is used for identifying the defect identification area according to calibration and carrying out defect identification; the process defect information refers to defect information in the determined manufacturing process of the packaged chip in the defect identification process, and comprises defect types, positions, sizes and the like.
Based on calibration information of the detection positioning features, extracting corresponding identification window parameters, and setting a proper identification threshold according to the parameters for subsequent defect identification; determining a defect identification area and performing defect identification processing on the calibrated package chip detection image according to a set identification threshold by utilizing an execution processing layer of the multi-level identification structure, so as to obtain accurate process defect information;
through the calibrated package chip detection image, more accurate and reliable detection data can be obtained, and the accuracy and reliability of defect detection are improved; the defect identification is carried out based on the multi-level identification structure, so that the comprehensive, systematic and accurate defect detection and classification of the packaging process to be detected can be realized, and the detection accuracy and efficiency are improved; by setting the parameters of the identification window and the identification threshold, the accuracy and the efficiency of defect identification can be further optimized, and the requirements of different detection targets are met; the processing layer is executed to identify the defect identification area according to calibration, so that the precise positioning and identification of the packaging technology to be detected can be realized, and the accuracy and reliability of detection are improved; and finally, the process defect information is obtained, so that the defect information feedback in the overall packaging chip manufacturing process can be provided, the process optimization and the quality control are guided, and the quality and the reliability of the product are improved.
In summary, the method for rapidly detecting defects in a chip packaging process provided by the embodiment of the application has the following technical effects:
through the multi-level identification structure, the detection area and the identification area can be more accurately determined, and the detection precision is improved;
the multi-level identification structure can be realized by combining the multi-level detection requirements, and the multi-level identification can be carried out on the detection image of the packaged chip, so that the detection efficiency is improved;
the detection area of the detection image of the packaged chip can be rapidly and accurately positioned through the positioning identification module, so that the detection precision is improved;
the process defect information can be more accurately determined through the calibrated detection image of the packaged chip, and the detection precision is improved.
The detection target defect sample of the detection packaging process is collected, so that defect detection is carried out on the detection target defect sample, and a defect detection characteristic sample and corresponding identification window parameters are determined; performing defect identification training based on the defect detection feature sample to obtain detection target defect features and corresponding identification window parameters; and establishing a mapping relation between the defect characteristics of the detection target and the corresponding recognition window parameters, and constructing a training database. Through collecting and detecting a detection target defect sample of a packaging process, performing defect identification training and establishing a mapping relation, constructing a training database, and providing powerful data support for the subsequent construction of a multi-stage detection structure.
Example two
Based on the same inventive concept as the method for rapidly detecting the defects of the chip packaging process in the foregoing embodiments, as shown in fig. 3, an embodiment of the present application provides a system for rapidly detecting the defects of the chip packaging process, where the system includes:
the feature analysis module 100 is used for performing detection target feature analysis on the detection packaging process and determining detection positioning features;
the detection precision analysis module 200 is used for carrying out detection precision analysis on multiple detection targets to obtain a multi-level detection requirement;
the defect feature detection module 300 is configured to build a multi-level identification structure based on the multi-level detection requirement in combination with a detection target defect feature, where the multi-level identification structure includes a multi-level identification window;
the detection image acquisition module 400 is used for acquiring detection images of the packaged chips by using detection equipment to obtain detection images of the packaged chips;
the detection area positioning module 500 is configured to construct a positioning recognition module based on the detection positioning feature, and perform detection area positioning on the detection image of the packaged chip by using the positioning recognition module to determine a recognition positioning area;
the area calibration module 600 is configured to perform area calibration on the detection image of the packaged chip by using the identification positioning area;
The defect recognition module 700 is configured to perform defect recognition through the calibrated detection image of the packaged chip and the multi-level recognition structure, so as to determine process defect information.
Further, the system further comprises:
performing process stage package analysis on the packaging process to be detected to obtain a process packaging product;
acquiring a product image sample based on the process packaging product to obtain image binarization;
and carrying out binary characteristic analysis according to the image binarization to determine the detection positioning characteristic.
Further, the system further comprises:
performing binary numerical distribution feature analysis according to image binarization to determine binary partition features;
collecting the characteristic area of the binary partition to obtain an area difference value;
when the area difference value reaches a preset requirement, determining the partition characteristic with the largest area as the detection positioning characteristic;
when the area difference value does not reach the preset requirement, two adjacent subareas with the largest adjacent area binarization difference degree are determined, and after subarea combination is carried out, the subareas are used as the detection positioning characteristics.
Further, the system further comprises:
acquiring a plurality of detection targets of a multi-detection packaging process;
performing defect detection feature analysis on the plurality of detection targets to determine target detection defects and detection precision requirements;
And classifying according to the detection precision requirements based on target detection defects and the detection precision requirements of multiple detection targets to obtain the multi-stage detection requirements.
Further, the system further comprises:
determining target detection defects and detection precision requirements based on the multi-level detection requirements, and acquiring the detection target defect characteristics and recognition window parameters from a training database according to the target detection defects and detection precision requirements;
performing window parameter fusion optimization analysis according to a plurality of identification window parameters corresponding to the multiple detection targets, and determining multi-level window parameters;
and constructing a multi-level recognition window based on the multi-level window parameters, and constructing the multi-level recognition structure according to the connection of the multi-level recognition window from small to large.
Further, the system further comprises:
according to a plurality of the identification window parameters, sequencing from small to large according to the parameters to obtain a window parameter sequence;
acquiring a minimum recognition window parameter based on the window parameter sequence;
performing iterative decomposition on a second window parameter based on the minimum recognition window parameter, and determining a second window decomposition parameter, wherein the iterative result of the second window decomposition parameter and the minimum recognition window parameter is the same as the second window parameter;
And similarly, completing iterative analysis of all parameters in the window parameter sequence, and constructing the multi-level window parameters.
Further, the system further comprises:
collecting a detection target defect sample of a detection packaging process, carrying out defect detection on the detection target defect sample, and determining a defect detection characteristic sample and corresponding identification window parameters;
performing defect recognition training based on the defect detection feature sample to obtain the detection target defect feature and a corresponding recognition window parameter;
and establishing a mapping relation between the defect characteristics of the detection target and the corresponding recognition window parameters, and constructing the training database.
Further, the system further comprises:
extracting identification window parameters of a detection target according to calibration information of the detection positioning features, and setting an identification threshold value based on the identification window parameters;
and determining an execution processing layer of the multi-level identification structure according to the identification threshold, identifying a defect identification area through the execution processing layer according to calibration, and carrying out defect identification to obtain the process defect information.
Any of the steps of the methods described above may be stored as computer instructions or programs in a non-limiting computer memory and may be called by a non-limiting computer processor to identify any of the methods to implement embodiments of the present application, without unnecessary limitations.
Further, the first or second element may not only represent a sequential relationship, but may also represent a particular concept, and/or may be selected individually or in whole among a plurality of elements. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the present application and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (9)
1. The method for rapidly detecting the defects of the chip packaging process is characterized by comprising the following steps of:
performing detection target feature analysis on a detection packaging process to determine detection positioning features;
performing detection precision analysis on multiple detection targets to obtain a multi-level detection requirement;
constructing a multi-level identification structure based on the multi-level detection requirement and the detection target defect characteristic, wherein the multi-level identification structure comprises a multi-level identification window;
acquiring a detection image of the packaged chip by using detection equipment to obtain a detection image of the packaged chip;
constructing a positioning identification module based on the detection positioning characteristics, positioning a detection area of the detection image of the packaged chip by using the positioning identification module, and determining an identification positioning area;
Performing region calibration on the detection image of the packaged chip by using the identification positioning region;
and carrying out defect identification through the calibrated detection image of the packaged chip and the multi-level identification structure to determine process defect information.
2. The method of claim 1, wherein performing a test target feature analysis on the test encapsulation process to determine a test locating feature comprises:
performing process stage package analysis on the packaging process to be detected to obtain a process packaging product;
acquiring a product image sample based on the process packaging product to obtain image binarization;
and carrying out binary characteristic analysis according to the image binarization to determine the detection positioning characteristic.
3. The method of claim 2, wherein determining the detected locating feature from a binary feature analysis of the image binarization comprises:
performing binary numerical distribution feature analysis according to image binarization to determine binary partition features;
collecting the characteristic area of the binary partition to obtain an area difference value;
when the area difference value reaches a preset requirement, determining the partition characteristic with the largest area as the detection positioning characteristic;
When the area difference value does not reach the preset requirement, two adjacent subareas with the largest adjacent area binarization difference degree are determined, and after subarea combination is carried out, the subareas are used as the detection positioning characteristics.
4. The method of claim 1, wherein the performing the detection accuracy analysis on the multiple detection targets to obtain the multiple-stage detection requirement comprises:
acquiring a plurality of detection targets of a multi-detection packaging process;
performing defect detection feature analysis on the plurality of detection targets to determine target detection defects and detection precision requirements;
and classifying according to the detection precision requirements based on target detection defects and the detection precision requirements of multiple detection targets to obtain the multi-stage detection requirements.
5. The method of claim 4, wherein constructing a multi-level recognition structure based on the multi-level detection requirement in combination with detecting target defect features, wherein the multi-level recognition structure comprises a multi-level recognition window, comprising:
determining target detection defects and detection precision requirements based on the multi-level detection requirements, and acquiring the detection target defect characteristics and recognition window parameters from a training database according to the target detection defects and detection precision requirements;
Performing window parameter fusion optimization analysis according to a plurality of identification window parameters corresponding to the multiple detection targets, and determining multi-level window parameters;
and constructing a multi-level recognition window based on the multi-level window parameters, and constructing the multi-level recognition structure according to the connection of the multi-level recognition window from small to large.
6. The method of claim 5, wherein performing a window parameter fusion optimization analysis based on a plurality of the identified window parameters corresponding to the plurality of detection targets, determining a multi-level window parameter, comprises:
according to a plurality of the identification window parameters, sequencing from small to large according to the parameters to obtain a window parameter sequence;
acquiring a minimum recognition window parameter based on the window parameter sequence;
performing iterative decomposition on a second window parameter based on the minimum recognition window parameter, and determining a second window decomposition parameter, wherein the iterative result of the second window decomposition parameter and the minimum recognition window parameter is the same as the second window parameter;
and similarly, completing iterative analysis of all parameters in the window parameter sequence, and constructing the multi-level window parameters.
7. The method of claim 6, wherein the retrieving the inspection target defect signature and the recognition window parameters from the training database comprises, before:
Collecting a detection target defect sample of a detection packaging process, carrying out defect detection on the detection target defect sample, and determining a defect detection characteristic sample and corresponding identification window parameters;
performing defect recognition training based on the defect detection feature sample to obtain the detection target defect feature and a corresponding recognition window parameter;
and establishing a mapping relation between the defect characteristics of the detection target and the corresponding recognition window parameters, and constructing the training database.
8. The method of claim 1, wherein said determining process defect information by said calibrated said packaged chip inspection image via said multi-level recognition structure comprises:
extracting identification window parameters of a detection target according to calibration information of the detection positioning features, and setting an identification threshold value based on the identification window parameters;
and determining an execution processing layer of the multi-level identification structure according to the identification threshold, identifying a defect identification area through the execution processing layer according to calibration, and carrying out defect identification to obtain the process defect information.
9. A rapid detection system for defects in a chip packaging process, which is used for implementing a rapid detection method for defects in a chip packaging process according to any one of claims 1 to 8, comprising:
The feature analysis module is used for carrying out detection target feature analysis on the detection packaging process and determining detection positioning features;
the detection precision analysis module is used for carrying out detection precision analysis on multiple detection targets to obtain multi-level detection requirements;
the defect feature detection module is used for constructing a multi-level identification structure based on the multi-level detection requirements and combining detection target defect features, wherein the multi-level identification structure comprises a multi-level identification window;
the detection image acquisition module is used for acquiring detection images of the packaged chips by using detection equipment to obtain detection images of the packaged chips;
the detection area positioning module is used for constructing a positioning identification module based on the detection positioning characteristics, positioning the detection area of the detection image of the packaged chip by using the positioning identification module, and determining an identification positioning area;
the area calibration module is used for carrying out area calibration on the detection image of the packaged chip by utilizing the identification positioning area;
and the defect identification module is used for carrying out defect identification through the calibrated packaging chip detection image and the multi-level identification structure to determine process defect information.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070288219A1 (en) * | 2005-11-18 | 2007-12-13 | Khurram Zafar | Methods and systems for utilizing design data in combination with inspection data |
| US7739065B1 (en) * | 2007-06-12 | 2010-06-15 | Pdf Solutions, Incorporated | Inspection plan optimization based on layout attributes and process variance |
| CN110555839A (en) * | 2019-09-06 | 2019-12-10 | 腾讯云计算（北京）有限责任公司 | Defect detection and identification method and device, computer equipment and storage medium |
| CN110927184A (en) * | 2019-11-15 | 2020-03-27 | 扬州迪飞特测控设备有限公司 | Visual detection method for chip packaging defects |
| CN112330591A (en) * | 2020-09-30 | 2021-02-05 | 中国铁道科学研究院集团有限公司 | Steel rail surface defect detection method and device capable of achieving sample-less learning |
| CN116563641A (en) * | 2023-05-30 | 2023-08-08 | 江西软件职业技术大学 | Surface defect identification method and system based on small target detection |
-
2023
- 2023-11-13 CN CN202311501071.5A patent/CN117274239B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070288219A1 (en) * | 2005-11-18 | 2007-12-13 | Khurram Zafar | Methods and systems for utilizing design data in combination with inspection data |
| US7739065B1 (en) * | 2007-06-12 | 2010-06-15 | Pdf Solutions, Incorporated | Inspection plan optimization based on layout attributes and process variance |
| CN110555839A (en) * | 2019-09-06 | 2019-12-10 | 腾讯云计算（北京）有限责任公司 | Defect detection and identification method and device, computer equipment and storage medium |
| CN110927184A (en) * | 2019-11-15 | 2020-03-27 | 扬州迪飞特测控设备有限公司 | Visual detection method for chip packaging defects |
| CN112330591A (en) * | 2020-09-30 | 2021-02-05 | 中国铁道科学研究院集团有限公司 | Steel rail surface defect detection method and device capable of achieving sample-less learning |
| CN116563641A (en) * | 2023-05-30 | 2023-08-08 | 江西软件职业技术大学 | Surface defect identification method and system based on small target detection |
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