CN117271419A - I2C communication control device and method suitable for RISC-V architecture - Google Patents
I2C communication control device and method suitable for RISC-V architecture Download PDFInfo
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- CN117271419A CN117271419A CN202311340876.6A CN202311340876A CN117271419A CN 117271419 A CN117271419 A CN 117271419A CN 202311340876 A CN202311340876 A CN 202311340876A CN 117271419 A CN117271419 A CN 117271419A
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- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000000872 buffer Substances 0.000 claims abstract description 12
- 230000005540 biological transmission Effects 0.000 claims description 8
- 230000003139 buffering effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
Abstract
The invention discloses an I2C communication control device and method suitable for RISC-V architecture, belonging to the technical field of communication, and solving the technical problem of how to improve the I2C communication rate. The device comprises a bus state register fifo_latch, a data transceiving buffer register tx_rd_data and a slave address register i2c_addr, wherein the fifo_latch is used for storing a receiving and sending flag and a bus restarting flag, the tx_rd_data is used for providing data receiving and sending buffer memory, and the i2c_addr is used for storing a slave address for placing the I2C communication.
Description
Technical Field
The invention relates to the technical field of communication, in particular to an I2C communication control device and method suitable for RISC-V architecture.
Background
The I2C bus hardware is simple in design, has extremely low power consumption and high anti-interference capability, can realize multiple masters and multiple slaves, and is widely used in circuit design.
The I2C is a half duplex communication scheme, and the data transmission and reception of the existing I2C controller share the same 16-bit data buffer tx_rd_data. The 16 bits all play a role in data receiving, but only the lower 8 bits, namely tx_rd_data [7:0], are used in data sending, tx_rd_data [8] are used for representing a receiving and sending mark, tx_rd_data [9] are used for representing a bus restarting mark, the transmission rate of I2C is greatly influenced, and particularly when the peripheral equipment with larger communication data volume such as a liquid crystal screen is faced, the communication rate is more important.
How to increase the I2C communication rate is a technical problem to be solved.
Disclosure of Invention
The technical task of the invention is to provide an I2C communication control device and method suitable for RISC-V architecture to solve the technical problem of how to improve the I2C communication rate.
In a first aspect, the present invention provides an I2C communication control device adapted to a RISC-V architecture, including a bus status register fifo_latch, a data transmit/receive buffer register tx_rd_data, and a slave address register i2c_addr, where fifo_latch is used for storing a receive and transmit flag and a bus restart flag, tx_rd_data is used for providing a data receive and transmit buffer, and i2c_addr is used for storing a slave address for placing the present I2C communication.
Preferably, fifo_latch [0] is used to represent a receive transmit flag, fifo_latch [1] is used to represent a bus restart flag, tx_rd_data [15:0] is used for data receive and transmit buffering, and i2c_addr [9:0] is used to store the slave address where the present I2C communication is placed.
Preferably, when the MCU transmits data to the I2C module, the device is configured to perform the following:
the MCU writes the target slave address into the i2c_addr, writes a bus restart mark into the fifo_latch [1], and writes a bus send mark into the fifo_latch [0 ];
the I2CM module will pull the bus low after reading the above registers and generate a start bit to send the slave address, and after receiving the response from the slave, send the following data through the bus in turn.
Preferably, when the MCU receives data from the I2C module, the device is configured to perform the following:
the MCU writes the target slave address into the i2c_addr register, writes a bus restart flag into the fifo_latch [1], and writes a bus receive flag into the fifo_latch [0 ];
the I2CM module will pull the bus low after reading the above registers and generate a start bit that will be sent from the slave address.
In a second aspect, the present invention provides an I2C communication control method suitable for a RISC-V architecture, which is applied to an I2C communication control device suitable for a RISC-V architecture as described in any one of the first aspects, wherein when a MUC and an I2C module perform data transmission, a receiving and transmitting flag and a bus restart flag are stored through fifo_latch, data receiving and transmitting cache is provided through tx_rd_data, and a slave address for placing the current I2C communication is stored through i2c_addr.
Preferably, the receiving and transmitting flag is represented by fifo_latch [0], the bus restarting flag is represented by fifo_latch [1], the data receiving and transmitting buffer is represented by tx_rd_data [15:0], and the slave address for the current I2C communication is stored by i2c_addr [9:0 ].
Preferably, when the MCU transmits data to the I2C module, the following operations are performed:
the MCU writes the target slave address into the i2c_addr, writes a bus restart mark into the fifo_latch [1], and writes a bus send mark into the fifo_latch [0 ];
the I2CM module will pull the bus low after reading the above registers and generate a start bit to send the slave address, and after receiving the response from the slave, send the following data through the bus in turn.
Preferably, when the MCU receives data from the I2C module, the following operations are performed:
the MCU writes the target slave address into the i2c_addr register, writes a bus restart flag into the fifo_latch [1], and writes a bus receive flag into the fifo_latch [0 ];
the I2CM module will pull the bus low after reading the above registers and generate a start bit that will be sent from the slave address.
The I2C communication control device and method suitable for RISC-V architecture of the invention has the following advantages: the complexity of the state machine of the I2C controller can be greatly reduced by adding a special bus state register fifo_latch, the writing difficulty of SOC application codes is reduced, and the data transmission rate is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a diagram of a prior art scheme tx_rd_data register information storage format;
FIG. 2 is a diagram showing the information storage format of the tx_rd_data register in an I2C communication control device applicable to RISC-V architecture according to embodiment 1;
FIG. 3 is a diagram showing a fifo_latch register information storage format in an I2C communication control device adapted to RISC-V architecture according to embodiment 1;
FIG. 4 is a flow chart showing the fifo_latch register operation in an I2C communication control device suitable for RISC-V architecture according to embodiment 1.
Detailed Description
The invention will be further described with reference to the accompanying drawings and specific examples, so that those skilled in the art can better understand the invention and implement it, but the examples are not meant to limit the invention, and the technical features of the embodiments of the invention and the examples can be combined with each other without conflict.
The embodiment of the invention provides an I2C communication control device and method suitable for RISC-V architecture, which are used for solving the technical problem of how to improve the I2C communication rate.
Example 1:
the invention relates to an I2C communication control device suitable for RISC-V architecture, which comprises a bus state register fifo_latch, a data receiving and transmitting buffer register tx_rd_data and a slave address register i2c_addr, wherein fifo_latch is used for storing a receiving and transmitting mark and a bus restarting mark, tx_rd_data is used for providing data receiving and transmitting buffer memory, and i2c_addr is used for storing a slave address for placing the I2C communication.
Wherein fifo_latch [0] is used for representing a receiving and transmitting flag, fifo_latch [1] is used for representing a bus restarting flag, tx_rd_data [15:0] is used for data receiving and transmitting buffering, and i2c_addr [9:0] is used for storing the slave address for placing the present I2C communication.
In this embodiment, a dedicated bus state register fifo_latch is newly added, so that the complexity of the state machine of the I2C controller can be greatly reduced, the writing difficulty of SOC application codes is reduced, the data sending rate is greatly improved, and the workflow of the fifo_latch register is shown in fig. 3.
When the MCU sends data to the I2C module, the device is used for executing the following steps: the MCU writes the target slave address into the i2c_addr, writes a bus restart mark into the fifo_latch [1], and writes a bus send mark into the fifo_latch [0 ]; the I2CM module will pull the bus low after reading the above registers and generate a start bit to send the slave address, and after receiving the response from the slave, send the following data through the bus in turn.
When the MCU receives data from the I2C module, the device is used for executing the following steps: the MCU writes the target slave address into the i2c_addr register, writes a bus restart flag into the fifo_latch [1], and writes a bus receive flag into the fifo_latch [0 ]; the I2CM module will pull the bus low after reading the above registers and generate a start bit that will be sent from the slave address.
Example 2:
the invention discloses an I2C communication control method suitable for RISC-V architecture, which is applied to the device disclosed in the embodiment 1, when MUC and I2C module carry out data transmission, a receiving and transmitting mark and a bus restarting mark are stored through fifo_latch, data receiving and transmitting cache is provided through tx_rd_data, and the slave address of the I2C communication is stored and placed through i2c_addr.
As specific implementation, a receiving and sending flag is represented by fifo_latch [0], a bus restarting flag is represented by fifo_latch [1], data receiving and sending buffering is represented by tx_rd_data [15:0], and a slave address for placing the current I2C communication is stored by i2c_addr [9:0 ].
When the MCU sends data to the I2C module, the following operations are executed: the MCU writes the target slave address into the i2c_addr, writes a bus restart mark into the fifo_latch [1], and writes a bus send mark into the fifo_latch [0 ]; the I2CM module will pull the bus low after reading the above registers and generate a start bit to send the slave address, and after receiving the response from the slave, send the following data through the bus in turn.
When the MCU receives data from the I2C module, the following operations are executed: the MCU writes the target slave address into the i2c_addr register, writes a bus restart flag into the fifo_latch [1], and writes a bus receive flag into the fifo_latch [0 ]; the I2CM module will pull the bus low after reading the above registers and generate a start bit that will be sent from the slave address.
While the invention has been illustrated and described in detail in the drawings and in the preferred embodiments, the invention is not limited to the disclosed embodiments, but it will be apparent to those skilled in the art that many more embodiments of the invention can be made by combining the means of the various embodiments described above and still fall within the scope of the invention.
Claims (8)
1. An I2C communication control device suitable for RISC-V architecture, comprising a bus status register fifo_latch, a data transmit-receive buffer register tx_rd_data, and a slave address register i2c_addr, wherein fifo_latch is used for storing a receive and transmit flag and a bus restart flag, tx_rd_data is used for providing data receive and transmit buffers, and i2c_addr is used for storing a slave address for placing the I2C communication.
2. The I2C communication control device according to claim 1, wherein fifo_latch [0] is used for representing a reception transmission flag, fifo_latch [1] is used for representing a bus restart flag, tx_rd_data [15:0] is used for data reception and transmission buffering, and i2c_addr [9:0] is used for storing a slave address for placing the present I2C communication.
3. The I2C communication control device according to claim 1 or 2, adapted for RISC-V architecture, wherein when the MCU sends data to the I2C module, the device is adapted to perform the following:
the MCU writes the target slave address into the i2c_addr, writes a bus restart mark into the fifo_latch [1], and writes a bus send mark into the fifo_latch [0 ];
the I2CM module will pull the bus low after reading the above registers and generate a start bit to send the slave address, and after receiving the response from the slave, send the following data through the bus in turn.
4. The I2C communication control device according to claim 1 or 2, adapted for RISC-V architecture, wherein when the MCU receives data from the I2C module, the device is adapted to perform the following:
the MCU writes the target slave address into the i2c_addr register, writes a bus restart flag into the fifo_latch [1], and writes a bus receive flag into the fifo_latch [0 ];
the I2CM module will pull the bus low after reading the above registers and generate a start bit that will be sent from the slave address.
5. An I2C communication control method suitable for RISC-V architecture, which is characterized in that it is applied to an I2C communication control device suitable for RISC-V architecture according to any one of claims 1-3, when MUC and I2C module perform data transmission, a receiving and transmitting flag and a bus restarting flag are stored through fifo_latch, data receiving and transmitting buffer is provided through tx_rd_data, and a slave address for placing the present I2C communication is stored through i2c_addr.
6. The method according to claim 5, wherein the received and transmitted flag is indicated by fifo_latch [0], the bus restart flag is indicated by fifo_latch [1], the data receiving and transmitting buffers are indicated by tx_rd_data [15:0], and the slave address for the present I2C communication is stored by i2c_addr [9:0 ].
7. The I2C communication control device according to claim 5 or 6, wherein when the MCU transmits data to the I2C module, the following operations are performed:
the MCU writes the target slave address into the i2c_addr, writes a bus restart mark into the fifo_latch [1], and writes a bus send mark into the fifo_latch [0 ];
the I2CM module will pull the bus low after reading the above registers and generate a start bit to send the slave address, and after receiving the response from the slave, send the following data through the bus in turn.
8. The I2C communication control device according to claim 5 or 6, wherein the MCU performs the following operations when receiving data from the I2C module:
the MCU writes the target slave address into the i2c_addr register, writes a bus restart flag into the fifo_latch [1], and writes a bus receive flag into the fifo_latch [0 ];
the I2CM module will pull the bus low after reading the above registers and generate a start bit that will be sent from the slave address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311340876.6A CN117271419A (en) | 2023-10-17 | 2023-10-17 | I2C communication control device and method suitable for RISC-V architecture |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311340876.6A CN117271419A (en) | 2023-10-17 | 2023-10-17 | I2C communication control device and method suitable for RISC-V architecture |
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| CN117271419A true CN117271419A (en) | 2023-12-22 |
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| CN202311340876.6A Pending CN117271419A (en) | 2023-10-17 | 2023-10-17 | I2C communication control device and method suitable for RISC-V architecture |
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| CN (1) | CN117271419A (en) |
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