CN117271374A - Simulation test method, device and equipment for chip and storage medium - Google Patents
Simulation test method, device and equipment for chip and storage medium Download PDFInfo
- Publication number
- CN117271374A CN117271374A CN202311551546.1A CN202311551546A CN117271374A CN 117271374 A CN117271374 A CN 117271374A CN 202311551546 A CN202311551546 A CN 202311551546A CN 117271374 A CN117271374 A CN 117271374A
- Authority
- CN
- China
- Prior art keywords
- test
- simulation
- code
- chip
- server
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 131
- 238000010998 test method Methods 0.000 title abstract description 5
- 238000012360 testing method Methods 0.000 claims abstract description 204
- 238000000034 method Methods 0.000 claims abstract description 56
- 238000012544 monitoring process Methods 0.000 claims abstract description 16
- 230000007246 mechanism Effects 0.000 claims abstract description 9
- 238000012795 verification Methods 0.000 claims description 22
- 230000008569 process Effects 0.000 abstract description 20
- 230000010354 integration Effects 0.000 description 33
- 230000006870 function Effects 0.000 description 25
- 238000012545 processing Methods 0.000 description 12
- 238000004891 communication Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 238000011161 development Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 230000006399 behavior Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000005236 sound signal Effects 0.000 description 4
- 230000006978 adaptation Effects 0.000 description 3
- 238000007726 management method Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 244000035744 Hura crepitans Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3624—Software debugging by performing operations on the source code, e.g. via a compiler
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The application provides a simulation test method and device of a chip, electronic equipment and a computer readable storage medium, wherein the simulation test method comprises the following steps: acquiring simulation program codes to be tested and a plurality of different test cases; the simulation program codes are used for representing the running mechanism of the chip, and the test cases are used for representing task parameters required in the chip test; compiling to obtain a plurality of executable test programs according to the simulation program codes and a plurality of test cases; distributing the test programs to a simulation server, performing parallel simulation operation on all the test programs, and monitoring the operation state of the simulation server on the test programs; in case the running state of all test programs is successful, the simulation program code is submitted. The simulation test of the simulation program codes of the chip can be realized by an automatic process, so that the dependence on manpower can be greatly reduced, and the manpower cost is saved.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method and apparatus for testing a chip, an electronic device, and a computer readable storage medium.
Background
When designing a chip using hardware description language (Verilog HDL, verilog Hardware Description Language), it is necessary to test the performance of the circuits of the chip.
At present, a developer submits simulation program codes written in the chip development process, a verifier performs simulation verification on the simulation program codes, and after the simulation verification is passed, the simulation program codes can be merged into a code warehouse.
However, in the whole simulation test process, a verifier is required to pay attention to the simulation process at any time and operate the simulation verification, so that the labor cost is high.
Disclosure of Invention
The embodiment of the application provides a simulation test method and device for a chip, electronic equipment and a computer readable storage medium, so as to solve the problems in the related art.
In a first aspect, an embodiment of the present application provides a method for performing a simulation test on a chip, where the method includes:
acquiring simulation program codes to be tested and a plurality of different test cases; the simulation program code is used for representing the running mechanism of the chip, and the test case is used for representing task parameters required in the chip test;
compiling to obtain a plurality of executable test programs according to the simulation program codes and a plurality of test cases;
distributing the test programs to a simulation server, performing parallel simulation operation on all the test programs, and monitoring the operation state of the simulation server on the test programs;
and submitting the simulation program codes under the condition that the running states of all the test programs are successful.
In a second aspect, an embodiment of the present application provides a simulation test apparatus for a chip, where the apparatus includes:
the acquisition module is used for acquiring simulation program codes to be tested and a plurality of different test cases; the simulation program code is used for representing the running mechanism of the chip, and the test case is used for representing task parameters required in the chip test;
the compiling module is used for compiling and obtaining a plurality of executable test programs according to the simulation program codes and a plurality of test cases;
the distribution module is used for distributing the test programs to a simulation server, carrying out parallel simulation operation on all the test programs, and monitoring the operation state of the simulation server on the test programs;
and the submitting module is used for submitting the simulation program codes under the condition that the running states of all the test programs are successful.
In a third aspect, embodiments of the present application further provide an electronic device, including a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the method of the first aspect.
In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform the method of the first aspect.
In the embodiment of the application, the simulation program codes can be acquired, and the simulation program codes and a plurality of test cases are compiled automatically to obtain a plurality of executable test programs, so that the test programs are distributed to the simulation server automatically to perform parallel simulation operation, the state of the simulation operation can be monitored in time, and the simulation program codes are submitted to realize code integration under the condition that the operation states of all the test programs are successful. According to the embodiment of the application, the simulation test of the simulation program codes of the chip can be realized by an automatic process, wherein the code acquisition, the code compiling, the test program distribution and operation, the operation state monitoring and the code integration after the test pass are all completed by the automatic process, so that the dependence on manpower can be greatly reduced, and the labor cost is saved.
The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of an implementation scenario provided in an embodiment of the present application;
FIG. 2 is a flow chart of steps of a method for simulating and testing a chip according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating specific steps of a method for testing a chip according to an embodiment of the present disclosure;
FIG. 4 is a block diagram of a simulation test apparatus for a chip according to an embodiment of the present application;
FIG. 5 is a block diagram of an electronic device provided by an embodiment of the present invention;
fig. 6 is a block diagram of another electronic device in accordance with another embodiment of the invention.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in the embodiments of the present application means two or more, and other adjectives are similar thereto.
Referring to fig. 1, fig. 1 is an implementation scenario structure diagram provided in an embodiment of the present application, including: code warehouse, integrated server, compiling server and emulation server.
Where Code Repository (Code Repository) refers to a centralized or distributed system for managing and storing source Code, it typically includes version control tools, collaboration tools, build tools, and the like.
The integration server is used for realizing the purpose of continuous integration in the process of developing projects, so that the project products can be iterated quickly, and meanwhile, the high quality can be maintained. The core measure of the integrated server is that before the code is integrated to the trunk, the code is automatically tested, the integration can not be realized as long as one test case fails, and when all the test cases succeed, the integration is realized.
The compiling server is used for compiling the source code into an executable program through a compiling function, and particularly in a code testing scene, the test case required by the test and the tested code can be compiled in a combined way to obtain the executable test program.
The simulation server is used for providing a simulation running environment, running of the chip circuit can be simulated by running the compiled test program in the simulation server, and the running result reflects the test condition of the chip circuit.
Specifically, the developer can upload the simulation program code developed for the chip to the code warehouse, and after the integration server monitors the uploading operation, the simulation program code can be immediately downloaded from the code warehouse, and the simulation program code is sent to the compiling server. The compiling server respectively compiles the test cases and the simulation program codes required by the test to obtain a plurality of executable test programs, sends the test programs to each simulation server for parallel operation, and the integration server can monitor the operation condition of the simulation server and submits the simulation program codes to a code warehouse to realize integration under the condition that the operation states of all the test programs are successful; if the running state of the test program is failed, notifying a developer and a verifier, realizing timely notification of defects of the simulation program code, and promoting timely correction of the defects of the simulation program code.
It should be noted that the integration server, the compiling server and the simulation server may be independent servers, or may be integrated together into the same server.
In the embodiment of the application, the simulation program codes uploaded by the developer can be acquired, and the simulation program codes and a plurality of test cases are compiled automatically to obtain a plurality of executable test programs, so that the test programs are distributed to the simulation server automatically to perform parallel simulation operation, the state of the simulation operation can be monitored in time, and the simulation program codes are submitted to realize code integration under the condition that the operation states of all the test programs are successful. According to the embodiment of the application, the simulation test of the simulation program codes of the chip can be realized by an automatic process, wherein the code acquisition, the code compiling, the test program distribution and operation, the operation state monitoring and the code integration after the test pass are all completed by the automatic process, so that the dependence on manpower can be greatly reduced, and the labor cost is saved.
Fig. 2 is a flowchart of steps of a method for testing a chip according to an embodiment of the present application, where, as shown in fig. 2, the method may include:
step 101, obtaining simulation program codes to be tested and a plurality of different test cases; the simulation program code is used for representing the running mechanism of the chip, and the test case is used for representing task parameters required in the chip test.
In the embodiment of the application, the simulation program code is a file produced in the chip development process, and can describe the structure and the behavior of the designed chip circuit and characterize the operation mechanism of the chip. The test cases are cases obtained by describing test tasks of a circuit of a designed chip, and since a plurality of different test tasks are often tested, the number of test cases is usually plural. This step may be implemented by the integration server in fig. 1.
For example, in the case where the simulation program code is a program code developed for a processor chip, the test scenario needs to test each different function of the processor, where each test case corresponds to a function, so that the test case can describe the tested function, and if the processor needs to test a clock function and an interface function, the test case corresponding to the clock function describes parameters required for the clock test, and the test case corresponding to the interface function describes parameters required for the interface test.
And 102, compiling to obtain a plurality of executable test programs according to the simulation program codes and a plurality of test cases.
In the embodiment of the present application, code compiling refers to a process of translating source program code written in a high-level programming language into an equivalent machine language format target program, and the code can be run on a computer only after being compiled into the program by a compiler.
Specifically, in this step, the obtained simulation program code and the plurality of test cases need to be compiled into a computer executable program, so after the integration server in fig. 1 obtains the simulation program code and the plurality of test cases, the simulation program code and the plurality of test cases may be sent to the compiling server to be compiled, so as to obtain a plurality of executable test programs.
Specifically, the compiling server may compile each test case and the simulation program code in a combined manner, so as to obtain executable test programs corresponding to the test cases, that is, the number of the test programs is the same as the number of the test cases, and the test programs are in one-to-one correspondence with the test cases.
And step 103, distributing the test programs to a simulation server, performing parallel simulation operation on all the test programs, and monitoring the operation state of the simulation server on the test programs.
In this embodiment of the present application, after the compiling server in fig. 1 compiles and obtains the test program, the test program may be distributed to the simulation server for operation, where the simulation server provides a simulation operation environment, and all the test programs may be operated in parallel through the simulation server, and at the same time, the integration server may monitor the operation state of the simulation server on the test program, where the operation state includes success and failure of operation.
Step 104, submitting the simulation program codes under the condition that the running states of all the test programs are successful.
In the embodiment of the present application, the running time of different test programs is different, but because the integration server of fig. 1 monitors the simulation server, the integration server can obtain the running states of all the test programs, and in order to meet the stability and correctness of the code integration process, in the embodiment of the present application, the simulation program code needs to be submitted to the code warehouse when the integration server monitors that the running states of all the test programs are successful, so that all the chip functions in the simulation program code can be guaranteed to run normally, and the code integration will not affect the main branch code of the project.
If the test program with the failed running state exists, the simulation program code is also proved to have the defect of certain chip functions, and in order to meet the stability and the correctness of the code integration process, developers and verifiers are required to be notified to improve the simulation program code in time.
In summary, in the embodiment of the present application, a simulation program code may be obtained, and the simulation program code and a plurality of test cases may be compiled automatically to obtain a plurality of executable test programs, so that the test programs may be distributed to a simulation server automatically to perform parallel simulation operation, the state of the simulation operation may be monitored in time, and under the condition that the operation states of all the test programs are successful, the simulation program code may be submitted to implement code integration. According to the embodiment of the application, the simulation test of the simulation program codes of the chip can be realized by an automatic process, wherein the code acquisition, the code compiling, the test program distribution and operation, the operation state monitoring and the code integration after the test pass are all completed by the automatic process, so that the dependence on manpower can be greatly reduced, and the labor cost is saved.
Fig. 3 is a flowchart of specific steps of a method for testing a chip according to an embodiment of the present application, where, as shown in fig. 3, the method may include:
step 201, monitoring a code warehouse; the code repository is used to store uploaded codes.
In the embodiment of the application, the code warehouse refers to a centralized or distributed system for managing and storing source codes, the code warehouse can store code files of various development projects, and for each development project, the code warehouse stores corresponding main branch codes, and codes newly added in the development project can be combined into the main branch codes, so that code integration is realized.
Specifically, the integrated server in fig. 1 may monitor the code repository, specifically monitor the behavior generated by the code repository, such as uploading, deleting, replacing, and the like.
And 202, acquiring the simulation program code from the code warehouse when the simulation program code to be tested is uploaded to the code warehouse.
In this embodiment of the present application, since the integrated server in fig. 1 monitors the behavior of the code repository, when the developer uploads the simulation program code to be tested to the code repository, the integrated server may immediately monitor the uploading behavior and acquire the simulation program code uploaded by the developer from the code repository.
And 203, compiling each test case and the simulation program code in a combined way to obtain a test program corresponding to each test case.
In the embodiment of the application, the simulation program code is a program code developed for a circuit of the chip, a test scene of the simulation program code needs to test different functions of the chip, each test case corresponds to one function, so that the test case can describe the tested function, a plurality of test programs need to be built, and each test program can realize the test of the corresponding one chip function. The integration server of fig. 1 may send the simulation program code to a compiling server, and the compiling server may respectively combine and compile the test cases and the simulation program code required for the test, to obtain a plurality of executable test programs.
For example, assuming that the simulation program code is a program code developed for a circuit of a processor, the processor needs to test a clock function and an interface function, a test case corresponding to the clock function describes parameters required for clock testing, and a test case corresponding to the interface function describes parameters required for interface testing. When the compiling server compiles, the simulation program codes and the test cases corresponding to the clock functions can be combined and compiled to obtain a test program for testing the clock functions; in addition, the compiling server can also compile the simulation program code and the test cases corresponding to the interface functions in a combined way to obtain the test program for testing the interface functions.
And 204, distributing the test programs to a simulation server, performing parallel simulation operation on all the test programs, and monitoring the operation state of the simulation server on the test programs.
This step may refer to step 103, and will not be described herein.
Optionally, step 204 may specifically include sub-steps 2041-2042:
and 2041, obtaining a current load value of each simulation server.
Sub-step 2042, distributing the test program to the simulation server according to a load balancing strategy according to the current load value of the simulation server.
In the embodiment of the present application, for sub-steps 2041-2042, in the scenario shown in fig. 1, the simulation server is configured to provide a simulation running environment, and by running the compiled test program in the simulation server, the running of the chip circuit can be simulated, and the running result reflects the test condition of the chip circuit. The number of simulation servers may be 1 or more. Under the condition that 1 simulation server is adopted, the compiling server can distribute all the compiled test programs to the simulation server, the simulation server can construct parallel threads, and parallel simulation operation is carried out on all the test programs.
Under the condition that the number of the simulation servers is multiple, the current load values of different simulation servers may be different, in order to meet the stability of parallel simulation operation of all the test programs, the embodiment of the application can obtain the current load value of each simulation server and the required resource quantity of each test program, according to the total resource quantity and the current load value of the simulation servers, the residual resource quantity of the simulation servers can be obtained, and then according to the residual resource quantity of the simulation servers and the required resource quantity of each test program, the test programs are distributed to the simulation servers according to a load balancing strategy, so that stable and efficient parallel simulation operation of all the test programs can be realized, the occurrence probability of the phenomenon that a certain simulation server is overloaded to cause the test program to be blocked is reduced, and the occurrence probability of idle waste phenomenon caused by no test program operation of a certain simulation server is reduced.
It should be noted that, in the embodiment of the present application, under the condition that the number of simulation servers is sufficient, a corresponding simulation server may be allocated to each test program, so that stable and efficient parallel simulation operation of all the test programs may be implemented.
Optionally, the test program runs in a virtualized container built in the emulation server.
The simulation server is used for providing a simulation running environment, specifically, a virtualized container can be built in the simulation server, and each test program can run in the corresponding virtualized container, so that each test program has an independent running environment, the simulation running of the test programs can not interfere with each other, and the stability of the test process is improved.
For example, the virtualization container may be a dock container, where a dock is an open-source application container engine, so that the developer may package their application programs and rely on packages to a portable container, and then issue them to any operating system computer, where the dock may implement virtualization, where the dock completely uses a sandbox mechanism, and runs independently of each other, without any interface between each other.
In the related art, the simulation verification environment for each test program needs to be built independently, and the operations of interface adaptation and authority grant are involved, which makes the building of the simulation verification environment in the simulation server time-consuming and laborious. By the embodiment of the application, a plurality of dock containers can be quickly built through a virtualization mirroring technology, interface adaptation and authority grant operation of each simulation verification environment are omitted, and building efficiency of the simulation verification environments is improved.
Step 205, uploading the simulation program code to the code warehouse for the code warehouse to merge the simulation program code into the main branch code of the project if all the running states of the test program are successful.
In the embodiment of the application, a developer can continuously develop new functions aiming at a development project, simulation program codes of each new function can be uploaded for simulation verification, and the simulation program codes are submitted to a code warehouse under the condition that the running states of all test programs constructed based on the simulation program codes are successful, so that the code warehouse can combine the simulation program codes into main branch codes of the development project, and therefore normal running of all sub functions in the simulation program codes can be ensured, and the main branch codes of the project cannot be influenced after code integration.
Optionally, the method further comprises:
and step 206, in the case of the failure of compiling the test program, sending compiling failure notification information to a verification device and/or an uploading device of the simulation program code.
In the embodiment of the application, in the case that the compiling of the test program fails, the compiling server may send compiling failure notification information to the verification device and/or the uploading device of the simulation program code. Therefore, a developer or a verifier can be timely informed of the occurrence of the compiling defect, and the improvement of the compiling defect is promoted. The notification mode can comprise mail, short message, telephone notification and the like.
Optionally, the method further comprises:
step 207, obtaining an error log sent by the simulation server and a test code with operation failure when the running state of the test program is failure;
step 208, transmitting the error log and the test code to a verification device and/or an uploading device of the simulation program code.
In the embodiment of the application, when the integrated server monitors that the running state of the simulation server on the test program is failed, the integrated server may send an error log and a test code with the failed running state to the verification device and/or the uploading device of the simulation program code. In this way, the developer or the verifier can be timely informed of the occurrence of the simulation program code defect, and an error log for checking errors and test codes for running failure are provided to promote improvement of the simulation program code defect. The notification mode can comprise mail, short message, telephone notification and the like.
Optionally, the method further comprises:
step 209, sending operation timeout notification information to the verification device when the operation duration of the simulation server on the test program exceeds a preset duration threshold.
In the embodiment of the application, when the integrated server monitors that the running time of the simulation server on the test program exceeds the preset time threshold, the integrated server can consider that the simulation running fault exists currently, and the integrated server can send running overtime notification information to the verification device so as to enable verification personnel to check the overtime fault reason. The notification mode can comprise mail, short message, telephone notification and the like.
It should be noted that, under the condition of overtime simulation running, the integration flow of the integration server is not ended, waiting for the intervention check of a verification personnel, if the code problem is detected, stopping the integration flow, notifying a developer of modification, and if the code problem is not detected, continuing the simulation test.
In summary, in the embodiment of the present application, the simulation program code may be obtained, and the simulation program code and the multiple test cases may be compiled automatically to obtain multiple executable test programs, so that the test programs may be distributed to the simulation server automatically to perform parallel simulation operation, the state of the simulation operation may be monitored in time, and the simulation program code may be submitted to implement code integration under the condition that the running states of all the test programs are successful. According to the embodiment of the application, the simulation test of the simulation program codes of the chip can be realized by an automatic process, wherein the code acquisition, the code compiling, the test program distribution and operation, the operation state monitoring and the code integration after the test pass are all completed by the automatic process, so that the dependence on manpower can be greatly reduced, and the labor cost is saved.
Fig. 4 is a block diagram of a simulation test apparatus for a chip according to an embodiment of the present application, where the apparatus includes:
the acquiring module 301 is configured to acquire a simulation program code to be tested and a plurality of different test cases; the simulation program code is used for representing the running mechanism of the chip, and the test case is used for representing task parameters required in the chip test;
a compiling module 302, configured to compile a plurality of executable test programs according to the simulation program code and a plurality of the test cases;
the distribution module 303 is configured to distribute the test program to a simulation server, perform parallel simulation operation on all the test programs, and monitor an operation state of the simulation server on the test programs;
and the submitting module 304 is configured to submit the simulation program code if all running states of the test program are successful.
Optionally, the acquiring module 301 includes:
the monitoring submodule is used for monitoring the code warehouse; the code warehouse is used for storing uploaded codes;
and the downloading sub-module is used for acquiring the simulation program code from the code warehouse when the code warehouse is monitored to upload the simulation program code to be tested.
Optionally, the submitting module 304 includes:
and the submitting submodule is used for uploading the simulation program codes to the code warehouse so that the code warehouse can merge the simulation program codes into main branch codes of projects under the condition that the running states of all the test programs are successful.
Optionally, the compiling module 302 includes:
and the compiling sub-module is used for carrying out combined compiling on each test case and the simulation program code to obtain a test program corresponding to each test case.
Optionally, the apparatus further includes:
and the first notification module is used for sending compiling failure notification information to the verification device and/or the uploading device of the simulation program code under the condition that the compiling of the test program fails.
Optionally, the apparatus further includes:
the error acquisition module is used for acquiring an error log sent by the simulation server and a test code with operation failure under the condition that the running state of the test program is failure;
and the second notification module is used for sending the error log and the test code to verification equipment and/or uploading equipment of the simulation program code.
Optionally, the apparatus further includes:
and the third notification module is used for sending the operation timeout notification information to the verification device under the condition that the operation duration of the simulation server to the test program exceeds a preset duration threshold value.
Optionally, the allocation module 303 includes:
the load acquisition sub-module is used for acquiring the current load value of each simulation server;
and the load balancing sub-module is used for distributing the test program to the simulation server according to the current load value of the simulation server and the load balancing strategy.
Optionally, the test program runs in a virtualized container built in the emulation server.
In summary, in the embodiment of the present application, a simulation program code may be obtained, and the simulation program code and a plurality of test cases may be compiled automatically to obtain a plurality of executable test programs, so that the test programs may be distributed to a simulation server automatically to perform parallel simulation operation, the state of the simulation operation may be monitored in time, and under the condition that the operation states of all the test programs are successful, the simulation program code may be submitted to implement code integration. According to the embodiment of the application, the simulation test of the simulation program codes of the chip can be realized by an automatic process, wherein the code acquisition, the code compiling, the test program distribution and operation, the operation state monitoring and the code integration after the test pass are all completed by the automatic process, so that the dependence on manpower can be greatly reduced, and the labor cost is saved.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.
The embodiment of the application provides a simulation test device of a chip, which comprises a memory and more than one program, wherein the more than one program is stored in the memory, and the more than one program is configured to be executed by more than one processor, and the method for performing one or more embodiments is included.
Fig. 5 is a block diagram of an electronic device 600, according to an example embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.
Referring to fig. 5, the electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power component 606, a multimedia component 608, an audio component 610, an input/output (I/O) interface 612, a sensor component 614, and a communication component 616.
The processing component 602 generally controls overall operation of the electronic device 600, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 602 can include one or more modules that facilitate interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate interaction between the multimedia component 608 and the processing component 602.
The memory 604 is used to store various types of data to support operations at the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phonebook data, messages, pictures, multimedia, and so forth. The memory 604 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.
The power supply component 606 provides power to the various components of the electronic device 600. The power supply components 606 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.
The multimedia component 608 includes a screen between the electronic device 600 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense demarcations of touch or sliding actions, but also detect durations and pressures associated with the touch or sliding operations. In some embodiments, the multimedia component 608 includes a front camera and/or a rear camera. When the electronic device 600 is in an operational mode, such as a shooting mode or a multimedia mode, the front-facing camera and/or the rear-facing camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
The audio component 610 is for outputting and/or inputting audio signals. For example, the audio component 610 includes a Microphone (MIC) for receiving external audio signals when the electronic device 600 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, audio component 610 further includes a speaker for outputting audio signals.
The I/O interface 612 provides an interface between the processing component 602 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.
The sensor assembly 614 includes one or more sensors for providing status assessment of various aspects of the electronic device 600. For example, the sensor assembly 614 may detect an on/off state of the electronic device 600, a relative positioning of the components, such as a display and keypad of the electronic device 600, the sensor assembly 614 may also detect a change in position of the electronic device 600 or a component of the electronic device 600, the presence or absence of a user's contact with the electronic device 600, an orientation or acceleration/deceleration of the electronic device 600, and a change in temperature of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 616 is utilized to facilitate communication between the electronic device 600 and other devices, either in a wired or wireless manner. The electronic device 600 may access a wireless network based on a communication standard, such as WiFi, an operator network (e.g., 2G, 3G, 4G, or 5G), or a combination thereof. In one exemplary embodiment, the communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 616 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the electronic device 600 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for implementing the methods provided by the embodiments of the present application.
In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as memory 604, including instructions executable by processor 620 of electronic device 600 to perform the above-described method. For example, the non-transitory storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
Fig. 6 is a block diagram of an electronic device 700, according to an example embodiment. For example, the electronic device 700 may be provided as a server. Referring to fig. 6, electronic device 700 includes a processing component 722 that further includes one or more processors and memory resources represented by memory 732 for storing instructions, such as application programs, executable by processing component 722. The application programs stored in memory 732 may include one or more modules that each correspond to a set of instructions. Further, the processing component 722 is configured to execute instructions to perform the methods provided by embodiments of the present application.
The electronic device 700 may also include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input output (I/O) interface 758. The electronic device 700 may operate based on an operating system stored in memory 732, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.
Embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, implements the method described in the above embodiments.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (12)
1. A method for simulation testing of a chip, the method comprising:
acquiring simulation program codes to be tested and a plurality of different test cases; the simulation program code is used for representing the running mechanism of the chip, and the test case is used for representing task parameters required in the chip test;
compiling to obtain a plurality of executable test programs according to the simulation program codes and a plurality of test cases;
distributing the test programs to a simulation server, performing parallel simulation operation on all the test programs, and monitoring the operation state of the simulation server on the test programs;
and submitting the simulation program codes under the condition that the running states of all the test programs are successful.
2. The method for simulated testing of a chip according to claim 1, wherein said obtaining simulated program code to be tested comprises:
monitoring a code warehouse; the code warehouse is used for storing uploaded codes;
and acquiring the simulation program code from the code warehouse when the code warehouse is monitored to upload the simulation program code to be tested.
3. The method for simulation test of a chip according to claim 2, wherein said submitting the simulation program code in the case that the running states of all the test programs are successful includes:
and uploading the simulation program code to the code warehouse for the code warehouse to merge the simulation program code into main branch codes of items under the condition that the running states of all the test programs are successful.
4. The method for testing the chip according to claim 1, wherein compiling the plurality of executable test programs according to the simulation program code and the plurality of test cases comprises:
and compiling each test case and the simulation program code in a combined way to obtain a test program corresponding to each test case.
5. The method for simulated testing of a chip according to claim 1 or 4, further comprising:
and under the condition that the compiling of the test program fails, sending compiling failure notification information to a verification device and/or an uploading device of the simulation program code.
6. The method for simulated testing of a chip of claim 1, further comprising:
under the condition that the running state of the test program is failure, acquiring an error log sent by the simulation server and a test code with the failure running;
and transmitting the error log and the test code to a verification device and/or an uploading device of the simulation program code.
7. The method for simulated testing of a chip of claim 1, further comprising:
and under the condition that the running time of the simulation server to the test program exceeds a preset time threshold, sending running timeout notification information to verification equipment.
8. The method for simulation testing of a chip according to claim 1, wherein the distributing the test program to a simulation server comprises:
acquiring a current load value of each simulation server;
and distributing the test program to the simulation server according to a load balancing strategy according to the current load value of the simulation server.
9. The method for simulation testing of a chip according to any one of claims 1 to 8, wherein the test program is run in a virtualized container built in the simulation server.
10. A simulation test apparatus for a chip, the apparatus comprising:
the acquisition module is used for acquiring simulation program codes to be tested and a plurality of different test cases; the simulation program code is used for representing the running mechanism of the chip, and the test case is used for representing task parameters required in the chip test;
the compiling module is used for compiling and obtaining a plurality of executable test programs according to the simulation program codes and a plurality of test cases;
the distribution module is used for distributing the test programs to a simulation server, carrying out parallel simulation operation on all the test programs, and monitoring the operation state of the simulation server on the test programs;
and the submitting module is used for submitting the simulation program codes under the condition that the running states of all the test programs are successful.
11. An electronic device, comprising: a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 9.
12. A computer readable storage medium, characterized in that instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311551546.1A CN117271374A (en) | 2023-11-20 | 2023-11-20 | Simulation test method, device and equipment for chip and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311551546.1A CN117271374A (en) | 2023-11-20 | 2023-11-20 | Simulation test method, device and equipment for chip and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117271374A true CN117271374A (en) | 2023-12-22 |
Family
ID=89216356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311551546.1A Pending CN117271374A (en) | 2023-11-20 | 2023-11-20 | Simulation test method, device and equipment for chip and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117271374A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117743059A (en) * | 2024-02-18 | 2024-03-22 | 北京开源芯片研究院 | Processor testing method and device, electronic equipment and readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111859638A (en) * | 2020-07-06 | 2020-10-30 | 中国人民解放军海军航空大学航空作战勤务学院 | Real-time efficient distributed virtual-real combined simulation system and construction method |
| CN115879323A (en) * | 2023-02-02 | 2023-03-31 | 西安深信科创信息技术有限公司 | Automatic driving simulation test method, electronic device and computer readable storage medium |
| CN116362198A (en) * | 2023-03-21 | 2023-06-30 | 深圳云豹智能有限公司 | Method, system, storage medium and computing device for improving chip verification efficiency |
| CN116933707A (en) * | 2023-09-15 | 2023-10-24 | 北京开源芯片研究院 | Test method, device, equipment and medium for design circuit |
-
2023
- 2023-11-20 CN CN202311551546.1A patent/CN117271374A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111859638A (en) * | 2020-07-06 | 2020-10-30 | 中国人民解放军海军航空大学航空作战勤务学院 | Real-time efficient distributed virtual-real combined simulation system and construction method |
| CN115879323A (en) * | 2023-02-02 | 2023-03-31 | 西安深信科创信息技术有限公司 | Automatic driving simulation test method, electronic device and computer readable storage medium |
| CN116362198A (en) * | 2023-03-21 | 2023-06-30 | 深圳云豹智能有限公司 | Method, system, storage medium and computing device for improving chip verification efficiency |
| CN116933707A (en) * | 2023-09-15 | 2023-10-24 | 北京开源芯片研究院 | Test method, device, equipment and medium for design circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117743059A (en) * | 2024-02-18 | 2024-03-22 | 北京开源芯片研究院 | Processor testing method and device, electronic equipment and readable storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111221559B (en) | Application updating method, device, storage medium, terminal and server | |
| CN117271374A (en) | Simulation test method, device and equipment for chip and storage medium | |
| US11119747B2 (en) | System and method for application release orchestration and deployment | |
| CN109684112B (en) | Program file operation method, device, terminal and storage medium | |
| CN116069612A (en) | Abnormality positioning method and device and electronic equipment | |
| CN111209195B (en) | Method and device for generating test case | |
| CN112395192A (en) | Information processing method and device | |
| CN110209401B (en) | Application program loading method and device | |
| CN113626321B (en) | Bridging test method, device, system and storage medium | |
| CN115729609A (en) | Configuration library information normalization checking method, device, equipment and storage medium | |
| CN113467854B (en) | Application program starting method and device, electronic equipment and storage medium | |
| CN115563156A (en) | Method, device and equipment for checking stream data information and storage medium | |
| CN112631695B (en) | Data verification method and device, electronic equipment and storage medium | |
| CN112395138B (en) | Method and device for checking parameters | |
| CN111596980B (en) | Information processing method and device | |
| CN114201484A (en) | Information processing method, information processing device, electronic equipment and storage medium | |
| CN111597106A (en) | Point burying management method and device | |
| CN109933357B (en) | Application program upgrading method and device | |
| CN112306883A (en) | Software testing method, device and medium | |
| CN110311968B (en) | Method and device for loading file in streaming mode and intelligent equipment | |
| CN116450534B (en) | Method, device, equipment and medium for generating mobile terminal application program | |
| CN109739763B (en) | Code segment operation method, device, terminal and storage medium | |
| CN116431401A (en) | Test method, test device and storage medium | |
| CN111367787B (en) | Method and device for checking leakage of page script object in application | |
| US20240201973A1 (en) | Accelerating software change requests in deployment pipelines |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |