CN117255981A - Synchronization and SYSREF windowing without glitches and occurrence scheme - Google Patents

Abstract

In an example, a system (400) is adapted to be coupled to a load device having a load clock. The system (400) includes a clock generation device having a pin (102). The system (400) also includes a capture circuit (304) coupled to the (102) pin and operable to sample a value at the pin (102). The system (400) includes a D flip-flop (306) having a data input (316) coupled to the capture circuit (304), a clock input (318) coupled to a clock, and having an output (320), wherein the D flip-flop (306) is operable to provide a system reference event (SYSREF) signal at the output (320) to align the load clock to the clock based at least in part on the value at the pin (102).

Description

Synchronization and SYSREF windowing without glitches and occurrence scheme

Background

The clock generation/distribution means is adapted to generate/distribute signals having a wide range of frequencies for various applications. As one example, a clock generation/distribution device may provide a clock reference signal to a plurality of load devices. The system reference event (SYSREF) signal may be adapted to align a load clock in a load device. For example, the SYSREF signal may be a periodic signal that is sampled by a device (e.g., an analog-to-digital converter ADC) and used to align boundaries of a local multi-frame clock used by the device.

For high frequency synchronization, windowing may be used to determine the position of the SYSREF signal relative to the clock edge and generate delayed SYSREF copies within the appropriate timing window. In addition, the load device may request a SYSREF signal from the clock generation/distribution device.

Disclosure of Invention

In some examples, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generating device having pins. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, wherein the D flip-flop is operable to provide a system reference event (SYSREF) signal at the output to align the load clock to the clock based at least in part on the value at the pin.

In some examples, a method includes performing sampling of a value at a user interface of a clock generation device. The method includes entering a windowing mode in response to the value being a first value. The method also includes determining a position of a Synchronization (SYNC) signal or a SYSREF signal request relative to a clock. The method includes programming a register to delay the SYNC signal or SYSREF request.

In some examples, a method includes performing a first sampling of a value at a user interface of a clock generation device. The method also includes entering a capture mode in response to the value being a first value. The method includes performing a second sampling of values at the user interface. The method also includes entering a synchronous mode or a SYSREF signal request mode in response to the value of the second sample.

Drawings

Fig. 1 is a block diagram of a single pin synchronization and SYSREF windowing and generation system in some examples.

Fig. 2 is a flow chart of a method for single pin synchronization and SYSREF windowing and occurrence in some examples.

Fig. 3A is a schematic diagram of a system for providing simultaneous windowing and SYSREF occurrence in some examples.

Fig. 3B is a timing diagram for providing waveforms for simultaneous windowing and SYSREF occurrences in some examples.

Fig. 4A is a schematic diagram of a system for providing simultaneous windowing, SYSREF occurrence, and synchronization without glitches in some examples.

Fig. 4B is a timing diagram of waveforms used in some examples to provide simultaneous windowing, SYSREF occurrence, and synchronization without glitches.

Fig. 5 is a circuit diagram of an evaluation trigger for a windowing scheme in some examples.

Fig. 6 is a circuit diagram of a windowing circuit in some instances.

FIG. 7 is a flow chart of a method for performing a windowing operation in some instances.

Fig. 8 is a flow diagram of a method for entering a synchronization and SYSREF request mode using a single pin interface in some examples.

The same reference numbers or other reference indicators will be used throughout the drawings to refer to the same or like features (functionally and/or structurally).

Detailed Description

The clock generation/distribution device may provide clock reference signals to a plurality of load devices in various applications (e.g., ADC, radio Frequency (RF) receiver, RF transmitter, cellular base station transmitter, wireless backhaul, etc.). A load device (e.g., an electronic component within a chip) may send a request to a source device (e.g., a clock generation/distribution component within a chip) for a SYSREF signal. After receiving the request, the source device sends a SYSREF signal to the load device or devices. The load device uses the SYSREF signal to align a local load clock in the load device. The clock generation device may also require Synchronization (SYNC) operations to maintain a deterministic relationship between the clock signal and the SYSREF signal. The internal circuitry of the source device synchronizes to the clock edge without any setup or hold violations, so SYSREF can be provided deterministically to the load device. In some clock generation/distribution devices, one device pin is used for SYNC and the other pin is used for SYSREF generation control. However, two pins may not be used on pin limited devices (e.g., a 40 pin RF multiplier/buffer/divider, or a 40 pin or 48 pin frequency synthesizer chip).

In the examples herein, a single pin interface provides both SYNC and SYSREF occurrence control. The pin functions may be programmed through any device communication interface (e.g., serial peripheral interface). In addition, a windowing scheme is described herein that provides SYNC and SYSREF occurrences at high frequencies for multi-device synchronization. Windowing determines the position of the SYSREF signal relative to the clock edge of the internal clock and provides a delayed replica of the SYSREF signal within a reliable window to avoid setup and hold violations. Windowing may be performed concurrently with SYSREF occurrence without glitches being generated at the output. Simultaneous windowing and SYSREF occurrence provides flexibility in assessing the position of the synchronization signal relative to the clock without disturbing the SYSREF output. In addition, the output may be muted during synchronization to allow SYSREF to be provided to the load device without glitches.

Fig. 1 is a block diagram 100 of a single pin synchronization and SYSREF windowing and generation system in some examples herein. The system includes a single pin 102 interface that is programmable by decoder 103 to provide SYSREF for windowing 104 or capture 106. Capturing means sampling the signal on the pin at a specified time, for example, on a rising edge without any set-hold violations. In capture mode, a synchronization 108 or SYSREF request 110 may be performed. Decoder 103 may be any suitable hardware and/or software that provides a device mode for a clock generation/distribution device. In one example, decoder 103 includes a two-bit interface represented by bits 112A and 112B. In this example, bit 112A is the Most Significant Bit (MSB) and bit 112B is the Least Significant Bit (LSB). The user may use bits 112A and 112B to place the clock generation/distribution device in a particular mode.

As described above, two bits may be written to select the device mode. For example, the MSB (e.g., bit 112A) set to 1 may select the window 104. Windowing is performed with a location register as described below. The MSB set to 0 may select capture 106. Then, a second bit (e.g., 112B) may select between sync 108 and SYSREF request 110 after entering capture mode. The synchronization process is described below. The SYSREF request provides a SYSREF signal to the load device, as described below. In some examples, the term "pin" is generally used to designate a connector to another device (e.g., a pin used on a pin grid array, a wire on a leadframe, a ball on a ball grid array, or any other connection that may be used to connect one device to another device, such as an integrated circuit).

Fig. 2 is a flow chart of a method 200 for single pin synchronization and SYSREF windowing and occurrence in some examples herein. Method 200 is one example of a process described herein. The steps of method 200 may be performed in any suitable order.

The method 200 begins at 210 where a device mode is received by a clock generation/distribution device. The device mode may be communicated from the user via two bits (e.g., bits 112A and 112B). For example, the MSB may select between windowing 104 or capturing 106 based on the value of the MSB.

The method 200 continues at 220, where a low (0) to high (1) on the MSB 112A may indicate windowing 104. The method 200 then continues at 230, where windowing is performed. The location register may be updated and the select register programmed, as described below. This process determines the position of the SYSREF signal relative to the input clock edge and provides a delayed replica of the SYSREF signal. The select register may be programmed to delay the SYSREF signal based on the position of the SYSREF signal so that the set and hold timings are satisfied. An example windowing scheme is described below.

The method 200 continues at step 240, where the user may un-program a pin of the clock generation/distribution device (e.g., pin 102) and set the mode to capture via the MSB (e.g., bit 112A) going from high to low. Next, the device mode switches to a Synchronization (SYNC) mode, where LSB (e.g., 112B) is (0) on. The method 200 continues at 250 where the device is synchronized without a setup or hold problem.

The method 200 continues at 260, where the device is switched to the request mode. The device may switch by un-programming the two bit interface (e.g., 112A and 112B), setting the mode to capture via MSB 112A, and then switching to the request mode and low (0) to high (1) on the LSB. After entering request mode, the method may enable the SYSREF output by setting pin 102 from low (0) to high (1) at 270. At 280, the method may mute the SYSREF output by setting pin 102 from high (1) to low (0). In the present example, the output is not disturbed by switching between modes using, for example, decoder 103. In addition, the user may return to the windowed mode after the request mode using a user interface such as decoder 103 without disturbing the output.

Frequent windowing is suitable for high frequency synchronization, where the SYNC and SYSREF request (SYSREFREQ) pulses (referred to as SYNC/SYSREFREQ pulses) and the relative position of the clocks vary, for example, with respect to temperature. In the present example, windowing may be performed concurrently with SYSREF occurrence without glitches being generated at the output. In addition, the output is muted during synchronization to allow the SYSREF to be provided to the load device without glitches.

Fig. 3A is a schematic diagram of a system 300 for providing simultaneous windowing and SYSREF occurrences in some examples herein. System 300 includes pin 102, capture circuit 304, AND gate 305, flip-flop 306, AND SYSREF generation block 308 (e.g., a SYSREF generator). AND gate 305 includes a first input 310, a second input 312, AND an output 314. Flip-flop 306 includes a D input 316, a clock input 318, and an output 320 (also referred to herein as Q1).

In an example, the clock generation/distribution device is in a request mode (e.g., SYSREF request 110), which is the non-windowed mode described above. In operation, a signal (e.g., CTRL) on pin 102 is captured by capture circuit 304, which provides a signal CTRL_capt to flip-flop 306. The capture circuit 304 helps to deterministically sample the CTRL signal presented by the user on the rising edge of CLK. The CTRL signal is not shown in fig. 3B, but ctlr_capt may appear as a slightly delayed CTRL signal, depending on the time at which the rising edge of CLK occurs for the samples. In the non-windowed mode, the CTRL_capt signal is sampled on a clock edge by the flip-flop 306 and provided to the SYSREF generation block 308. The SYSREF generation block 308 provides the SYSREF output to the load device. Thus, if a high (1) signal is provided to pin 102, the SYSREF output is provided by SYSREF generation block 308. If a low (0) signal is provided to pin 102 while in the request mode, the SYSREF output is muted.

In the non-windowed mode as described above, the WINDOW signal is low (0) to indicate the non-windowed mode. Thus, WINDOW applied to the first input 310 of AND gate 305 is high (1). If WINDOW is high (1), then the clock signal CLK at the second input 312 is provided to the clock input 318 of the flip-flop 306 and the signal at the pin 102 is provided to the output 320 of the flip-flop 306. If the system switches to windowed mode (e.g., by a user command), the WINDOW signal goes high (1) and WINDOW goes low (0). The clock input 318 of flip-flop 306 thus stops receiving the CLK signal. Without the CLK signal, the change on pin 102 would not be captured by flip-flop 306, as the flip-flop would not sample the input. Output 320 remains at its previous value and will not update until the device is again programmed to the request mode and flip-flop 306 begins receiving the CLK input again. Thus, if WINDOW is high (1), windowing may be performed without any glitch at the output. In some examples, to avoid transition glitches, the state of pin 102 is made the same in response to returning to the request mode as it was initially when the mode was switched from request to windowing.

Fig. 3B is a timing diagram for providing waveforms 350 for simultaneous windowing and SYSREF occurrences in some examples herein. Waveform 350 describes the operation of system 300 described above with respect to fig. 3A. Waveform 350 includes pattern 352, CTRL_capt 354, Q1 356, and SYSREF output 358. Mode 352 indicates a mode of clock generation/distribution device operation, which in one example may be set via MSB 112A. CTRL_capt 354 is the CTRL signal captured on the rising edge (at pin 102 in FIG. 3A). Q1 is the output 320 of flip-flop 306 as described above. SYSREF output 358 is the output of SYSREF generation block 308, which may be provided at an SYSREF output pin on the chip in some examples.

The mode 352 shows the mode set by the user as described above, either Request (REQ) mode or Window (WIN) mode. At time t ₁ In request mode, ctrl_capt 354 goes high (1), and thus Q1 356 goes high (1). In response to Q1 356 going high, SYSREF output 358 goes high at time t ₁ And then provided by SYSREF generation block 308. At time t ₂ The mode 352 changes from REQ to WIN. At time t ₂ Thereafter, the SYSREF output 358 continues. Thus, the windowed mode may be entered without glitches at the SYSREF output 358. CTRL_CapT 354 at time t ₃ From high (1) to low (0), but as such the SYSREF output 358 is unaffected. Thus, as shown in fig. 3B, in windowed mode, SYSREF output 358 is unaffected even if ctrl_capt 354 changes state from high (1) to low (0) or from low (0) to high (1).

At time t ₄ Mode 352 changes to the request mode. Thus, when in request mode, the change in CTRL_capt 354 propagates to Q1 356 and affects SYSREF output 358. At time t ₅ Mode 352 is in the request mode and CTRL_capt 354 changes from high (1) to low (0). Thus, Q1 356 also goes from high (1) to low (0). After Q1 356 goes low (0), SYSREF output 358 is muted and goes to zero. At time t ₆ A second windowing mode is entered as shown in mode 352. During the second windowing mode, the SYSREF output 358 is likewise unaffected and remains squelched. To re-open the SYSREF output 358, ctrl_capt 354 transitions from low (0) to high (1) when in the request mode for mode 352.

Fig. 4A is a schematic diagram of a system 400 for providing simultaneous windowing and SYSREF occurrences in some examples herein. The system 400 also includes a glitch-free SYSREF output due to the sampled_ctrl signal SAMPLED on the negative edge of the SYSREF CLK signal during synchronization, as described below. In fig. 4A, the same reference numerals or other reference indicators as in fig. 3A are used to denote (functionally and/or structurally) the same or similar features. Fig. 4A includes the components of fig. 3A, AND also includes AND gate 402, SYNC GEN 404, flip-flop 406, AND gate 408.AND gate 402 includes an input 410, an input 412, AND an output 414. Flip-flop 406 includes a D input 416, a clock input 418, and an output 420 (also referred to herein as Q2). AND gate 408 includes an input 422, an input 424, AND an output 426.

The components from fig. 3A operate similarly as described above with respect to fig. 3A. Referring again to fig. 4A, output 320 (Q1) is provided to input 410 of AND gate 402. An input 412 of the AND gate 402 is coupled to a SYNC signal (which indicates whether the device is in SYNC mode). The SYNC pattern may be set through a two-bit interface represented by bits 112A and 112B. If the device is in SYNC mode, SYNC is low (0) AND the output of AND gate 402 is low (0). Thus, the sample_ctrl signal is low (0). If the SAMPLED_CTRL signal is low (0), then Q2 is low (0). In this example, the SYSREF output at output 426 is also low (0), meaning that the output remains squelched while the device is in SYNC mode. In the SYNC mode, the next low (0) to high (1) signal on pin 102 is used to synchronize the SYSREF divider, as described below with respect to FIG. 4B. The operation synchronizes the SYSREF signal. In addition, SYNC GEN 404 is "on" only in the SYNC pattern. In one example, there is a sufficient delay between programming the device to the SYNC pattern and providing the SYNC pulse to allow the device to mute the SYSREF.

If the device is in request mode, SYNC is high (1). If SYNC is high, SAMPLED_CTRL is set to the value Q1 at output 320. SYNC is also high (1) in the windowing mode, and sampledctrl is also set to the value Q1 under this condition. The flip-flop 406 samples the falling edge (e.g., high to low transition) of the signal at the clock input 418. The SYSREF generation block 308 receives a reset signal from the SYNC GEN 404 in a SYNC mode that synchronizes the frequency divider in the SYSREF generation block 308. In request mode, the SYSREF generation block 308 provides a SYSREF output, and the data in flip-flop 406 is sampled on the negative edge of this signal from SYSREF generation block 308. The SYSREF signal is provided at output 426 (e.g., the SYSREF output).

Fig. 4B is a timing diagram of waveforms 450 used in some examples herein to provide simultaneous windowing and SYSREF occurrence and synchronization without glitches. Waveform 450 describes the operation of system 400 described above with respect to fig. 4A. Waveform 450 includes Clock (CLK) 451, mode 452, CTRL 453, ctrl_capt 454, sampled_ctrl 456, Q2 458, sysref_clk 460, and SYSREF output 462.

Mode 452 shows whether the device is in a Request (REQ) mode or a Synchronization (SYNC) mode. In request mode, at time t ₁ High (1) on pin 102 (indicated by CTRL 453) provides: the low (0) to high (1) transition of the CTRL_capt signal 454 and the SAMPLED_CTRL signal 456; SYSREF_CLK 460 starts; and SYSREF output 462 begins. At time t ₂ Mode 452 changes from request to SYNC (e.g., low (0) to high (1)), and sampled_ctrl 456 goes low (0). Due to events at the system level, SYSREF_CLK (460) may become unsynchronized (with respect to another device or with respect to its own CLK output clock). Thus, to resynchronize, the device is placed in SYNC mode (452). In SYNC mode, after sample_ctrl 456 goes low (0), Q2 458 goes low (0) on the negative edge of sysref_clk and SYSREF output 462 is muted without any glitches.

In SYNC mode, since the user provides a signal (e.g., CTRL 453) at pin 102, ctrl_capt 454 is at time t ₃ Becomes high(1). This signal (CTRL 453) is a request by the user to perform synchronization. SYSREF output 462 at time t ₃ The squelch is maintained. Synchronization is performed by SYNC GEN 404. As shown in fig. 4B, SYSREF CLK 460 at time t ₃ Synchronized to CLK 451.

SYNC GEN 404 provides a synchronization pulse that resets the divider in SYSREF generation block 308. If the device is in request mode, the Q1 signal indicates to SYSREF generation block 308 whether the SYSREF CLK signal is required or whether it is to be muted. In the SYNC mode, signal Q1 is first provided to SYNC GEN 404, which provides a low (0) to high (1) synchronization pulse. This low (0) to high (1) synchronization pulse resets the divider in SYSREF generation block 308. Resetting these dividers aligns SYSREF CLK to the master output clock (e.g., reference clock signal).

If SYNC GEN 404 provides a low (0) output to SYSREF generation block 308, SYSREF generation block 308 will not be reset. SYNC GEN 404 transmits signal transitions only in SYNC pattern. In either the request mode or the windowing mode, SYNC GEN 404 provides a low (0) output.

As described above, system 400 provides for simultaneous windowing and SYSREF occurrence, as well as synchronization without glitches. Modifications may be made to system 400 to provide these functions and still fall within the scope of the present description.

Fig. 5 is a circuit diagram 500 of an evaluation trigger for a windowing scheme in some examples herein. Circuit diagram 500 is one component of an example windowing scheme described below with respect to fig. 6. The circuit diagram 500 produces as output a position calculation. Circuit diagram 500 includes AND gate 502 AND flip-flop 504. The AND gate 502 has a first input 506 AND a second input 508. The AND gate has an output 510 coupled to the flip-flop 504. The flip-flop 504 has a D input 512, a Clock (CLK) input 514, and a Q output 516 coupled to the second input 508.

In operation, the inverted output of Q output 516 is provided to AND gate 502. If the CTRL_DEL signal at the first input 506 is initially low (0), then the input provided to the D input 512 is low (0). The output of Q output 516 remains low (0). The Q output 516 remains low (0) until CTRL_DEL goes high (1). After CTRL_DEL goes high (1), the Q output 516 will switch and also generate a position calculation at 510. This circuitry allows windowing to be performed without setting any input or initial value for the windowing circuitry, which is described below with respect to fig. 6.

Fig. 6 is a circuit diagram of a windowing circuit 600 in some examples herein. Windowing circuit 600 is one example of a windowing circuit, but in other examples, windowing may be performed using any suitable technique. Windowing determines the position of the SYSREF signal relative to the rising edge of the input clock and provides a delayed replica of the SYSREF signal within a reliable window. The windowing circuit 600 includes AND gates 502a, 502b, 502c … (collectively or individually referred to as AND gates 502), AND flip-flops 504a, 504b, 504c … (collectively or individually referred to as flip-flops 504). The windowing circuit 600 also includes delay buffers 602a, 602b, 602c … (collectively or individually referred to as delay buffers 602), flip-flops 604a, 604b, 604c … (collectively or individually referred to as flip-flops 604), exclusive-or (XOR) gates 606a, 606b, 606c … (collectively or individually referred to as XOR gates 606), and a Clock (CLK) input 608. Windowing circuit 600 includes a first XOR input 610, a second XOR input 612, OR gates 614a, 614b … (collectively OR individually referred to as OR gates 614), and a SYSREF input 616.

The windowing circuit 600 includes a plurality of serially coupled delay buffers 602a, 602b, 602c … (collectively or individually referred to as delay buffers 602). Although five delay buffers 602 are shown, any number may be used in other examples. The windowing circuit 600 includes a plurality of flip-flops 604. In this example, each flip-flop 604 is a D flip-flop. Windowing circuit 600 generally includes one flip-flop 604 for each delay buffer 602. Each delay buffer 602 introduces a delay of a fixed amount of time between its input and output. The SYSREF signal is provided to an input of the first delay buffer 602a via a SYSREF input 616. Delay buffer 602 may be any passive or active element that transmits a signal with a delay. For example, a buffer may be used as delay buffer 602, where the buffer is positive phase. The delay buffer 602 may have a static delay or a configurable delay. The SYSREF is provided to a delay buffer 602a, which generates a delayed version of the SYSREF on its output. The delayed SYSREF from delay buffer 602a is provided to the input of the next delay buffer 602b in the series chain of delay buffers 602, and delay buffer 602b adds an additional delay to the SYSREF. Thus, the output of delay buffer 602 provides SYSREF with varying degrees of time delay.

In this example, each flip-flop 604 includes a data input (D) and an output (Q). The clock input of each flip-flop 604 receives a clock signal (CLK) at a clock input 608. In response to the active edge of CLK (assumed to be a rising edge in this example), each flip-flop 604 latches the logic value present on its D input to its Q output.

The windowing circuit 600 also includes an AND gate 502 AND a flip-flop 504. These components are described above with respect to fig. 5. Flip-flops 604 and 504 are clocked with the same clock signal CLK. Each flip-flop 504 includes a data (D) input and a Q output. As shown, each AND gate 502 includes two inputs, one of which is coupled to a corresponding delay buffer 602 AND the other of which is coupled to the inverted Q output of a corresponding flip-flop 504. Each AND gate 502 provides a signal on its output that is the AND result of the corresponding delayed SYSREF AND the inverted Q output of the corresponding flip-flop 504. The output from AND gate 502 is provided to the D input of a corresponding flip-flop 504.

The windowing circuit 600 also includes an exclusive OR (XOR) gate 606 and an OR gate 614. Each XOR gate 606 includes two inputs 610 and 612.XOR gate 606b has two example inputs 610 and 612. Inputs 610 and 612 of XOR gate 606b are coupled to inputs of adjacent XOR gates 606a and 606c, respectively. The outputs of adjacent XOR gates 606 are then OR-operated together as shown by OR gate 614. The output of OR gate 614 is adapted to identify an edge of CLK at clock input 608 and is designated SYSREF POS n, where n is equal to 0, 1, 2. These values may be stored in location registers. The location register indicates how far the SYSREF edge is from the clock edge. At the XOR gate 606 associated with the delay buffer 602 in which the clock transition occurs, a high (1) value is output from the XOR gate 606 and provided to two OR gates 614 coupled to the XOR gate 606. The SYSREF_POS value at the output of these two OR gates 614 is high (1) and the other SYSREF_POS values are low (0). The location register stores these SYSREF_POS values and retains them. The select register may be programmed to delay the SYSREF signal according to its location (e.g., the sysref_pos value) so that the set and hold timings are met.

Fig. 7 is a flow chart of a method 700 for performing a windowing operation in some examples herein. The steps of method 700 may be performed in any suitable order. The hardware components described above with respect to fig. 4A may perform the method 700 in some examples.

The method 700 begins at 710, where capture circuitry performs sampling of values at a user interface of a clock generation/distribution device. In one embodiment, the value at the user interface may be set by the user.

The method 700 continues at 720, where in response to the value being a first value, the device enters a windowing mode. Method 700 continues at 730, where the windowing operation determines the location of a SYNC signal or SYSREF request at a pin of the device relative to the clock. In one example, the location may be determined by circuitry such as windowing circuit 600.

Method 700 continues at 740 with a register programmed to delay the SYNC signal or SYSREF request at a pin of the device. The registers may be programmed as described above with respect to fig. 6.

Fig. 8 is a flow chart of a method 800 for entering a synchronization and SYSREF request mode using a single pin interface in some examples herein. The steps of method 800 may be performed in any suitable order. The hardware components described above with respect to fig. 4A may perform the method 800 in some examples.

The method 800 begins at 810, where capture circuitry performs a first sampling of a value at a user interface of a clock generation/distribution device, such as bit 112A. In one embodiment, the value at the user interface may be set by the user.

The method 800 continues at 820, where in response to the value being a first value, the device enters a capture mode. The method 800 continues at 830 where the capture circuitry performs a second sampling of the value at the user interface. The value at the user interface may be set by the user (e.g., two bits of 112A and 112B). Method 800 continues at 840, where in response to the second sampled value, the device enters a synchronous mode or a SYSREF request mode. As described above, the synchronization operation or SYSREF output may be provided to the device via a single pin input.

The examples herein provide that simultaneous windowing and SYSREF occur without glitches at the output. The examples herein also mute the output during SYNC to prevent glitches in the SYSREF output. A single pin provides the functionality described herein, which makes the example suitable for pin-limited devices. The synchronization signal may reference the high frequency clock using a windowing scheme. The examples herein provide 2-bit programmability via a user interface for switching between SYNC, windowing, and SYSREF occurrence modes.

The term "coupled" is used throughout this specification. The terms may encompass a connection, communication, or signal path that achieves a functional relationship consistent with the specification. For example, if device a provides a signal to control device B to perform an action, in a first example, device a is coupled to device B, or in a second example, if intermediate component C does not substantially change the functional relationship between device a and device B such that device B is controlled by device a via the control signal provided by device a, device a is coupled to device B through intermediate component C. Although some elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some of the features illustrated as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) incorporated in/on a semiconductor substrate; (ii) incorporated into a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board. As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnections between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components, or their ends.

A device "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) to perform the function when manufactured by a manufacturer, and/or may be configurable (or reconfigurable) by a user after manufacture to perform the function and/or other additional or alternative functions. The configuration may be programmed by firmware and/or software of the device, by the construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

Unless otherwise stated, "about," "about," or "substantially" preceding a value means +/-10% of the stated value. Modifications of the described examples are possible and other examples are possible within the scope of the claims.

Claims (20)

1. A system adapted to be coupled to a load device having a load clock, the system comprising:

a clock generating device having pins;

a capture circuit coupled to the pin and operable to sample a value at the pin; and

a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, wherein the D flip-flop is operable to provide a system reference event (SYSREF) signal at the output to align the load clock to the clock based at least in part on the value at the pin.

2. The system of claim 1, wherein the value at the pin is a first value and the clock generation means is operable to mute the SYSREF signal in response to the value at the pin being a second value.

3. The system of claim 1, further comprising:

an AND gate coupled to the clock input, wherein the AND gate includes a first input coupled to the clock, a second input coupled to an interface indicating a windowing mode, AND wherein the AND gate is operable to block the clock from the D flip-flop during the windowing mode.

4. The system of claim 3, wherein the D flip-flop is operable to provide the SYSREF signal at the output after the clock generating device switches from a non-windowed mode to the windowed mode.

5. The system of claim 3, wherein the capture circuit is operable to not sample the value on the pin during the windowing mode.

6. The system of claim 1, wherein the D flip-flop is a first D flip-flop, and the system further comprises:

an AND gate coupled to the output of the first D flip-flop;

a second D flip-flop coupled to an output of the AND gate; and

a SYSREF generator coupled to the output of the AND gate, wherein the SYSREF generator is operable to generate the SYSREF signal.

7. The system of claim 6, further comprising:

a synchronization generator coupled to the output of the first D flip-flop, wherein an output of the synchronization generator is coupled to the SYSREF generator, and wherein the synchronization generator is operable to synchronize the SYSREF generator.

8. The system of claim 7, wherein a synchronization signal indicates a synchronization mode and the synchronization generator is operable to activate in the synchronization mode.

9. The system of claim 8, wherein the AND gate is operable to receive a zero value at an input during the synchronous mode.

10. The system of claim 8, wherein the SYSREF signal is muted during the synchronization mode.

11. A method, comprising:

performing a sampling of values at a user interface of the clock generation apparatus;

responsive to the value being a first value, entering a windowing mode;

determining a position of a Synchronization (SYNC) signal or a system reference event (SYSREF) signal request relative to a clock; and

the register is programmed to delay the SYNC signal or SYSREF request.

12. The method as recited in claim 11, further comprising:

the location of the SYSREF request is determined via a series of delay buffers.

13. The method as recited in claim 11, further comprising:

the SYSREF request is provided during the windowed mode.

14. The method as recited in claim 11, further comprising:

performing a second sampling of the value at the user interface;

in response to the value being a second value, entering a synchronous mode; and

the SYSREF signal is muted in the synchronization mode.

15. A method, comprising:

performing a first sampling of values at a user interface of the clock generation apparatus;

in response to the value being a first value, entering a capture mode;

performing a second sampling of values at the user interface; and

in response to the value of the second sample, a synchronous mode or a system reference event (SYSREF) signal request mode is entered.

16. The method as recited in claim 15, further comprising:

in response to entering the SYSREF signal request mode, a SYSREF signal is provided to a load device.

17. The method as recited in claim 16, further comprising:

the SYSREF signal is muted in response to performing a third sampling of the value at the user interface.

18. The method as recited in claim 15, further comprising:

in response to entering the sync mode, the SYSREF signal is muted.

19. The method as recited in claim 15, further comprising:

in response to entering the synchronization mode, the SYSREF signal is synchronized with a reference clock signal.

20. The method as recited in claim 19, further comprising:

the synchronization mode is exited in response to another sampling of the value at the user interface being performed.